General Description
The MAX9324 low-skew, low-jitter, clock and data driver
distributes a differential LVPECL input to four differential
LVPECL outputs and one single-ended LVCMOS output.
All outputs default to logic low when the differential inputs
equal GND or are left open. The MAX9324 operates from
3.0V to 3.6V, making it ideal for 3.3V systems, and consumes only 25mA (max) of supply current.
The MAX9324 features low 150ps (max) part-to-part
skew, low 15ps output-to-output skew, and low 1.7ps
RMS jitter, making the device ideal for clock and data
distribution across a backplane or board. CLK_EN and
SEOUT_Z control the status of the various outputs.
Asserting CLK_EN low configures the differential (Q_,
Q_) outputs to a differential low condition and SEOUT to
a single-ended logic-low state. CLK_EN operation is
synchronous with the CLK_ inputs. A logic high on
SEOUT_Z places SEOUT in a high-impedance state.
SEOUT_Z is asynchronous with the CLK (CLK) inputs.
The MAX9324 is available in space-saving 20-pin
TSSOP and ultra-small 20-pin 4mm ✕ 4mm thin QFN
packages and operates over the extended (-40°C to
+85°C) temperature range.
Applications
Precision Clock Distribution
Low-Jitter Data Repeater
Data and Clock Driver and Buffer
Central-Office Backplane Clock Distribution
DSLAM Backplane
Base Station
ATE
Features
♦ 15ps Differential Output-to-Output Skew
♦ 1.7ps
RMS
Added Random Jitter
♦ 150ps (max) Part-to-Part Skew
♦ 450ps Propagation Delay
♦ Synchronous Output Enable/Disable
♦ Single-Ended Monitor Output
♦ Outputs Assert Low when CLK, CLK are Open or
at GND
♦ 3.0V to 3.6V Supply Voltage Range
♦ -40°C to +85°C Operating Temperature Range
MAX9324
One-to-Five LVPECL/LVCMOS Output Clock and
Data Driver
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
19-2576; Rev 0; 10/02
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Functional Diagram and Typical Operating Circuit appear at
end of data sheet.
Pin Configurations
*Future product—Contact factory for availability.
**EP = Exposed paddle.
PART TEMP RANGE PIN-PACKAGE
MAX9324EUP -40°C to +85°C 20 TSSOP
MAX9324ETP* -40°C to +85°C 20 Thin QFN-EP**
N.C.
CLK_EN
TOP VIEW
1
SEOUT
2
GND
3
N.C.
4
SEOUT_Z
5
CLK
THIN QFN-EP** (4mm x 4mm)
**CONNECT EXPOSED PADDLE TO GND.
GNDQ0Q0
1617181920
MAX9324
**EXPOSED PADDLE
678910
CLK
CC
V
CC
Q3
Q3
V
1
GND
2
V
15
CC
Q1
14
Q1
13
12
Q2
11
Q2
CLK_EN
N.C.
GND
N.C.
SEOUT_Z
CLK
CLK
3
4
MAX9324
5
6
7
8
9
10Q3V
CC
TSSOP
Q0
20
19
Q0
V
18
CC
17
Q1SEOUT
16
Q1
15
Q2
14
Q2
13
V
CC
12
11
Q3
MAX9324
One-to-Five LVPECL/LVCMOS Output Clock and
Data Driver
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(VCC= 3.0V to 3.6V, differential outputs terminated with 50Ω ±1% to (VCC- 2V), SEOUT_Z = GND, CLK_EN = VCC, TA= -40°C to
+85°C, unless otherwise noted. Typical values are at V
CC
= 3.3V, TA= +25°C.) (Notes 1, 2, and 3)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCCto GND...........................................................-0.3V to +4.0V
Q_, Q_, CLK, CLK, SEOUT_Z, CLK_EN,
SEOUT to GND.......................................-0.3V to (V
CC
+ 0.3V)
CLK to CLK ............................................................................±3V
SEOUT Short to GND .................................................Continuous
Continuous Output Current (Q_, Q_) ..................................50mA
Surge Output Current (Q_, Q_) .........................................100mA
Continuous Power Dissipation (T
A
= +70°C)
20-Pin TSSOP (derate 11mW/°C)..............................879.1mW
20-Pin 4mm
✕ 4mm Thin QFN (derate 16.9mW/°C)..1349.1mW
Junction-to-Ambient Thermal Resistance in Still Air
20-Pin TSSOP ............................................................+91°C/W
20-Pin 4mm
✕ 4mm Thin QFN.................................+59.3°C/W
Junction-to-Case Thermal Resistance
20-Pin TSSOP ............................................................+20°C/W
20-Pin 4mm
✕ 4mm Thin QFN......................................+2°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Soldering Temperature (10s) ...........................................+300°C
SINGLE-ENDED INPUTS (CLK_EN, SEOUT_Z)
Input High Voltage V
Input Low Voltage V
Input High Current I
Input Low Current I
DIFFERENTIAL INPUT (CLK, CLK)
Differential Input High Voltage V
Differential Input Low Voltage V
Differential Input Voltage V
Input Current I
DIFFERENTIAL OUTPUTS (Q_, Q_)
Single-Ended Output High
Single-Ended Output Low
Differential Output Voltage VOH - VOLFigure 1 0.6 0.85 V
SINGLE-ENDED OUTPUT (SEOUT)
Output High Voltage V
Output Low Voltage V
Output High-Impedance Current I
Output Short-Circuit Current I
SUPPLY
Supply Current I
PARAMETER SYM B O L CONDITIONS MIN TYP MAX UNITS
IH
IL
CLK_EN = V
SEOUT_Z = V
CLK_EN = GND -150
IL
SEOUT_Z = GND -5 +5
Figure 1 1.5 V
Figure 1 0 VCC - 0.15 V
ILD
V
Figure 1 VCC - 1.4 VCC - 1.0 V
Figure 1 VCC - 2.0 VCC - 1.7 V
IOH = -4mA 2.4 V
IOL = 4mA 0.4 V
SEOUT_Z = VCC, SEOUT = VCC or GND -10 +10 µA
V
(Note 4) 25 mA
IHD
CLK
V
V
IH
IHD
ILD
- V
OH
OL
OH
OL
OZ
OS
CC
, V
IHD
ILD
= VCC, SEOUT = GND 75 mA
CLK
2V
0 0.8 V
CC
CC
-5 +5
0.15 1.5 V
-5 +150 µA
CC
150
CC
V
µA
µA
V
MAX9324
One-to-Five LVPECL/LVCMOS Output Clock and
Data Driver
_______________________________________________________________________________________ 3
Note 1: Measurements are made with the device in thermal equilibrium.
Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 3: DC parameters are production tested at T
A
= +25°C and guaranteed by design over the full operating temperature range.
Note 4: All pins open except V
CC
and GND.
Note 5: Guaranteed by design and characterization. Limits are set at ±6 sigma.
Note 6: Measured from the differential input signal crosspoint to the differential output signal crosspoint.
Note 7: Measured between the differential outputs of the same part at the differential signal crosspoint for a same-edge transition.
Note 8: Measured between the differential outputs of different parts at the differential signal crosspoint under identical conditions
for a same-edge transition.
Note 9: Jitter added to the input signal.
Note 10: Measured at 50% of V
CC
.
AC ELECTRICAL CHARACTERISTICS
(VCC= 3.0V to 3.6V, differential outputs terminated with 50Ω ±1% to (VCC- 2V), f
CLK
≤ 266MHz, input duty cycle = 50%, input transi-
tion time = 125ps (20% to 80%), V
IHD
= 1.5V to VCC, V
ILD
= GND to (VCC- 0.15V), V
IHD
- V
ILD
= 0.15V to 1.5V, CLK_EN = VCC,
SEOUT_Z = GND, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at VCC= 3.3V, V
IHD
= (VCC- 1V), V
ILD
= (VCC-
1.5V), T
A
= +25°C.) (Note 5)
(
)
(
)
(
)
PARAMETER SYM B O L CONDITIONS MIN TYP MAX UNITS
Switching Frequency f
Propagation Delay t
PHL
Output-to-Output Skew t
Part-to-Part Skew t
Output Rise Time t
Output Fall Time t
MAX
SKOO
SKPP
VOH - VOL ≥ 0.6V, SEOUT_Z = V
SEOUT_Z = GND, SEOUT 125 200
, t
CLK, CLK to Q_, Q_, Figure 1 (Note 6) 100 450 600 ps
PLH
(Note 7) 30 ps
(Note 8) 150 ps
20% to 80%, Figure 1 100 217 300 ps
R
80% to 20%, Figure 1 100 207 300 ps
F
Output Duty Cycle ODC 48 50 52 %
Added Random Jitter t
Added Deterministic Jitter
Added Jitter t
Single-Ended Output Rise Time t
Single-Ended Output Fall Time t
RJ
t
DJ
AJ
f
= 650MHz (Note 9) 1.7 3 ps
CLK
23
2e
- 1 PRBS pattern, f = 650Mbps (Note 9) 83 100 ps
VCC = 3.3V with 25mV superimposed
sinusoidal noise at 100kHz (Note 9)
CL = 15pF, 20% to 80%, Figure 1 1.6 2 ns
R
CL = 15pF, 80% to 20%, Figure 1 1.6 2 ns
F
Single-Ended Output Duty Cycle ODC (Note 10) 40 52 60 %
CC
650 800
8.5 12 ps
MHz
RMS
P-P
P-P
MAX9324
One-to-Five LVPECL/LVCMOS Output Clock and
Data Driver
4 _______________________________________________________________________________________
Typical Operating Characteristics
(VCC= 3.3V, outputs terminated to (VCC- 2V) through 50Ω, SEOUT_Z = VCC, CLK_EN = VCC, TA= +25°C.)
SUPPLY CURRENT vs. TEMPERATURE
MAX9324 toc01
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
6035-15 10
10.5
11.0
11.5
12.0
12.5
13.0
13.5
14.0
10.0
-40 85
DIFFERENTIAL OUTPUT AMPLITUDE
(V
OH
- VOL) vs. FREQUENCY
MAX9324 toc02
FREQUENCY (MHz)
OUTPUT AMPLITUDE (mV)
14001200200 400 600 800 1000
100
200
300
400
500
600
700
800
0
0 1600
DIFFERENTIAL OUTPUT RISE/FALL TIME
vs. TEMPERATURE
MAX9324 toc03
TEMPERATURE (°C)
DIFFERENTIAL OUTPUT RISE/FALL TIME (ps)
603510-15
160
170
180
190
200
210
220
230
250
240
150
-40 85
t
F
t
R
DIFFERENTIAL PROPAGATION DELAY
vs. TEMPERATURE
MAX9324 toc04
TEMPERATURE (°C)
DIFFERENTIAL PROPAGATION DELAY (ps)
603510-15
420
430
440
450
460
470
480
490
500
510
410
-40 85
t
PHL
t
PLH
MAX9324
One-to-Five LVPECL/LVCMOS Output Clock and
Data Driver
_______________________________________________________________________________________ 5
Pin Description
PIN
TSSOP QFN
1, 5 2, 18 GND Ground. Provide a low-impedance connection to the ground plane.
2 19 CLK_EN
3, 6 3, 20 N.C. No Connect. Not internally connected.
4 1 SEOUT
7 4 SEOUT_Z
8 5 CLK
96CLK
10, 13, 18 7, 10, 15 V
11 8 Q3 Inverting Differential LVPECL Output. Terminate Q3 to (VCC - 2V) with a 50Ω ±1% resistor.
12 9 Q3 Noninverting Differential LVPECL Output. Terminate Q3 to (VCC - 2V) with a 50Ω ±1% resistor.
14 11 Q2 Inverting Differential LVPECL Output. Terminate Q2 to (VCC - 2V) with a 50Ω ±1% resistor.
15 12 Q2 Noninverting Differential LVPECL Output. Terminate Q2 to (VCC - 2V) with a 50Ω ±1% resistor.
16 13 Q1 Inverting Differential LVPECL Output. Terminate Q1 to (VCC - 2V) with a 50Ω ±1% resistor.
17 14 Q1 Noninverting Differential LVPECL Output. Terminate Q1 to (VCC - 2V) with a 50Ω ±1% resistor.
19 16 Q0 Inverting Differential LVPECL Output. Terminate Q0 to (VCC - 2V) with a 50Ω ±1% resistor.
20 17 Q0 Noninverting Differential LVPECL Output. Terminate Q0 to (VCC - 2V) with a 50Ω ±1% resistor.
NAME FUNCTION
Synchronous Output Enable. Connect CLK_EN to V
differential outputs. Connect CLK_EN to GND to disable the differential outputs. When
disabled, Q_ asserts low, Q_ asserts high, and SEOUT asserts low. A 51kΩ pullup resistor to
V
allows CLK_EN to be left floating.
CC
LVCMOS/LVTTL Clock Output. SEOUT reproduces CLK when SEOUT_Z = GND. SEOUT
goes high impedance when SEOUT_Z = VCC. The maximum output frequency of SEOUT is
125MHz.
Single-Ended Clock Output Enable/Disable. Connect SEOUT_Z to GND to enable the singleended clock output. Connect SEOUT_Z to V
51kΩ pulldown resistor to GND allows SEOUT_Z to be left floating.
Noninverting Differential LVPECL Input. An internal 51kΩ pulldown resistor to GND forces the
outputs (Q_, Q_) to differential low and logic low (SEOUT) when CLK and CLK are left open or
at GND and the outputs are enabled.
Inverting Differential LVPECL Input. An internal 51kΩ pulldown resistor to GND forces the
outputs (Q_, Q_) to differential low and logic low (SEOUT) when CLK and CLK are left open or
at GND and the outputs are enabled.
Positive Supply Voltage. Bypass VCC to GND with three 0.01µF and one 0.1µF ceramic
capacitors. Place the 0.01µF capacitors as close to each V
CC
input). Connect all VCC inputs together, and bypass to GND with a 0.1µF ceramic capacitor.
to disable the single-ended clock output. A
CC
or leave floating to enable the
CC
input as possible (one per V
CC
CC
MAX9324
Detailed Description
The MAX9324 low-skew, low-jitter, clock and data driver distributes a differential LVPECL input signal to four
differential LVPECL outputs and a single-ended LVCMOS output. The differential output drivers operate at
frequencies up to 800MHz. When SEOUT_Z = GND,
the single-ended LVCMOS output driver operates with
frequencies as high as 200MHz. The MAX9324 operates from 3.0V to 3.6V, making the device ideal for 3.3V
systems.
Data Inputs
Differential LVPECL Inputs
The MAX9324 accepts a differential LVPECL input.
Each differential output duplicates the differential input
signal. Terminate CLK and CLK through 50Ω to (V
CC
2V) to minimize input signal reflections. Internal 51kΩ
pulldown resistors to GND ensure the outputs default to
differential low (Q_, Q_) or logic low (SEOUT) when the
CLK inputs are left open.
CLK_EN Input
CLK_EN enables/disables the differential outputs of the
MAX9324. Connect CLK_EN to V
CC
to enable the dif-
ferential outputs. The (Q_, Q_) outputs are driven to a
differential low condition when CLK_EN = GND. Each
differential output pair disables following successive
rising and falling edges on CLK (falling and rising
edges on CLK), after CLK_EN connects to GND. Both a
rising and falling edge on CLK are required to complete the enable/disable function (Figure 2).
One-to-Five LVPECL/LVCMOS Output Clock and
Data Driver
6 _______________________________________________________________________________________
Figure 1. MAX9324 Clock Input-to-Output Delay and Rise/Fall Time
CLK
V
IHD
V
ILD
CLK
Q_
V
OH
V
OL
Q_
t
PLH
Q_ - Q_
20%
SEOUT
20%
V
- V
OH
OL
t
PHL
80% 80%
t
R
80% 80%
t
R
t
F
t
F
20%
20%
SEOUT_Z
SEOUT_Z enables/disables the single-ended LVCMOS
output (Table 1). Connect SEOUT_Z to GND to enable
the single-ended output. Connect SEOUT_Z to VCCto
force the single-ended output to a high-impedance
state. SEOUT provides a single-ended monitor for operating frequencies as high as 200MHz.
Applications Information
Output Termination
Terminate both outputs of each differential pair through
50Ω to (VCC- 2V) or use an equivalent Thevenin termination. Use identical termination on each output for the
lowest output-to-output skew. Terminate both outputs
when deriving a single-ended signal from a differential
output. For example, using Q0 as a single-ended output requires termination for both Q0 and Q0.
MAX9324
One-to-Five LVPECL/LVCMOS Output Clock and
Data Driver
_______________________________________________________________________________________ 7
Figure 2. MAX9324 CLK_EN Timing Diagram
Table 1. Control Input Table
CLK
CLK
CLK_EN
SEOUT
SEOUT_Z
DISABLED
Q_
Q_
ENABLED
HIGH
IMPEDANCE
INPUTS OUTPUTS
QQ0000
CLK_EN SEOUT_Z Q0–Q3 QQ
0 0 Disabled, pulled to logic low Disabled, pulled to logic high Enabled, logic low
0 1 Disabled, pulled to logic low Disabled, pulled to logic high Disabled, high impedance
1 0 Enabled Enabled Enabled
1 1 Enabled Enabled Disabled, high impedance
–QQQQ33
33
SEOUT
MAX9324
SEOUT provides a single-ended LVCMOS monitor output. SEOUT operates with a maximum output frequency
of 200MHz.
Ensure that the output currents do not violate the current limits as specified in the Absolute Maximum
Ratings table. Observe the device’s total thermal limits
under all operating conditions.
Power-Supply Bypassing
Bypass VCCto GND using three 0.01µF ceramic capacitors and one 0.1µF ceramic capacitor. Place the 0.01µF
capacitors (one per VCCinput) as close to VCCas possible (see the Typical Operating Circuit). Use multiple
bypass vias to minimize parasitic inductance.
Circuit Board Traces
Input and output trace characteristics affect the performance of the MAX9324. Connect each input and output
to a 50Ω characteristic impedance trace to minimize
reflections. Avoid discontinuities in differential impedance and maximize common-mode noise immunity by
maintaining the distance between differential traces
and avoiding sharp corners. Minimize the number of
vias to prevent impedance discontinuities. Minimize
skew by matching the electrical length of the traces.
Chip Information
TRANSISTOR COUNT: 4430
PROCESS: BiCMOS
One-to-Five LVPECL/LVCMOS Output Clock and
Data Driver
8 _______________________________________________________________________________________
Functional Diagram
SEOUT_Z
MAX9324
V
V
CC
V
CC
CC
SEOUT
V
CC
CLK_EN
CLK
CLK
D
Q
CLK
GNDGND
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
MAX9324
One-to-Five LVPECL/LVCMOS Output Clock and
Data Driver
_______________________________________________________________________________________ 9
Typical Operating Circuit
ZO = 50Ω
ZO = 50Ω
3.0V TO
3.6V
0.1µF
50Ω 50Ω
VCC - 2V
ON
OFF
OFF
ON
0.01µF 0.01µF 0.01µF
V
CC
V
CC
MAX9324
CLK
CLK
CLK_EN
SEOUT_Z
V
CC
SEOUT
ZO = 50Ω
Q0
Q0
ZO = 50Ω
ZO = 50Ω
Q1
Q1
ZO = 50Ω
ZO = 50Ω
Q2
Q2
ZO = 50Ω
ZO = 50Ω
Q3
Q3
ZO = 50Ω
50Ω 50Ω
VCC - 2V
LVPECL
RECEIVER
LVCMOS/
LVTTL
INPUT
GND
MAX9324
One-to-Five LVPECL/LVCMOS Output Clock and
Data Driver
10 ______________________________________________________________________________________
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE
12,16,20,24L QFN THIN, 4x4x0.8 mm
21-0139 A
MAX9324
One-to-Five LVPECL/LVCMOS Output Clock and
Data Driver
______________________________________________________________________________________ 11
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE
12,16,20,24L QFN THIN, 4x4x0.8 mm
A21-0139
MAX9324
One-to-Five LVPECL/LVCMOS Output Clock and
Data Driver
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
TSSOP4.40mm.EPS
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