MAXIM MAX9323 User Manual
General Description
The MAX9323 low-skew, low-jitter, clock and data driver distributes one of two single-ended LVCMOS inputs
to four differential LVPECL outputs. A single logic control signal (CLK_SEL) selects the input signal to distribute to all outputs. The device operates from 3.0V to
3.6V, making the device ideal for 3.3V systems, and
consumes only 25mA (max) of supply current.
The MAX9323 features low 150ps part-to-part skew, low
11ps output-to-output skew, and low 1.7ps RMS jitter,
making the device ideal for clock and data distribution
across a backplane or board. All outputs are enabled
and disabled synchronously with the clock input to prevent partial output clock pulses.
The MAX9323 is available in space-saving 20-pin
TSSOP and ultra-small 20-pin 4mm ✕ 4mm thin QFN
packages and operates over the extended (-40°C to
+85°C) temperature range. The MAX9323 is pin compatible with Integrated Circuit Systems’ ICS8535-01.
Applications
Precision Clock Distribution
Low-Jitter Data Repeater
Data and Clock Driver and Buffer
Central-Office Backplane Clock Distribution
DSLAM Backplane
Base Station
Hubs
Features
♦ 1.7ps
RMS
Added Random Jitter
♦ 150ps (max) Part-to-Part Skew
♦ 11ps Output-to-Output Skew
♦ 450ps Propagation Delay
♦ Pin Compatible with ICS8535-01
♦ Consumes Only 25mA (max) Supply Current
(50% Less than ICS8535-01)
♦ Synchronous Output Enable/Disable
♦ Two Selectable LVCMOS Inputs
♦ 3.0V to 3.6V Supply Voltage Range
♦ -40°C to +85°C Operating Temperature Range
MAX9323
One-to-Four LVCMOS-to-LVPECL
Output Clock and Data Driver
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
19-2575; Rev 0; 10/02
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Functional Diagram and Typical Operating Circuit appear at
end of data sheet.
Pin Configurations
*Future product—Contact factory for availability.
**EP = Exposed paddle.
MAX9323EUP -40°C to +85°C 20 TSSOP
MAX9323ETP* -40°C to +85°C 20 Thin QFN-EP**
PART TEMP RANGE PIN-PACKAGE
CLK_SEL
CLK_EN
TOP VIEW
1
CLK0
2
N.C.
3
CLK1
4
N.C.
5
N.C.
678910
THIN QFN-EP** (4mm x 4mm)
**CONNECT EXPOSED PADDLE TO GND.
GNDQ0Q0
MAX9323
**EXPOSED PADDLE
CC
Q3
V
N.C.
1617181920
V
15
CC
Q1
14
Q1
13
12
Q2
11
Q2
CC
Q3
V
GND
CLK_EN
CLK_SEL
N.C.
CLK1
N.C.
N.C.
N.C.
V
1
2
3
4
MAX9323
5
6
7
8
9
10
CC
TSSOP
20
Q0
19
Q0
18
V
CC
17
Q1CLK0
Q1
16
15
Q2
14
Q2
13
V
CC
12
Q3
Q3
11
MAX9323
One-to-Four LVCMOS-to-LVPECL
Output Clock and Data Driver
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(VCC= 3.0V to 3.6V, outputs terminated with 50Ω ±1% to (VCC- 2V), CLK_SEL = VCCor GND, CLK_EN = VCC, TA= -40°C to +85°C,
unless otherwise noted. Typical values are at V
CC
= 3.3V, TA= +25°C.) (Notes 1, 2, and 3)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCCto GND...........................................................-0.3V to +4.0V
Q_, Q_, CLK_, CLK_SEL,
CLK_EN to GND.....................................-0.3V to (V
CC
+ 0.3V)
Continuous Output Current .................................................50mA
Surge Output Current........................................................100mA
Continuous Power Dissipation (T
A
= +70°C)
20-Pin TSSOP (derate 11mW/°C)..............................879.1mW
20-Pin 4mm
✕ 4mm Thin QFN (derate 16.9mW/°C)...1349.1mW
Junction-to-Ambient Thermal Resistance in Still Air
20-Pin TSSOP ............................................................+91°C/W
20-Pin 4mm
✕ 4mm Thin QFN.................................+59.3°C/W
Junction-to-Case Thermal Resistance
20-Pin TSSOP ............................................................+20°C/W
20-Pin 4mm
✕ 4mm Thin QFN......................................+2°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Soldering Temperature (10s) ...........................................+300°C
INPUTS (CLK0, CLK1, CLK_SEL, CLK_EN)
Input High Voltage V
Input Low Voltage V
Input High Current I
Input Low Current I
Input Capacitance C
OUTPUTS (Q_, Q_)
Single-Ended Output High
Voltage
Single-Ended Output Low
Voltage
Differential Output Voltage V
SUPPLY
Supply Current (Note 5) I
PARAMETER SYM B O L CONDITIONS MIN TYP MAX UNITS
IH
IL
IH
IL
IN
V
OH
V
OL
OD
CC
Figure 1
Figure 1
CLK0, CLK1, CLK_SEL = V
CLK_EN = V
CLK0, CLK1, CLK_SEL = GND -5 +5
CLK_EN = GND -150
CLK0, CLK1, CLK_SEL, CLK_EN (Note 4) 4 pF
Figure 1
Figure 1
Figure 1, VOD = VOH - V
CLK0, CLK1 2 V
CLK_EN, CLK_SEL 2 V
CLK0, CLK1 0 1.3
CLK_EN, CLK_SEL 0 0.8
CC
OL
CC
-5 +5
V
-
CC
1.4
V
-
CC
2.0
0.6 0.85 V
VCC -
VCC -
CC
CC
150
1.0
1.7
25 mA
V
V
µA
µA
V
V
MAX9323
One-to-Four LVCMOS-to-LVPECL
Output Clock and Data Driver
_______________________________________________________________________________________ 3
Note 1: Measurements are made with the device in thermal equilibrium.
Note 2: Positive current flows into a pin. Negative current flows out of a pin.
Note 3: DC parameters are production tested at T
A
= +25°C and guaranteed by design over the full operating temperature range.
Note 4: Guaranteed by design and characterization. Limits are set at ±6 sigma.
Note 5: All pins open except V
CC
and GND.
Note 6: Measured from the 50% point of the input to the crossing point of the differential output signal.
Note 7: Measured between outputs of the same part at the differential signal crosspoint for a same-edge transition.
Note 8: Measured between outputs of different parts at the differential signal crosspoint under identical conditions for a same-edge
transition.
Note 9: Jitter added to the input signal.
AC ELECTRICAL CHARACTERISTICS
(VCC= 3.0V to 3.6V, outputs terminated with 50Ω ±1% to (VCC-2V), fIN< 266MHz, input duty cycle = 50%, input transition time =
1.1ns (20% to 80%), V
IH
= VCC, VIL= GND, CLK_SEL = VCCor GND, CLK_EN = VCC, TA= -40°C to +85°C, unless otherwise noted.
Typical values are at V
CC
= 3.3V, TA= +25°C.) (Note 4)
(
)
(
)
Switching Frequency f
Propagation Delay t
Output-to-Output Skew t
Part-to-Part Skew t
Output Rise Time t
Output Fall Time t
Output Duty Cycle ODC 48 50 52 %
Added Random Jitter t
Added Jitter (Note 9) t
PARAMETER SYM B O L CONDITIONS MIN TYP MAX UNITS
PHL
MAX
, t
SKOO
SKPP
R
F
RJ
AJ
VOH - VOL ≥ 0.6V 266 800
VOH - VOL ≥ 0.3V 1500
CLK0 or CLK1 to Q_, Q_, Figure 1 (Note 6) 100 450 600 ps
PLH
(Note 7) 30 ps
(Note 8) 150 ps
20% to 80%, Figure 1 100 203 300 ps
80% to 20%, Figure 1 100 198 300 ps
fIN = 266MHz, clock pattern (Note 9) 1.7 3 ps
VCC = 3.3V with 25mV superimposed
sinusoidal noise at 100kHz
10 ps
MHz
RMS
P-P
MAX9323
One-to-Four LVCMOS-to-LVPECL
Output Clock and Data Driver
4 _______________________________________________________________________________________
Typical Operating Characteristics
(VCC= 3.3V, outputs terminated to (VCC- 2V) through 50Ω, CLK_SEL = VCCor GND, CLK_EN = VCC, TA= +25°C.)
SUPPLY CURRENT vs. TEMPERATURE
MAX9323 toc01
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
6035-15 10
10.5
11.0
11.5
12.0
12.5
13.0
13.5
14.0
10.0
-40 85
OUTPUT AMPLITUDE (VOH - VOL)
vs. FREQUENCY
MAX9323 toc02
FREQUENCY (MHz)
OUTPUT AMPLITUDE (mV)
14001200200 400 600 800 1000
100
200
300
400
500
600
700
800
0
0 1600
OUTPUT RISE/FALL TIME
vs. TEMPERATURE
MAX9323 toc03
TEMPERATURE (°C)
OUTPUT RISE/FALL TIME (ps)
603510-15
150
160
170
180
190
200
210
220
230
140
-40 85
t
F
t
R
PROPAGATION DELAY
vs. TEMPERATURE
MAX9323 toc04
TEMPERATURE (°C)
PROPAGATION DELAY (ps)
603510-15
410
420
430
440
450
460
470
480
490
500
400
-40 85
t
PHL
t
PLH
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