MAXIM MAX9322 User Manual

General Description

The MAX9322 low-skew 1:15 differential clock driver reproduces or divides one of two differential input clocks at 15 differential outputs. An input multiplexer selects from one of two input clocks with input switching frequency in excess of 1.0GHz. The 15 outputs are arranged in four banks with 2, 3, 4, and 6 outputs, respectively. Each output bank is individually programmable to provide a divide-by-1 or divide-by-2 frequency function.

The MAX9322 operates in LVPECL systems with a +2.375V to +3.8V supply or in LVECL systems with a

-2.375V to -3.8V supply. A VBBreference output provides compatibility with single-ended clock input signals and a master reset input provides a simultaneous reset on all outputs.

The MAX9322 is available in 52-pin TQFP and 68-pin QFN packages and is specified for operation over

-40°C to +85°C. For 1:10 clock drivers, refer to the MAX9311/MAX9313 data sheet. For 1:5 clock drivers, refer to the MAX9316 data sheet.

Applications

Precision Clock Distribution

Low-Jitter Data Repeaters

Central-Office Backplane Clock Distribution

DSLAM Backplane

Base Stations

ATE

Features

♦ 1.2ps (RMS) Maximum Random Jitter

♦ 300mV Differential Output at 1.0GHz

♦ 900ps Propagation Delay

♦ Selectable Divide-by-1 or Divide-by-2 Frequency

Outputs

♦ Multiplexed 2:1 Input Function

♦ LVECL Operation from V

= -2.375V to -3.8V

♦ LVPECL Operation from V

= +2.375V to +3.8V

♦ ESD Protection: > 2kV Human Body Model

MAX9322

LVECL/LVPECL 1:15 Differential

Divide-by-1/Divide-by-2 Clock Driver

________________________________________________________________ Maxim Integrated Products 1

TQFP

TOP VIEW

VCCO51QA050QA049QA148QA147VCCO46QB045QB044QB143QB142QB241QB2

VCCO

QD515QD5

QD417QD418QD319QD320QD221QD1

QD222QD124QD0

QD0

VCCO

28 N.C.

29 N.C.

30 VCCO

31 QC3

QC3

34 QC2

33 QC2

35 QC1

36 QC1

37 QC0

38 QC0

39 VCCO

FSELD 12

FSELC 11

CLK1 9

CLK1 8

CLK_SEL 7

CLK0 6

CLK0 5

FSELA

FSELB 4

MAX9322

Pin Configurations

Ordering Information

Typical Operating Circuit

19-2544; Rev 2; 2/07

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

PART

TEMP RANGE

PINPACKAGE

MAX9322ECY -40°C to +85°C 52 TQFP

MAX9322ETK* -40°C to +85°C 68 QFN

*Future product—contact factory for availability.

50Ω 50Ω

MAX9322

ZO = 50Ω

= 50Ω

RECEIVER

VTT = VCC - 2.0V

Pin Configurations continued at end of data sheet.

MAX9322

LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

VCCto VEE.............................................................................4.1V

Inputs and Outputs to V

..........................-0.3V to (VCC+ 0.3V)

Differential Input Magnitude............Lower of (V

- VEE) and 3V

Continuous Output Current .................................................50mA

Surge Output Current........................................................100mA

Sink/Source Current ...............................................±0.65mA

Continuous Power Dissipation (T

= +70°C) Single-Layer PC Board

52-Pin TQFP (derate 15.4mW/°C above +70°C).....1230.8mW

68-Lead QFN (derate 27.8mW/°C above +70°C) ...2222.2mW Multilayer PC Board

52-Pin TQFP (derate 19.1mW/°C above +70°C).....1529.6mW

68-Lead QFN (derate 38.5mW/°C above +70°C) ...3076.9mW

Junction-to-Ambient Thermal Resistance in Still Air

Single-Layer PC Board

52-Pin TQFP...............................................................+65°C/W

68-Lead QFN .............................................................+36°C/W

Multilayer PC Board

52-Pin TQFP............................................................+52.3°C/W

68-Lead QFN .............................................................+26°C/W

Junction-to-Ambient Thermal Resistance with 500 LFPM Airflow

Single-Layer PC Board

52-Pin TQFP...............................................................+50°C/W

68-Lead QFN .............................................................+27°C/W

Multilayer PC Board

52-Pin TQFP...............................................................+40°C/W

68-Lead QFN .............................................................+20°C/W

Junction-to-Case Thermal Resistance

52-Pin TQFP............................................................+12.9°C/W

68-Lead QFN ...............................................................+2°C/W

Operating Temperature Range ...........................-40°C to +85°C

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-65°C to +150°C

ESD Protection

Human Body Model (Q_ _,

Q_ _, CLK_SEL,

FSEL_, CLK_, CLK_, MR, V

) ............................................±2kV

Soldering Temperature (10s) ...........................................+300°C

DC ELECTRICAL CHARACTERISTICS

((VCC- VEE) = 2.375V to 3.8V, outputs loaded with 50Ω ±1% to VCC- 2V; CLK_SEL, FSEL_ = high or low; MR = low; |VID| = 0.095V to the lower of (V

- VEE) and 3V. Typical values are at (VCC- VEE) = 3.3V, V

IHD

= VCC- 1V, V

ILD

= VCC- 1.5V.) (Notes 1–4)

-40°C

+25°C

+85°C

PARAMETER

SYMBOL

CONDITIONS

UNITS

SINGLE-ENDED INPUT (MR, FSEL_, CLK_SEL)

Input High Voltage

Figure 1

VCC -

0.88

VCC -

Input Low Voltage V

IL1

Figure 1

VCC -

Input Current I

IN1

MR, FSEL_, CLK_SEL = V

or V

µA

DIFFERENTIAL INPUT (CLK_, CLK_)

Single-Ended Input High Voltage

IH2

Figure 1

VCC -

Single-Ended Input Low Voltage

IL2

Figure 1

VCC -

High Voltage of Differential Input

IHD

Low Voltage of Differential Input

ILD

VCC -

IH1

MIN TYP MAX MIN TYP MAX MIN TYP MAX

1.155

1.81

-15 +150 -15 +150 -15 +150

1.155

1.81

VEE +

1.2

1.505

0.88

1.505

0.095

1.155

1.81

1.155

1.81

VEE +

1.2

0.88

1.155

1.505

0.095

0.88

1.81

1.155

1.81

VEE +

1.2

0.88

1.505

0.88

1.505

0.095

MAX9322

LVECL/LVPECL 1:15 Differential

Divide-by-1/Divide-by-2 Clock Driver

_______________________________________________________________________________________ 3

DC ELECTRICAL CHARACTERISTICS (continued)

((VCC- VEE) = 2.375V to 3.8V, outputs loaded with 50Ω ±1% to VCC- 2V; CLK_SEL, FSEL_ = high or low; MR = low; |VID| = 0.095V to the lower of (V

- VEE) and 3V. Typical values are at (VCC- VEE) = 3.3V, V

IHD

= VCC- 1V, V

ILD

= VCC- 1.5V.) (Notes 1–4)

PARAMETER

CONDITIONS

For VCC - V

< 3.0V

VCC -

Differential Input Voltage

IHD

ILD

For VCC - V

≥ 3.0V

Input Current

IN2

CLK_, CLK_ = V

IHD

or V

ILD

µA

OUTPUTS (Q_, Q_)

Single-Ended Output High Voltage

Figure 1

VCC -

Single-Ended Output Low Voltage

Figure 1

VCC -

Differential Output Voltage

VOH -

Figure 1

REFERENCE

Reference Voltage Output

IBB = ±0.5mA (Note 5)

VCC -

SUPPLY

Supply Current I

(Note 6) 50 85 66

SYMBOL

MIN TYP MAX MIN TYP MAX MIN TYP MAX

0.095

0.095 3.0 0.095 3.0 0.095 3.0

-150 +150 -150 +150 -150 +150

1.085

1.810

500 600 600

1.41

-40°C +25°C +85°C

0.880

1.52

1.25

0.095

1.025

1.810

1.41

0.095

0.880

1.025

1.620

1.810

1.25

1.41

0.880

1.620

1.25

UNITS

115 80 130

MAX9322

LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver

4 _______________________________________________________________________________________

Note 1: Measurements are made with the device in thermal equilibrium. Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. Note 3: Single-ended CLK_, CLK_ input operation is limited to V

- VEE= 3.0V to 3.8V.

Note 4: DC parameters are production tested at T

= +25°C and guaranteed by design over the full operating temperature range.

Note 5: Use V

as a reference for inputs of the same device only.

Note 6: All pins open except V

and VEE.

Note 7: Guaranteed by design and characterization. Limits are set at ±6 sigma. Note 8: Measured between outputs of the same parts at the signal crossing points under identical conditions for a same-edge transition. Note 9: Device jitter added to a jitter-free input signal.

AC ELECTRICAL CHARACTERISTICS

((VCC- VEE) = 2.375V to 3.8V; outputs loaded with 50Ω ±1% to VCC- 2V; input frequency ≤ 1000MHz; input transition time = 125ps (20% to 80%); CLK_SEL, FSEL_ = high or low, MR = low; V

IHD

= VEE+ 1.2V to VCC; V

ILD

= VEEto VCC- 0.4V; V

IHD

- V

ILD

= 0.4V to

1V. Typical values are at (V

- VEE) = 3.3V, V

IHD

= VCC- 1V, V

ILD

= VCC- 1.5V.) (Note 7)

PARAMETER

CONDITION

UNITS

Differential Input-toOutput Delay

PLHD

Figure 2

Single-Ended CLK_/CLK_ to Output Delay

PHLS

Figure 1

MR to Output Delay

Figure 3

Output-to-Output Skew

(Note 8)

Added Random Jitter

fIN = 1.0GHz clock pattern (Note 9)

(RMS)

Added Deterministic Jitter

1Gbps 223 - 1 PRBS pattern (Note 9)

P-P

Switching Frequency

MAX

VOD > 300mV

GHz

Differential Output Rise and Fall Time (20% to 80%)

Figure 2

SYMBOL

-40°C +25°C +85°C

MIN TYP MAX MIN TYP MAX MIN TYP MAX

PHLD

PLHS

SKOO

tR, t

700 900 1150 725 900 1180 750 950 1225

700 900 1170 700 900 1175 725 950 1250

450 930 450 930 450 930

85 56 50

1.2 1.2 1.2

61 61 61

1.0 1.0 1.0

200 260 400 200 260 400 200 240 400

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