General Description
The MAX9321/MAX9321A are low-skew differential
receiver/drivers designed for clock and data distribution. The differential input can be adapted to accept a
single-ended input by connecting the on-chip VBBsupply to an input as a reference voltage.
The MAX9321/MAX9321A feature ultra-low propagation
delay (172ps) and part-to-part skew (20ps) with 24mA
maximum supply current, making these devices ideal
for clock buffering or repeating. For interfacing to differential HSTL and LVPECL signals, these devices operate over a +2.25V to +3.8V supply range, allowing
high-performance clock and data distribution in systems with a nominal +2.5V or +3.3V supply. For differential LVECL operation, these devices operate from a
-2.25V to -3.8V supply. Multiple pinouts are provided to
simplify routing across a backplane to either side of a
double-sided board.
Both devices are offered in space-saving 8-pin SOT23,
SO, and µMAX packages.
Applications
Precision Clock Buffers
Low-Jitter Data Repeaters
Features
♦ Improved Second Source of the MC10LVEP16
(MAX9321)
♦ +2.25V to +3.8V Differential HSTL/LVPECL
Operation
♦ -2.25V to -3.8V Differential LVECL Operation
♦ Low 17mA Supply Current
♦ 20ps Part-to-Part Skew
♦ 172ps Propagation Delay
♦ Minimum 300mV Output at 3GHz
♦ Output Low for Open Input
♦ ESD Protection >2kV (Human Body Model)
♦ On-Chip Reference for Single-Ended Input
♦ Available in Thermally Enhanced Exposed-Pad
SO Package
MAX9321/MAX9321A
Differential LVPECL/LVECL/HSTL
Receiver/Drivers
________________________________________________________________ Maxim Integrated Products 1
Pin Configurations
19-2152; Rev 2; 11/02
Ordering Information
*Future product—contact factory for availability.
**EP = Exposed pad.
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Pin Configurations continued at end of data sheet.
PART
MAX9321EKA-T -40°C to +85°C 8 SOT23-8 AALK
MAX9321EUA* -40°C to +85°C 8 µMAX —
MAX9321ESA -40°C to +85°C 8 SO —
M A X9 3 2 1 A E KA- T -40°C to +85°C 8 SOT23-8 AAIX
MAX9321AEUA* -40°C to +85°C 8 µMAX —
MAX9321AESA -40°C to +85°C 8 SO-EP** —
TEMP
RANGE
PINPACKAGE
TOP
MARK
V
1
CC
V
2
EE
D
3
D
4
60kΩ
100kΩ
V
MAX9321
V
CC
100kΩ
EE
SOT23
Q
8
Q
7
N.C.
6
V
5
BB
N.C.
V
1
D
2
3
D
4
BB
100kΩ
MAX9321
V
CC
60kΩ
100kΩ
µMAX/SO
V
8
CC
Q
7
Q
6
V
5
EE
MAX9321/MAX9321A
Differential LVPECL/LVECL/HSTL
Receiver/Drivers
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(VCC- VEE= +2.25V to +3.8V, outputs loaded with 50Ω ±1% to VCC- 2.0V. Typical values are at VCC- VEE= +3.3V, V
IHD
= VCC- 1V,
V
ILD
= VCC- 1.5V, unless otherwise noted.) (Notes 1–5)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCCto VEE..........................................................................+4.1V
D or D .................................................. V
EE
- 0.3V to VCC+ 0.3V
D to D .................................................................................±3.0V
Continuous Output Current .................................................50mA
Surge Output Current........................................................100mA
V
BB
Sink/Source Current .................................................±0.6mA
Junction-to-Ambient Thermal Resistance in Still Air
8-Pin SOT23.............................................................+112°C/W
8-Pin µMAX ..............................................................+221°C/W
8-Pin SO-EP ...............................................................+53°C/W
Junction-to-Ambient Thermal Resistance with
500 LFPM Airflow
8-Pin SOT23...............................................................+78°C/W
8-Pin µMAX ..............................................................+155°C/W
8-Pin SO.....................................................................+99°C/W
Junction-to-Case Thermal Resistance
8-Pin SOT23...............................................................+80°C/W
8-Pin µMAX ................................................................+39°C/W
8-Pin SO.....................................................................+40°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
ESD Protection
Human Body Model (D, D, Q, Q, V
BB
).............................>2kV
Soldering Temperature (10s) ...........................................+300°C
-40°C +25°C +85°C
PARAMETER
CONDITIONS
UNITS
DIFFERENTIAL INPUT (D, D)
Single-Ended
Input High
Voltage
V
IH
VBB connected to D
(V
IL
for V
BB
connected to D),
Figure 1
V
CC
-
1.210
VCC -
1.145
VCC -
1.085
V
Single-Ended
Input Low
Voltage
V
IL
VBB connected to D
(V
IH
for V
BB
connected to D),
Figure 1
V
EE
VCC -
V
High Voltage of
Differential
Input
VEE +
1.2
VEE +
1.2
VEE +
1.2
V
Low Voltage of
Differential
Input
V
ILD
V
EE
V
EE
V
0.1
0.1
0.1
Differential
Input Voltage
V
IHD
-
V
ILD
0.1 3.0 0.1
0.1
V
Input High
Current
I
IH
µA
D Input Low
Current
I
ILD
-10
-10
-10
µA
D Input Low
Current
I
ILD
µA
SYMBOL
MIN TYP MAX MIN TYP MAX MIN TYP MAX
V
IHD
For VCC - VEE < 3.0V
For VCC - VEE ≥ 3.0V
V
CC
V
EE
VCC -
V
EE
VCC -
1.65
V
CC
0.1
V
EE
VCC -
V
EE
-150 +150 -150 +150 -150 +150
150 150 150
100
V
CC
VCC -
1.545
V
CC
VCC -
0.1
VCC -
V
EE
3.0
100
V
CC
1.485
V
CC
VCC -
0.1
VCC -
V
EE
3.0
100
MAX9321/MAX9321A
Differential LVPECL/LVECL/HSTL
Receiver/Drivers
_______________________________________________________________________________________ 3
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC- VEE= +2.25V to +3.8V, outputs loaded with 50Ω ±1% to VCC- 2.0V. Typical values are at VCC- VEE= +3.3V, V
IHD
= VCC- 1V,
V
ILD
= VCC- 1.5V, unless otherwise noted.) (Notes 1–5)
AC ELECTRICAL CHARACTERISTICS
(VCC- VEE= +2.25V to +3.8V, outputs loaded with 50Ω ±1% to VCC- 2V, input frequency = 1.5GHz, input transition time = 125ps
(20% to 80%), V
IHD
= VEE+ 1.2V to VCC, V
ILD
= VEEto VCC- 0.15V, V
IHD
- V
ILD
= 0.15V to the smaller of 3V or VCC- VEE. Typical
values are at V
CC
- VEE= 3.3V, V
IHD
= VCC- 1V, V
ILD
= VCC- 1.5V, unless otherwise noted.) (Notes 8, 11)
PARAMETER SYMBOL CONDITIONS
DIFFERENTIAL OUTPUT (Q, Q)
Single-Ended
Output High
Voltage
Single-Ended
Output Low
Voltage
Differential
Output Voltage
REFERENCE (VBB)
Reference
Voltage Output
(Note 6)
POWER SUPPLY
Supply Current
(Note 7)
V
V
V
OH
V
V
I
Figure 1
OH
Figure 1
OL
Figure 1 550 550 550 mV
OL
IBB = ±0.5mA
BB
EE
-40°C +25°C +85°C
MIN TYP MAX MIN TYP MAX MIN TYP MAX
V
CC
1.135
V
CC
1.935
V
CC
1.55
-
-
-
VCC -
0.885
VCC -
1.685
VCC -
16 24 17 24 18 24 mA
1.31
VCC -
1.07
VCC -
1.87
VCC -
1.445
VCC -
0.82
VCC -
1.62
VCC -
1.245
VCC -
1.01
VCC -
1.81
VCC -
1.385
V
-
CC
0.76
VCC -
1.56
VCC -
1.185
UNITS
V
V
V
PARAMETER SYMBOL CONDITIONS
Differential
Input-toOutput Delay
Part-to-Part
Skew (Note 9)
Added
Random Jitter
(Note 10)
t
,
PLHD
t
PHLD
t
SKPP
t
RJ
Figure 2 145 184 235 145 172 245 130 167 230 ps
fIN = 1.5GHz, Clock
pattern
fIN = 3.0GHz, Clock
pattern
MIN TYP MAX MIN TYP MAX MIN TYP MAX
-40°C +25°C +85°C
25 90 20 100 20 100 ps
1.7 2.8 1.7 2.8 1.7 2.8
0.6 1.5 0.6 1.5 0.6 1.5
UNITS
ps
(RMS)
MAX9321/MAX9321A
Differential LVPECL/LVECL/HSTL
Receiver/Drivers
4 _______________________________________________________________________________________
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC- VEE= +2.25V to +3.8V, outputs loaded with 50Ω ±1% to VCC- 2V, input frequency = 1.5GHz, input transition time = 125ps
(20% to 80%), V
IHD
= VEE+ 1.2V to VCC, V
ILD
= VEEto VCC- 0.15V, V
IHD
- V
ILD
= 0.15V to the smaller of 3V or VCC- VEE. Typical
values are at V
CC
- VEE= 3.3V, V
IHD
= VCC- 1V, V
ILD
= VCC- 1.5V, unless otherwise noted.) (Notes 8, 11)
Note 1: Guaranteed by design and characterization.
Note 2: Measurements are made with the device in thermal equilibrium.
Note 3: Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 4: DC parameters production tested at T
A
= +25°C. Guaranteed by design and characterization over the full operating temp-
erature range.
Note 5: Single-ended input operation is limited to V
CC
- VEE≥ 3.0V.
Note 6: Use V
BB
as a reference for inputs on the same device only.
Note 7: All pins open except V
CC
and VEE.
Note 8: Guaranteed by design and characterization. Limits are set at ±6 sigma.
Note 9: Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge transition.
Note 10: Device jitter added to the input signal.
PARAMETER SYMBOL CONDITIONS
Added
Deterministic
Jitter (Note 10)
t
DJ
3.0Gbps
23
2
-1 PRBS pattern
MIN TYP MAX MIN TYP MAX MIN TYP MAX
-40°C +25°C +85°C
57 80 57 80 57 80
UNITS
ps
(p-p)
VOH - VOL ≥ 300mV,
Clock pattern,
Switching
Frequency
Output Rise/
Fall Time
(20% to 80%)
f
MAX
t
R
Figure 2
VOH - VOL ≥ 550mV,
Clock pattern,
Figure 2
, t
Figure 2 50 88 120 50 89 120 50 90 120 ps
F
3.0 3.0 3.0
2.0 2.0 2.0
GHz
MAX9321/MAX9321A
Differential LVPECL/LVECL/HSTL
Receiver/Drivers
_______________________________________________________________________________________ 5
Typical Operating Characteristics
(SO packages) (VCC= +3.3V, VEE= 0, input transition time = 125ps (20% to 80%), V
IHD
= VCC- 1V, V
ILD
= VCC- 1.5V, fIN=
1.5GHz, outputs loaded with 50Ω to V
CC
- 2V, TA= +25°C, unless otherwise noted.)
SUPPLY CURRENT, IEE vs. TEMPERATURE
20
19
18
17
16
SUPPLY CURRENT (mA)
15
14
TEMPERATURE (°C)
3510-15-40 60 85
PROPAGATION DELAY vs. HIGH VOLTAGE
OF DIFFERENTIAL INPUT, V
200
195
190
185
180
175
170
165
PROPAGATION DELAY (ps)
160
155
150
1.41.0 3.43.02.62.21.8 3.8
OUTPUT AMPLITUDE, VOH - V
vs. FREQUENCY
1.0
0.9
MAX9321 toc01
0.8
0.7
0.6
0.5
0.4
0.3
OUTPUT AMPLITUDE (V)
0.2
0.1
0
500 25002000150010000 3000 3500
FREQUENCY (MHz)
IHD
V
- V
= 0.5V
IHD
ILD
MAX9321 toc04
t
PLHD
t
PHLD
PROPAGATION DELAY (ps)
V
(V)
IHD
OL
MAX9321 toc02
PROPAGATION DELAY vs. TEMPERATURE
200
190
180
170
160
150
140
130
120
TEMPERATURE (°C)
TRANSITION TIME vs. TEMPERATURE
90
89
88
TRANSITION TIME (ps)
87
10-15-40 6035 85
t
PLHD
t
PHLD
t
F
TEMPERATURE (°C)
t
R
10-15-40 6035 85
MAX9321 toc05
MAX9321 toc03
MAX9321/MAX9321A
Differential LVPECL/LVECL/HSTL
Receiver/Drivers
6 _______________________________________________________________________________________
Pin Description (MAX9321)
Pin Description (MAX9321A)
PIN
µMAX/SO SOT23
1 6 N.C. No Connection
2 3 D Noninverting Differential Input. 100kΩ pulldown to VEE.
34D Inverting Differential Input. 60kΩ pullup to VCC and 100kΩ pulldown to VEE.
45V
52VEENegative Supply Voltage
67Q Inverting Output. Typically terminate with 50Ω resistor to VCC - 2V.
7 8 Q Noninverting Output. Typically terminate with 50Ω resistor to VCC - 2V.
81V
NAME FUNCTION
Reference Output Voltage. Connect to the inverting or noninverting input to provide a
BB
CC
reference for single-ended operation. When used, bypass with a 0.01µF ceramic
capacitor to V
Positive Supply Voltage. Bypass from VCC to VEE with 0.1µF and 0.01µF ceramic
capacitors. Place the capacitors as close to the device as possible with the smaller
value capacitor closest to the device.
PIN
µMAX/SO SOT23
1 6 N.C. No Connection
23D Inverting Differential Input. 60kΩ pullup to VCC and 100kΩ pulldown to VEE.
3 4 D Noninverting Differential Input. 100kΩ pulldown to VEE.
45V
52VEENegative Supply Voltage
6 8 Q Noninverting Output. Typically terminate with 50Ω resistor to VCC - 2V.
77Q Inverting Output. Typically terminate with 50Ω resistor to VCC - 2V.
81V
NAME FUNCTION
Reference Output Voltage. Connect to the inverting or noninverting input to provide a
BB
CC
reference for single-ended operation. When used, bypass with a 0.01µF ceramic
capacitor to V
Positive Supply Voltage. Bypass from VCC to VEE with 0.1µF and 0.01µF ceramic
capacitors. Place the capacitors as close to the device as possible with the smaller
value capacitor closest to the device.
; otherwise leave open.
CC
; otherwise leave open.
CC
Detailed Description
The MAX9321/MAX9321A are low-skew differential
receiver/drivers designed for clock and data distribution. For interfacing to differential HSTL and LVPECL
signals, these devices operate over a +2.25V to +3.8V
supply range, allowing high-performance clock and
data distribution in systems with a nominal +2.5V or
+3.3V supply. For differential LVECL operation, these
devices operate from a -2.25V to -3.8V supply.
Inputs
The differential input can be configured to accept a single-ended input when operating at approximately VCCVEE= 3.0V to 3.8V. This is accomplished by connecting the on-chip reference voltage, VBB, to an input as a
reference. For example, the differential D, D input is
converted to a noninverting, single-ended input by connecting VBBto D and connecting the single-ended
input to D. An inverting input is obtained by connecting
V
BB
to D and connecting the single-ended input to D.
With the differential input configured as single ended
(using VBB), the single-ended input can be driven to
VCCand VEEor with a single-ended LVPECL/LVECL
signal.
When the differential input is configured as a singleended input (using VBB), the approximate supply range
is VCC- VEE= 3.0V to 3.8V. This is because one of the
inputs must be VEE+ 1.2V or higher for proper operation of the input stage. VBBmust be at least VEE+ 1.2V
because it becomes the high-level input when the other
(single-ended) input swings below it. Therefore, minimum VBB= VEE+ 1.2V.
The minimum VBBoutput is VCC- 1.510V. Substituting
the minimum VBBinto VBB= VEE+ 1.2V results in a
minimum supply of 2.71V. Rounding up to a standard
supply gives the single-ended operating supply range
of VCC- VEE= 3.0V to 3.8V.
MAX9321/MAX9321A
Differential LVPECL/LVECL/HSTL
Receiver/Drivers
_______________________________________________________________________________________ 7
Figure 1. Switching with Single-Ended Input
Figure 2. Differential Transition Time and Propagation Delay Timing Diagram
D
D
Q
Q
D
D
Q
Q
(Q) - (Q)
t
PLHD
20%
V
IL
V
IHD
80%
0 (DIFFERENTIAL)
t
R
- V
ILD
V
- V
OH
VOH - V
OL
t
PHLD
OL
80%
V
IH
(CONNECTED TO D)
0 (DIFFERENTIAL)
20%
t
F
V
BB
V
OH
V
OL
V
IHD
V
ILD
V
OH
V
OL
MAX9321/MAX9321A
Differential LVPECL/LVECL/HSTL
Receiver/Drivers
8 _______________________________________________________________________________________
When using the VBBreference output, bypass it with a
0.01µF ceramic capacitor to VCC. If the VBBreference
is not used, it can be left open. The VBBreference can
source or sink 0.5mA. Use VBBonly for an input on the
same device as the VBBreference.
The maximum magnitude of the differential input from D
to D is 3.0V or VCC- VEE, whichever is less. This limit
also applies to the difference between any reference
voltage input and a single-ended input.
The differential input has bias resistors that drive the
output to a differential low when the inputs are open.
The inverting input is biased with a 60kΩ pullup to V
CC
and a 100kΩ pulldown to VEE. The noninverting input is
biased with a 100kΩ pulldown to VEE.
Specifications for the high and low voltage of the differential input (V
IHD
and V
ILD
) and the differential input
voltage (V
IHD
- V
ILD
) apply simultaneously (V
ILD
cannot
be higher than V
IHD
).
Outputs
Output levels are referenced to VCCand are considered LVPECL or LVECL, depending on the level of the
VCCsupply. With VCCconnected to a positive supply
and VEEconnected to GND, the output is LVPECL. The
output is LVECL when VCCis connected to GND and
VEEis connected to a negative supply.
A single-ended input of at least VBB±100mV or a differential input of at least ±100mV switches the outputs to
the VOHand VOLlevels specified in the DC Electrical
Characteristics table.
Applications Information
Supply Bypassing
Bypass VCCto VEEwith high-frequency surface-mount
ceramic 0.1µF and 0.01µF capacitors in parallel as
close to the device as possible, with the 0.01µF value
capacitor closest to the device. Use multiple parallel
vias for low inductance. When using the V
BB
reference
output, bypass it with a 0.01µF ceramic capacitor to
VCC(if the VBBreference is not used, it can be left
open).
Traces
Input and output trace characteristics affect the performance of the MAX9321/MAX9321A. Connect each signal of a differential input or output to a 50Ω
characteristic impedance trace. Minimize the number of
vias to prevent impedance discontinuities. Reduce
reflections by maintaining the 50Ω characteristic
impedance through connectors and across cables.
Reduce skew within a differential pair by matching the
electrical length of the traces.
The exposed-pad (EP) SO package can be soldered to
the PC board for enhanced thermal performance. If the
EP is not soldered to the PC board, the thermal resistance is the same as the regular SO package. The EP is
connected to the chip VEEsupply. Be sure that the pad
does not touch signal lines or other supplies.
Contact Maxim's Packaging department for guidelines
on the use of EP packages.
Output Termination
Terminate outputs through 50Ω to VCC- 2V or use an
equivalent Thevenin termination. When a single-ended
signal is taken from the differential output, terminate
both outputs. For example, when Q is used as a singleended output, terminate both Q and Q.
Chip Information
TRANSISTOR COUNT: 162
Pin Configurations (continued)
V
1
V
CC
2
EE
D
3
D
4
V
CC
60kΩ
100kΩ
V
MAX9321A
100kΩ
EE
SOT23
8
Q
7V
Q
6
N.C.
5
V
BB
N.C.
CC
1
2
D
3
D
4
V
BB
MAX9321A
60kΩ
100kΩ
100kΩ
µMAX/SO
8
V
CC
7
Q
6
Q
5
V
EE
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ______________________9
© 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Differential LVPECL/LVECL/HSTL
Receiver/Drivers
MAX9321/MAX9321A
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
SOT23, 8L.EPS
8L, SOIC EXP. PAD.EPS
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