MAXIM MAX9320, MAX9320A User Manual

For pricing delivery, and ordering information please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

General Description

The MAX9320/MAX9320A are low-skew, 1-to-2 differen­tial drivers designed for clock and data distribution. The
input is reproduced at two differential outputs. The dif­ferential input can be adapted to accept single-ended
inputs by applying an external reference voltage.

The MAX9320/MAX9320A feature ultra-low propagation
delay (208ps), part-to-part skew (20ps), and output-to­output skew (6ps) with 30mA maximum supply current,
making these devices ideal for clock distribution. For
interfacing to differential HSTL and LVPECL signals,
these devices operate over a +2.25V to +3.8V supply
range, allowing high-performance clock or data distrib­ution in systems with a nominal +2.5V or +3.3V supply.
For differential LVECL operation, these devices operate
from a -2.25V to -3.8V supply.

The pinout is the only difference between the MAX9320
and MAX9320A. Multiple pinouts are provided to simplify
routing across a backplane to either side of a double­sided board.

These devices are offered in space-saving 8-pin SOT23,
µMAX, and SO packages.

Applications

Precision Clock Distribution

Low-Jitter Data Repeater

Protection Switching

Features

♦ Improved Second Source of the MC10LVEP11

(MAX9320)

♦ +2.25V to +3.8V Differential HSTL/LVPECL

Operation

♦ -2.25V to -3.8V LVECL Operation

♦ Low 22mA (typ) Supply Current

♦ 20ps (typ) Part-to-Part Skew

♦ 6ps (typ) Output-to-Output Skew

♦ 208ps (typ) Propagation Delay

♦ Minimum 300mV Output at 3GHz

♦ Outputs Low for Open Input

♦ ESD Protection >2kV (Human Body Model)

♦ Available in Thermally Enhanced Exposed-Pad

SO Package

MAX9320/MAX9320A

1:2 Differential LVPECL/LVECL/HSTL

Clock and Data Drivers

________________________________________________________________ Maxim Integrated Products 1

Pin Configurations

19-2201; Rev 3; 11/04

Ordering Information

*Contact factory for availability.

PART

MAX9320EKA-T -40°C to +85°C 8 SOT23-8 AALJ

MAX9320ESA -40°C to +85°C 8 SO —

MAX9320XESA -40°C to +85°C 8 SO-EP* —

MAX9320EUA -40°C to +85°C 8 µMAX —

MAX9320AEKA-T -40°C to +85°C 8 SOT23-8 AAIW

TEMP

RANGE

PIN­PACKAGE

TOP
MARK

Q0

1

Q0

2

Q1

3

Q1

4

MAX9320

100kΩ

100kΩ

µMAX/SO

8

60kΩ

7

6

5

V

V

CC

D

D

V

EE

1

CC

V

2

EE

D

3

D

4

V

CC

60kΩ

100kΩ

MAX9320A

100kΩ

V

EE

SOT23

8

7

6

5

V

Q0

Q0

Q1

Q1

1

CC

V

2

EE

D

3

D

4

60kΩ

100kΩ

MAX9320

V

CC

V

EE

100kΩ

SOT23

Q0

8

Q0

7

Q1

6

Q1

5

MAX9320/MAX9320A

1:2 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

DC ELECTRICAL CHARACTERISTICS

(VCC- VEE= +2.25V to +3.8V, outputs loaded with 50Ω ±1% to VCC- 2V. Typical values are at VCC- VEE= +3.3V, V

IHD

= VCC-

1.0V, V

ILD

= VCC- 1.5V, unless otherwise noted.) (Notes 1, 2, 3)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

VCCto VEE..........................................................................+4.1V

D or D .................................................. V

EE

- 0.3V to VCC+ 0.3V

D to D .................................................................................±3.0V

Continuous Output Current .................................................50mA

Surge Output Current........................................................100mA

Junction-to-Ambient Thermal Resistance in Still Air

8-Pin SOT23.............................................................+112°C/W

8-Pin µMAX ..............................................................+221°C/W

8-Pin SO...................................................................+170°C/W

Junction-to-Ambient Thermal Resistance with 500
LFPM Airflow

8-Pin SOT23...............................................................+78°C/W

8-Pin µMAX ..............................................................+155°C/W

8-Pin SO.....................................................................+99°C/W

Junction-to-Case Thermal Resistance

8-Pin SOT23...............................................................+80°C/W

8-Pin µMAX ................................................................+39°C/W

8-Pin SO.....................................................................+40°C/W

Operating Temperature Range ...........................-40°C to +85°C

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-65°C to +150°C

ESD Protection

Human Body Model (D, D, Q_, Q_) .................................>2kV

Soldering Temperature (10s) ...........................................+300°C

PARAMETER SYM BOL CONDITIONS

DIFFERENTIAL INPUT (D, D)

High Voltage of
Differential
Input

Low Voltage of
Differential
Input

Differential
Input Voltage

Input High
Current

D Input Low
Current

D Input Low
Current

DIFFERENTIAL OUTPUTS (Q_, Q_)

Single-Ended
Output High
Voltage

MIN TYP MAX MIN TYP MAX MIN TYP MAX

V

+ 1.2

V

0.1

0.1 3.0 0.1 3.0 0.1 3.0

-10 100 -10 100 -10 100 µA

-150 +150 -150 +150 -150 +150 µA

V

- 1.135

- V

V

IHD

V

ILD

For VCC - V

ILD

< +3.0V

For VCC - V

V

IHD

EE

EE

≥ +3.0V

I

IH

I

ILD

I

ILD

V

OH

Figure 1

-40°C +25°C +85°C

EE

EE

CC

V

CC

V

CC

- 0.1

V

CC

- V

EE

V

EE

+ 1.2

V

EE

0.1

V

V

- 0.1

V

- V

CC

CC

CC

EE

V

EE

+ 1.2

V

EE

0.1

V

CC

V

CC

- 0.1

V

CC

- V

EE

150 150 150 µA

V

- 0.885

CC

V

CC

- 1.07

V

CC

- 0.82

V

CC

- 1.01

V

CC

- 0.76

UNITS

V

V

V

V

MAX9320/MAX9320A

1:2 Differential LVPECL/LVECL/HSTL

Clock and Data Drivers

_______________________________________________________________________________________ 3

DC ELECTRICAL CHARACTERISTICS (continued)

(VCC- VEE= +2.25V to +3.8V, outputs loaded with 50Ω ±1% to VCC- 2V. Typical values are at VCC- VEE= +3.3V, V

IHD

= VCC-

1.0V, V

ILD

= VCC- 1.5V, unless otherwise noted.) (Notes 1, 2, 3)

AC ELECTRICAL CHARACTERISTICS

(VCC- VEE= +2.25V to +3.8V, outputs loaded with 50Ω ±1% to VCC- 2V, input frequency = 1.5GHz, input transition time = 125ps
(20% to 80%), V

IHD

= VEE+ 1.2V to VCC, V

ILD

= VEEto VCC- 0.15V, V

IHD

- V

ILD

= 0.15V to the smaller of 3V or VCC- VEE. Typical

values are at V

CC

- VEE= +3.3V, V

IHD

= VCC- 1V, V

ILD

= VCC- 1.5V, unless otherwise noted.) (Note 5)

PARAMETER SYMBOL CONDITIONS

Single-Ended
Output Low
Voltage

Differential
Output Voltage

POWER SUPPLY

Supply Current I

MIN TYP MAX MIN TYP MAX MIN TYP MAX

V

- 1.935

- V

V

OL

V

OH

EE

Figure 1

Figure 1 550 550 550 mV

OL

(Note 4) 20 28 22 28 23 30 mA

-40°C +25°C +85°C

CC

V

- 1.685

CC

V

CC

- 1.87

V

CC

- 1.62

- 1.81

V

CC

V

CC

- 1.56

UNITS

V

PARAMETER SYMBOL CONDITIONS

Differential
Input-to­Output Delay

,

t

PLHD

t

PHLD

Figure 1 145 203 265 155 208 265 160 220 270 ps

-40°C +25°C +85°C

MIN TYP MAX MIN TYP MAX MIN TYP MAX

UNITS

Output-to­Output Skew

Part-to-Part
Skew

Added
Random Jitter
(Note 8)

Added
Deterministic
Jitter

t

SKOO

t

SKPP

t

t

(Note 6) 6 30 6 30 6 30 ps

(Note 7) 20 120 20 110 20 110 ps

fIN = 1.5GHz, clock
pattern

RJ

fIN = 3.0GHz, clock
pattern

3.0Gbps

23

2

DJ

(Note 8)

-1 PRBS pattern

1.7 2.8 1.7 2.8 1.7 2.8

0.6 1.5 0.6 1.5 0.6 1.5

57 80 57 80 57 80

ps

(RMS)

ps

(p-p)

Note 1: Measurements are made with the device in thermal equilibrium.
Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 3: DC parameters production tested at T

A

= +25°C. Guaranteed by design and characterization over the full operating temper-

ature range.

Note 4: All pins open except V

CC

and VEE.

Note 5: Guaranteed by design and characterization. Limits are set at ±6 sigma.
Note 6: Measured between outputs of the same part at the signal crossing points for a same-edge transition.
Note 7: Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge

transition.

Note 8: Device jitter added to the input signal.

MAX9320/MAX9320A

1:2 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers

4 _______________________________________________________________________________________

AC ELECTRICAL CHARACTERISTICS (continued)

(VCC- VEE= +2.25V to +3.8V, outputs loaded with 50Ω ±1% to VCC- 2V, input frequency = 1.5GHz, input transition time = 125ps
(20% to 80%), V

IHD

= VEE+ 1.2V to VCC, V

ILD

= VEEto VCC- 0.15V, V

IHD

- V

ILD

= 0.15V to the smaller of 3V or VCC- VEE. Typical

values are at V

CC

- VEE= +3.3V, V

IHD

= VCC- 1V, V

ILD

= VCC- 1.5V, unless otherwise noted.) (Note 5)

PARAMETER SYMBOL CONDITIONS

Switching
Frequency

Output
Rise/Fall Time
(20% to 80%)

VOH - VOL ≥ 300mV,
clock pattern,

f

MAX

t

R

Figure 1

VOH - VOL ≥ 550mV,
clock pattern,
Figure 1

, t

Figure 1 50 88 120 50 89 120 50 90 120 ps

F

-40°C +25°C +85°C

MIN TYP MAX MIN TYP MAX MIN TYP MAX

3.0 3.0 3.0

2.0 2.0 2.0

UNITS

GHz

MAX9320/MAX9320A

1:2 Differential LVPECL/LVECL/HSTL

Clock and Data Drivers

_______________________________________________________________________________________ 5

Typical Operating Characteristics

(VCC= +3.3V, VEE= 0, input transition time = 125ps (20% to 80%), V

IHD

= VCC- 1V, V

ILD

= VCC- 1.5V, fIN= 1.5GHz, outputs loaded

with 50Ω to V

CC

- 2V, TA= +25°C, unless otherwise noted.)

SUPPLY CURRENT, IEE vs. TEMPERATURE

25

24

23

22

21

20

19

18

SUPPLY CURRENT (mA)

17

16

15

0.9

0.8

MAX9320 toc01

0.7

0.6

0.5

0.4

0.3

OUTPUT AMPLITUDE (V)

0.2

0.1

3510-15-40 60 85

TEMPERATURE (°C)

OUTPUT AMPLITUDE, VOH - V

vs. FREQUENCY

0

500 25002000150010000 3000 3500

FREQUENCY (MHz)

PROPAGATION DELAY vs.

HIGH VOLTAGE OF DIFFERENTIAL INPUT, V

225

220

215

210

205

PROPAGATION DELAY (ps)

200

195

V

- V

= 0.5V

IHD

ILD

t

PLHD

t

PHLD

1.41.0 3.43.02.62.21.8 3.8
V

(V)

IHD

IHD

MAX9320 toc04

PROPAGATION DELAY vs. TEMPERATURE

240

230

220

210

200

190

PROPAGATION DELAY (ps)

180

170

160

OL

TRANSITION TIME vs. TEMPERATURE

91

90

MAX9320 toc02

89

88

87

TRANSITION TIME (ps)

86

85

10-15-40 6035 85

TEMPERATURE (°C)

t

PLHD

t

F

10-15-40 6035 85

TEMPERATURE (°C)

MAX9320 toc05

t

PHLD

t

R

MAX9320 toc03

MAX9320/MAX9320A

1:2 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers

6 _______________________________________________________________________________________

Pin Description (MAX9320)

Pin Description (MAX9320A)

PIN

µMAX/SO SOT23

18Q0 Noninverting Q0 Output. Typically terminate with 50Ω resistor to VCC - 2V.
27Q0 Inverting Q0 Output. Typically terminate with 50Ω resistor to VCC - 2V.

36Q1 Noninverting Q1 Output. Typically terminate with 50Ω resistor to VCC - 2V.
45Q1 Inverting Q1 Output. Typically terminate with 50Ω resistor to VCC - 2V.

52VEENegative Supply Voltage
64D Inverting Differential Input. 60kΩ pullup to VCC and 100kΩ pulldown to VEE.

73DNoninverting Differential Input. 100kΩ pulldown to VEE.

81V

NAME FUNCTION

Positive Supply Voltage. Bypass from VCC to VEE with 0.1µF and 0.01µF ceramic

CC

capacitors. Place the capacitors as close to the device as possible with the smaller
value capacitor closest to the device.

PIN

SOT23

1V

2V
3 D Inverting Differential Input. 60kΩ pullup to VCC and 100kΩ pulldown to VEE.

4DNoninverting Differential Input. 100kΩ pulldown to VEE.
5 Q1 Inverting Q1 Output. Typically terminate with 50Ω resistor to VCC - 2V.

6Q1Noninverting Q1 Output. Typically terminate with 50Ω resistor to VCC - 2V.
7 Q0 Inverting Q0 Output. Typically terminate with 50Ω resistor to VCC - 2V.

8Q0Noninverting Q0 Output. Typically terminate with 50Ω resistor to VCC - 2V.

NAME FUNCTION

Positive Supply Voltage. Bypass from VCC to VEE with 0.1µF and 0.01µF ceramic

CC

EE

capacitors. Place the capacitors as close to the device as possible with the smaller value
capacitor closest to the device.

Negative Supply Voltage

MAX9320/MAX9320A

1:2 Differential LVPECL/LVECL/HSTL

Clock and Data Drivers

_______________________________________________________________________________________ 7

Detailed Description

The MAX9320/MAX9320A low-skew, 1-to-2 differential
drivers are designed for clock and data distribution. For
interfacing to differential HSTL and LVPECL signals,
these devices operate over a +2.25V to +3.8V supply
range, allowing high-performance clock and data distri­bution in systems with a nominal +2.5V or +3.3V sup­ply. For differential LVECL operation, these devices
operate from a -2.25V to -3.8V supply.

Inputs

The maximum magnitude of the differential input from D
to D is VCC- VEEor 3.0V, whichever is less. This limit
also applies to the difference between any reference
voltage input and a single-ended input.

The differential inputs have bias resistors that drive the
outputs to a differential low when the inputs are open.
The inverting input, D, is biased with a 60kΩ pullup to
VCCand a 100kΩ pulldown to VEE. The noninverting
input, D, is biased with a 100kΩ pulldown to VEE.

Specifications for the high and low voltages of the dif­ferential input (V

IHD

and V

ILD

) and the differential input

voltage (V

IHD

- V

ILD

) apply simultaneously (V

ILD

cannot

be higher than V

IHD

).

Outputs

Output levels are referenced to VCCand are consid­ered LVPECL or LVECL, depending on the level of the
VCCsupply. With VCCconnected to a positive supply
and VEEconnected to GND, the outputs are LVPECL.
The outputs are LVECL when V

CC

is connected to GND

and V

EE

is connected to a negative supply.

A single-ended input of ±100mV around a reference
voltage or a differential input of at least ±100mV switch­es the outputs to the V

OH

and VOLlevels specified in

the DC Electrical Characteristics table.

Applications Information

Supply Bypassing

Bypass VCCto VEEwith high-frequency surface-mount
ceramic 0.1µF and 0.01µF capacitors in parallel as
close to the device as possible, with the 0.01µF value
capacitor closest to the device. Use multiple parallel
vias for low inductance.

Traces

Input and output trace characteristics affect the perfor­mance of the MAX9320/MAX9320A. Connect each
signal of a differential input or output to a 50Ω charac­teristic impedance trace. Minimize the number of vias
to prevent impedance discontinuities. Reduce reflec­tions by maintaining the 50Ω characteristic impedance
through connectors and across cables. Reduce skew
within a differential pair by matching the electrical
length of the traces.

The exposed-pad (EP) SO package can be soldered to
the PC board for enhanced thermal performance. If the
EP is not soldered to the PC board, the thermal resis­tance is the same as the regular SO package. The EP
is connected to the chip VEEsupply. Be sure that the
pad does not touch signal lines or other supplies.

Contact the Maxim Packaging department for guide­lines on the use of EP packages.

Output Termination

Terminate outputs through 50Ω to VCC- 2V or use an
equivalent Thevenin termination. Terminate both out­puts and use the same termination on each for the low­est output-to-output skew. When a single-ended signal
is taken from a differential output, terminate both out­puts. For example, if Q0 is used as a single-ended out­put, terminate both Q0 and Q0.

Chip Information

TRANSISTOR COUNT: 182

Figure 1. Differential Transition Time and Propagation Delay
Timing Diagram

D

D

t

PLHD

Q_

Q

(Q_) - (Q_)

20%

V

IHD -VILD

80%

0 (DIFFERENTIAL)

t

R

V

OH -VOL

t

PHLD

80%

0 (DIFFERENTIAL)

t

F

20%

V

IHD

V

ILD

V

OH

V

OL

SOT23, 8L .EPS

REV.DOCUMENT CONTROL NO.APPROVAL

PROPRIETARY INFORMATION

TITLE:

3.002.60E

C

E1

E

BETWEEN 0.08mm AND 0.15mm FROM LEAD TIP.

8. MEETS JEDEC MO178.

8∞

0.60

1.75

0.30

L2

0∞

e1

e

L

1.50E1

0.65 BSC.

1.95 REF.

0.25 BSC.

GAUGE PLANE

SEATING PLANE C

C

L

PIN 1

I.D. DOT

(SEE NOTE 6)

L

C

L

C

A2

e1

D

DETAIL "A"

5. COPLANARITY 4 MILS. MAX.

NOTE:

7. SOLDER THICKNESS MEASURED AT FLAT SECTION OF LEAD

6. PIN 1 I.D. DOT IS 0.3 MM ÿ MIN. LOCATED ABOVE PIN 1.

4. PACKAGE OUTLINE INCLUSIVE OF SOLDER PLATING.

3. PACKAGE OUTLINE EXCLUSIVE OF MOLD FLASH & METAL BURR.

HEEL OF THE LEAD PARALLEL TO SEATING PLANE C.

2. FOOT LENGTH MEASURED FROM LEAD TIP TO UPPER RADIUS OF

1. ALL DIMENSIONS ARE IN MILLIMETERS.

L2

L

A1

A

0.45

1.30

0.15

1.45

MAX

0.28b

0.90A2

0.00A1

0.90

A

MIN

SYMBOL

3.00

0.20

2.80D

0.09

C

SEE DETAIL "A"

L

C

b

e

D

1

21-0078

1

PACKAGE OUTLINE, SOT-23, 8L BODY

0

0

MAX9320/MAX9320A

1:2 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers

8 _______________________________________________________________________________________

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)

MAX9320/MAX9320A

1:2 Differential LVPECL/LVECL/HSTL

Clock and Data Drivers

_______________________________________________________________________________________ 9

Package Information (continued)

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)

8L, SOIC EXP. PAD.EPS

PACKAGE OUTLINE
8L SOIC, .150" EXPOSED PAD

21-0111

1

B

1

MAX9320/MAX9320A

1:2 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

© 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

Package Information (continued)

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)

SOICN .EPS

PACKAGE OUTLINE, .150" SOIC

1

1

21-0041

B

REV.DOCUMENT CONTROL NO.APPROVAL

PROPRIETARY INFORMATION

TITLE:

TOP VIEW

FRONT VIEW

MAX

0.010

0.069

0.019

0.157

0.010

INCHES

0.150

0.007

E

C

DIM

0.014

0.004

B

A1

MIN

0.053A

0.19

3.80 4.00

0.25

MILLIMETERS

0.10

0.35

1.35

MIN

0.49

0.25

MAX

1.75

0.050

0.016L

0.40 1.27

0.3940.386D

D

MINDIM

D

INCHES

MAX

9.80 10.00

MILLIMETERS

MIN

MAX

16

AC

0.337 0.344 AB8.758.55 14

0.189 0.197 AA5.004.80 8

N MS012

N

SIDE VIEW

H 0.2440.228 5.80 6.20

e 0.050 BSC 1.27 BSC

C

HE

e

B

A1

A

D

0∞-8∞

L

1

VARIATIONS: