MAXIM MAX9315 User Manual

19-2220; Rev 1; 11/04

General Description

The MAX9315 low-skew, 1-to-5 differential driver is
designed for clock and data distribution. This device
allows selection between two inputs. The selected input
is reproduced at five differential outputs. The differential
inputs can be adapted to accept a single-ended input
by connecting the on-chip VBBsupply to one input as a
reference voltage.

The MAX9315 features low output-to-output skew
(20ps), making it ideal for clock and data distribution
across a backplane or a board. For interfacing to differ­ential HSTL and LVPECL signals, this device operates
over a +2.375V to +3.8V supply range, allowing high­performance clock or data distribution in systems with a
nominal +2.5V or +3.3V supply. For differential LVECL
operation, this device operates with a -2.375V to -3.8V
supply.

The MAX9315 is offered in a space-saving 20-pin
TSSOP package.

Applications

Precision Clock Distribution
Low-Jitter Data Repeater
Data and Clock Driver and Buffer
Central Office Backplane Clock Distribution
DSLAM Backplane
Base Station
ATE

Features

♦ +2.375V to +3.8V Supply for Differential

HSTL/LVPECL Operation

♦ -2.375V to -3.8V Supply for Differential LVECL

Operation

♦ Two Selectable Differential Inputs
♦ Synchronous Output Enable/Disable
♦ 20ps Output-to-Output Skew
♦ 360ps Propagation Delay
♦ Guaranteed 400mV Differential Output at 1.5GHz
♦ On-Chip Reference for Single-Ended Inputs
♦ Input Biased Low when Left Open
♦ Pin Compatible with MC100LVEP14

MAX9315

1:5 Differential LVPECL/LVECL/HSTL

Clock and Data Driver

________________________________________________________________ Maxim Integrated Products 1

20

19

18

17

16

15

14

13

1

2

3

4

5

6

7

8

V

CC

EN

V

CC

CLK1Q1

Q1

Q0

QO

TOP VIEW

CLK1

V

BB

CLK0

CLK0Q3

Q3

Q2

Q2

12

11

9

10

SEL

V

EE

Q4

Q4

MAX9315

D

Q

TSSOP

Pin Configuration

Ordering Information

50Ω 50Ω

MAX9315

ZO = 50Ω

Z

O

= 50Ω

RECEIVER

Q_

Q_

VTT = VCC - 2.0V

Typical Application Circuit

EVALUATION KIT

AVAILABLE

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

PART TEMP RANGE PIN-PACKAGE

MAX9315EUP -40°C to +85°C 20 TSSOP

Functional Diagram appears at end of data sheet.

MAX9315

1:5 Differential LVPECL/LVECL/HSTL
Clock and Data Driver

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

DC ELECTRICAL CHARACTERISTICS

(VCC- VEE= 2.375V to 3.8V, outputs loaded with 50Ω ±1% to VCC- 2V, SEL = high or low, EN = low, unless otherwise noted. Typical

values are at V

CC

- VEE= +3.3V, V

IHD

= VCC- 1V, V

ILD

= VCC- 1.5V.) (Notes 1, 2, 3)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

VCC- VEE...............................................................................4.1V

Inputs (CLK_, CLK_, SEL, EN)

to V

EE

...........................................(VEE- 0.3V) to (VCC+ 0.3V)

CLK_ to CLK_ ....................................................................±3.0V

Continuous Output Current.................................................50mA

Surge Output Current........................................................100mA

V

BB

Sink/Source Current...............................................±0.65mA

Continuous Power Dissipation (T

A

= +70°C)
Single-Layer PC Board

20-Pin TSSOP (derate 7.69mW/°C above +70°C) .......615mW

Multilayer PC Board

20-Pin TSSOP (derate 10.9mW/°C above +70°C) .......879mW

Junction-to-Ambient Thermal Resistance in Still Air

Single-Layer PC Board

20-Pin TSSOP .........................................................+130°C/W

Multilayer PC Board

20-Pin TSSOP ...........................................................+91°C/W

Junction-to-Ambient Thermal Resistance with 500LFPM

Airflow Single-Layer PC Board

20-Pin TSSOP ..........................................................+9.6°C/W

Junction-to-Case Thermal Resistance

20-Pin TSSOP ............................................................+20°C/W

Operating Temperature Range ...........................-40°C to +85°C

Junction Temperature......................................................+150°C

Storage Temperature Range.............................-65°C to +150°C

ESD Protection

Human Body Model (Inputs and Outputs).......................≥2kV

Soldering Temperature (10s)...........................................+300°C

PARAMETER

CONDITIONS

UNITS

SINGLE-ENDED INPUTS (SEL, EN)

Input High Voltage

V

IH

VCC -

VCC -

VCC -

V

Input Low Voltage V

IL

VCC -

VCC -

VCC -

V

Input Current I

IN

V

IH(MAX)

, V

IL(MIN)

µA

DIFFERENTIAL INPUTS (CLK_, CLK_)

Single-Ended Input
High Voltage
(Note 4)

V

IH

VBB connected to
CLK_, Figure 1

VCC -

VCC -

VCC -

V

Single-Ended Input
Low Voltage
(Note 4)

V

IL

VBB connected to
CLK_, Figure 1

VCC -

VCC -

VCC -

V

High Voltage of
Differential Input

V

IHD

VEE +

VEE +

VEE +

V

Low Voltage of
Differential Input

V

ILD

VCC -

VCC -

VCC -

V

SYMBOL

MIN TYP MAX MIN TYP MAX MIN TYP MAX

1.225

V

EE

-500 500 -500 500 -500 500

1.225

V

EE

1.2

V

EE

-40°C +25°C +85°C

V

CC

1.625

V

CC

1.625

V

CC

0.1

1.225

V

EE

1.225

V

EE

1.2

V

EE

V

CC

1.625

V

CC

1.625

V

CC

0.1

1.225

V

EE

1.225

V

EE

1.2

V

EE

V

CC

1.625

V

CC

1.625

V

CC

0.1

MAX9315

1:5 Differential LVPECL/LVECL/HSTL

Clock and Data Driver

_______________________________________________________________________________________ 3

DC ELECTRICAL CHARACTERISTICS (continued)

(VCC- VEE= 2.375V to 3.8V, outputs loaded with 50Ω ±1% to VCC- 2V, SEL = high or low, EN = low, unless otherwise noted. Typical
values are at V

CC

- VEE= +3.3V, V

IHD

= VCC- 1V, V

ILD

= VCC- 1.5V.) (Notes 1, 2, 3)

PARAMETER

CONDITIONS

UNITS

For (VCC - VEE) <
+3.0V

VCC -

VCC -

VCC -

Differential Input
Voltage

V

IHD

-

V

ILD

For (VCC - VEE) ≥
+3.0V

V

Input Current I

IN

µA

OUTPUTS (Q_, Q_)

Single-Ended
Output High
Voltage

V

OH

Figure 1

V

CC

-

VCC -

VCC -

VCC -

VCC -

VCC -

V

Single-Ended
Output Low
Voltage

V

OL

Figure 1

V

CC

-

VCC -

VCC -

VCC -

VCC -

VCC -

V

Differential Output
Voltage

VOH -

V

OL

Figure 1

mV

REFERENCE

Reference Voltage
Output (Note 5)

V

BB

IBB = ±0.5mA

V

CC

-

VCC -

VCC -

VCC -

VCC -

VCC -

V

SUPPLY

Supply Current
(Note 6)

I

EE

mA

SYMBOL

VIH, VIL, V

-40°C +25°C +85°C

MIN TYP MAX MIN TYP MAX MIN TYP MAX

0.1

0.1 3.0 0.1 3.0 0.1 3.0

IHD

, V

-150 150 -150 150 -150 150

ILD

1.145

1.945

550 910 550 910 550 910

1.525

V

EE

0.865

1.695

1.325

0.1

1.145

1.945

1.525

V

EE

0.865

1.695

1.325

0.1

1.145

1.945

1.525

V

EE

0.865

1.695

1.325

41 48 45 55 49 65

MAX9315

1:5 Differential LVPECL/LVECL/HSTL
Clock and Data Driver

4 _______________________________________________________________________________________

AC ELECTRICAL CHARACTERISTICS

(VCC- VEE= 2.375V to 3.8V, outputs loaded with 50Ω ±1% to VCC- 2V, input frequency = 1.5GHz, input transition time = 125ps (20%
to 80%), SEL = high or low, EN = low, V

IHD

= VEE+ 1.2V to VCC, V

ILD

= VEEto VCC- 0.15V, V

IHD

- V

ILD

= 0.15V to the smaller of 3V or

V

CC

- VEE, unless otherwise noted. Typical values are at VCC- VEE= +3.3V, V

IHD

= VCC- 1V, V

ILD

= VCC- 1.5V.) (Notes 1, 7)

UNITS

PARAMETER

CONDITIONS

ps

Differential Input­to-Output Delay

t

PLHD

,

Figure 2

ps

Output-to-Output
Skew (Note 8)

5

ps

Part-to-Part Skew
(Note 9)

ps

Added Random
Jitter (Note 10)

t

RJ

p s ( RM S )

Added
Deterministic Jitter
(Note 10)

t

DJ

1.5Gbps 2E23-1
PRBS pattern

ps (p-p)

Switching
Frequency

f

MAX

(VOH - VOL) ≥
400mV,
Figure 2

GHz

Output Rise/Fall
Time (20% to 80%)

Figure 2

ps

Note 1: Measurements are made with the device in thermal equilibrium.
Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 3: DC parameters production tested at T

A

= +25°C and guaranteed by design over the full operating temperature range.

Note 4: Single-ended input operation using V

BB

is limited to VCC- VEE= 3.0V to 3.8V.

Note 5: Use V

BB

only for inputs that are on the same device as the VBBreference.

Note 6: All pins open except V

CC

and VEE.

Note 7: Guaranteed by design and characterization. Limits are set at ±6 sigma.
Note 8: Measured between outputs of the same part at the signal crossing points for a same-edge transition.
Note 9: Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge transition.
Note 10: Device jitter added to the input signal.

SYMBOL

-40°C +25°C +85°C

MIN TYP MAX MIN TYP MAX MIN TYP MAX

t

PHLD

t

SKOO

t

SKPP

fIN = 1.5GHz clock 0.8 1.2 0.8 1.2 0.8 1.2

tR, t

F

290 400 310 440 300 520

30 20 40 20 50

110 130 220

50 70 50 70 50 70

1.5 1.5 1.5

80 120 90 130 90 145

MAX9315

1:5 Differential LVPECL/LVECL/HSTL

Clock and Data Driver

_______________________________________________________________________________________ 5

40

43

42

41

44

45

46

47

48

49

50

-40 10-15 35 60 85

SUPPLY CURRENT vs. TEMPERATURE

MAX9315 toc01

TEMPERATURE (°C)

SUPPLY CURRENT (mA)

ALL PINS ARE
OPEN EXCEPT
V

CC

AND V

EE

DIFFERENTIAL OUTPUT VOLTAGE (VOH - VOL)

vs. FREQUENCY

MAX9315 toc02

FREQUENCY (GHz)

DIFFERENTIAL OUTPUT VOLTAGE (mV)

2.52.01.51.00.5

100

200

300

400

500

600

700

800

900

0

03.0

TRANSITION TIME vs. TEMPERATURE

MAX9315 toc03

TEMPERATURE (°C)

TRANSITION TIME (ps)

603510-15

90

100

110

120

130

140

80

-40 85

t

R

t

F

PROPAGATION DELAY vs. HIGH VOLTAGE

OF DIFFERENTIAL INPUT (V

IHD

)

MAX9315 toc04

V

IHD

(V)

PROPAGATION DELAY (ps)

3.02.72.42.11.81.5

346

352

358

364

370

340

1.2 3.3

360

350

340

330

370

380

390

-40 10-15 35 60 85

PROPAGATION DELAY vs. TEMPERATURE

MAX9315 toc05

TEMPERATURE (°C)

PROPAGATION DELAY (ps)

Typical Operating Characteristics

(VCC= +3.3V, VEE= 0, V

IHD

= VCC- 1V, V

ILD

= VCC- 1.15V, input transition time = 125ps (20% to 80%), fIN= 2GHz, outputs loaded

with 50Ω to V

CC

- 2V, TA= +25°C, unless otherwise noted.)

MAX9315

Detailed Description

The MAX9315 is a low-skew, 1-to-5 differential driver
designed for clock or data distribution. A 2-to-1 MUX
selects one of the two differential clock inputs, CLK0,
CLK0 or CLK1, CLK1. The MUX is switched by the sin­gle-ended SEL input. A logic low selects the CLK0,
CLK0 input and a logic high selects the CLK1, CLK1
input. The SEL logic threshold is set by the internal volt­age reference VBB. SEL can be driven to VCCand V

EE

or by a single-ended LVPECL/LVECL signal. The
selected input is reproduced at five differential outputs.

Synchronous Enable

The MAX9315 is synchronously enabled and disabled
with outputs in the low state to eliminate shortened
clock pulses. EN is connected to the input of an edge­triggered D flip-flop. After power-up, drive EN low and

toggle the selected clock input to enable the outputs.
The outputs are enabled on the falling edge of the
selected clock input after EN goes low. The outputs are
set to a low state on the falling edge of the selected
clock input after EN goes high. The threshold for EN is
equal to VBB.

Supply

For interfacing to differential HSTL and LVPECL signals,
the VCCrange is from +2.375V to +3.8V (with V

EE

grounded), allowing high-performance clock or data
distribution in systems with a nominal +2.5V or +3.3V
supply. For interfacing to differential LVECL, the V

EE

range is -2.375V to -3.8V (with VCCgrounded). Output
levels are referenced to VCCand are considered
LVPECL or LVECL, depending on the level of the V

CC

supply. With VCCconnected to a positive supply and

1:5 Differential LVPECL/LVECL/HSTL
Clock and Data Driver

6 _______________________________________________________________________________________

Pin Description

PIN NAME FUNCTION

1 Q0 Noninverting Q0 Output. Typically terminate with 50Ω resistor to VCC - 2V.
2 Q0 Inverting Q0 Output. Typically terminate with 50Ω resistor to VCC - 2V.
3 Q1 Noninverting Q1 Output. Typically terminate with 50Ω resistor to VCC - 2V.
4 Q1 Inverting Q1 Output. Typically terminate with 50Ω resistor to VCC - 2V.
5 Q2 Noninverting Q2 Output. Typically terminate with 50Ω resistor to VCC - 2V.
6 Q2 Inverting Q2 Output. Typically terminate with 50Ω resistor to VCC - 2V.
7 Q3 Noninverting Q3 Output. Typically terminate with 50Ω resistor to VCC - 2V.
8 Q3 Inverting Q3 Output. Typically terminate with 50Ω resistor to VCC - 2V.

9 Q4 Noninverting Q4 Output. Typically terminate with 50Ω resistor to VCC - 2V.
10 Q4 Inverting Q4 Output. Typically terminate with 50Ω resistor to VCC - 2V.
11 V

EE

Negative Supply Voltage

12 SEL

Clock Select Input (Single Ended). Drive low to select the CLK0, CLK0 input. Drive high to select the
CLK1, CLK1 input. The SEL threshold is equal to V

BB

.
13 CLK0 Noninverting Differential Clock Input 0. Internal 75kΩ pulldown to VEE.
14 CLK0 Inverting Differential Clock Input 0. Internal 75kΩ pullup to VCC and 75kΩ pulldown to VEE.

15 V

BB

Reference Output Voltage. Connect to the inverting or noninverting clock input to provide a
reference for single-ended operation. When used, bypass with a 0.01µF ceramic capacitor to V

CC

;

otherwise, leave open.

16 CLK1 Noninverting Differential Clock Input 1. Internal 75kΩ pulldown to VEE.
17 CLK1 Inverting Differential Clock Input 1. Internal 75kΩ pullup to VCC and 75kΩ pulldown to VEE.

18, 20 V

CC

Positive Supply Voltage. Bypass VCC to VEE with 0.1µF and 0.01µF ceramic capacitors. Place the
capacitors as close to the device as possible with the smaller value capacitor closest to the device.

19 EN

Output Enable Input. Outputs are synchronously enabled on the falling edge of the selected clock
input when EN is low. Outputs are synchronously driven low on the falling edge of the selected
clock input when EN is high.

VEEconnected to ground, the outputs are LVPECL. The
outputs are LVECL when VCCis connected to ground
and VEEis connected to a negative supply.

Input Bias Resistors

When the inputs are open, the internal bias resistors set
the inputs to low state. The inverting inputs (CLK0 and
CLK1) are each biased with a 75kΩ pullup to VCCand a
75kΩ pulldown to VEE. The noninverting inputs (CLK0
and CLK1) are each biased with a 75kΩ pulldown to V

EE

.

Differential Clock Input Limits

The maximum magnitude of the differential signal
applied to the clock input is 3.0V or V

CC

- VEE, whichev­er is less. This limit also applies to the difference
between any reference voltage input and a single-ended
input. Specifications for the high and low voltages of a
differential input (V

IHD

and V

ILD

) and the differential input

voltage (V

IHD

- V

ILD

) apply simultaneously.

Single-Ended Clock Input and V

BB

The differential clock inputs can be configured to
accept single-ended inputs. This is accomplished by
connecting the on-chip reference voltage, VBB, to the
inverting or noninverting input of a differential input as a
reference. For example, the differential CLK0, CLK0
input is converted to a noninverting, single-ended input
by connecting VBBto CLK0 and connecting the single­ended input signal to CLK0. Similarly, an inverting con­figuration is obtained by connecting VBBto CLK0 and
connecting the single-ended input to CLK0. With a dif­ferential input configured as single ended (using VBB),
the single-ended input can be driven to VCCand V

EE

or
with a single-ended LVPECL/LVECL signal. Note that
single-ended input must be at least VBB±100mV or a
differential input of at least 100mV to switch the outputs
to the VOHand VOLlevels specified in the DC Electrical

Characteristics table.
If VBBis used, the supply must be in the VCC- VEE=

+2.725V to +3.8V range because one of the inputs
must be VEE+ 1.2V or higher for proper input stage
operation. VBBmust be at least VEE+ 1.2V because it
becomes the high-level input when the other (single­ended) input swings below it. Therefore, minimum V

BB

= VEE+ 1.2V. The minimum VBBoutput of the
MAX9315 is VCC- 1.525V. Substituting the minimum
VBBoutput into VBB= VEE+ 1.2V results in a minimum
supply of +2.725V. Rounding up to standard supplies
gives the single-ended operating supply range of VCC­VEE= +3.0V to +3.8V.

When using the VBBreference output, bypass it with a

0.01µF ceramic capacitor to VCC. If the VBBreference
is not used, leave it open. The VBBreference can
source or sink 0.5mA, which is sufficient to drive two
inputs. Use VBBonly for inputs that are on the same
device as the V

BB

reference.

Applications Information

Supply Bypassing

Bypass VCCto VEEwith high-frequency surface-mount
ceramic 0.1µF and 0.01µF capacitors in parallel as
close to the device as possible, with the 0.01µF capaci­tor closest to the device. Use multiple parallel vias to
minimize parasitic inductance. When using the VBBref­erence output, bypass it with a 0.01µF ceramic capaci­tor to VCC(if the VBBreference is not used, it can be
left open).

Controlled-Impedance Traces

Input and output trace characteristics affect the perfor­mance of the MAX9315. Connect high-frequency input
and output signals with 50Ω characteristic impedance
traces. Minimize the number of vias to prevent imped­ance discontinuities. Reduce reflections by maintaining
the 50Ω characteristic impedance through cables and
connectors. Reduce skew within a differential pair by
matching the electrical length of the traces.

Output Termination

Terminate outputs with 50Ω to VCC- 2V or use an
equivalent Thevenin termination. When a single-ended
signal is taken from a differential output, terminate both
outputs. For example, if Q0 is used as a single-ended
output, terminate both Q0 and Q0.

Chip Information

TRANSISTOR COUNT: 616
PROCESS: Bipolar

MAX9315

1:5 Differential LVPECL/LVECL/HSTL

Clock and Data Driver

_______________________________________________________________________________________ 7

MAX9315

1:5 Differential LVPECL/LVECL/HSTL
Clock and Data Driver

8 _______________________________________________________________________________________

CLK

Q_

V

OH

V

OL

V

IH

V

IL

V

BB

(CLK IS CONNECTED TO VBB)

VOH - V

OL

CLK

Q_

Figure 1. MAX9315 Switching Characteristics with Single-Ended Input

CLK

CLK

Q_

Q_

t

PLHD

t

PHLD

VOH - V

OL

V

IHD

- V

ILD

V

IHD

V

ILD

Q_ - Q_

0 (DIFFERENTIAL) 0 (DIFFERENTIAL)

20%

80%

20%

80%

t

R

t

F

V

OL

V

OH

Figure 2. MAX9315 Timing Diagram

MAX9315

1:5 Differential LVPECL/LVECL/HSTL

Clock and Data Driver

_______________________________________________________________________________________ 9

t

S

t

H

t

S

t

PLHD

OUTPUTS ARE LOW OUTPUTS STAY LOW

EN

CLK

CLK

Q_
Q_

t

H

Figure 3. MAX9315 ENTiming Diagram

MAX9315

1:5 Differential LVPECL/LVECL/HSTL
Clock and Data Driver

10 ______________________________________________________________________________________

Functional Diagram

MAX9315

CLK0

CLK0

CLK1

SEL

EN

V

BB

V

CC

V

EE

V

EE

V

EE

V

EE

V

CC

0

1

Q

D

75kΩ

75kΩ

75kΩ

Q0

Q0

Q1

Q1

Q2

Q2

Q3

Q3

Q4

Q4

75kΩ

75kΩ

75kΩ

V

CC

CLK1

MAX9315

1:5 Differential LVPECL/LVECL/HSTL

Clock and Data Driver

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11

© 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

TSSOP4.40mm.EPS

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages

.)