MAXIM MAX9310A User Manual
General Description
The MAX9310A is a fast, low-skew 1:5 differential driver
with selectable LVPECL inputs and LVDS outputs,
designed for clock distribution applications. This device
features an ultra-low propagation delay of 340ps with
48mA of supply current.
The MAX9310A operates from a 3V to 3.6V power supply for use in 3.3V systems. A 2:1 input multiplexer is
used to select one of two differential inputs. The input
selection is controlled through the CLKSEL pin.
This device features a synchronous enable function.
The MAX9310A LVPECL inputs can be driven by either
a differential or single-ended signal. A VBBreference
voltage output is provided for use with single-ended
inputs. The device can also accept differential HSTL
signals.
The MAX9310A is offered in a space-saving 20-pin
TSSOP package and operates over the extended temperature range from -40°C to +85°C.
Applications
Data and Clock Drivers and Buffers
Central-Office Backplane Clock Distribution
DSLAM
Base Stations
ATE
Features
♦ Guaranteed 1.0GHz Operating Frequency
♦ 8.0ps Output-to-Output Skew
♦ 340ps Propagation Delay
♦ Accepts LVPECL and Differential HSTL Inputs
♦ Synchronous Output Enable/Disable
♦ Two Selectable Differential Inputs
♦ 3V to 3.6V Supply Voltage
♦ On-Chip Reference for Single-Ended Operation
♦ ESD Protection: ±2kV (Human Body Model)
♦ Input Bias Resistors Drive Output Low for Open
Inputs
MAX9310A
1:5 Clock Driver with Selectable LVPECL
Inputs/Single-Ended Inputs and LVDS Outputs
________________________________________________________________ Maxim Integrated Products 1
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
V
CC
EN
V
CC
CLK1Q1
Q1
QO
Q0
TOP VIEW
CLK1
V
BB
CLK0
CLK0Q3
Q3
Q2
Q2
12
11
9
10
CLKSEL
GNDQ4
Q4
MAX9310A
TSSOP
Pin Configuration
Ordering Information
100Ω
MAX9310A
ZO = 50Ω
Z
O
= 50Ω
RECEIVER
Q_
Q_
Typical Application Circuit
19-2542; Rev 0; 7/02
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Functional Diagram appears at end of data sheet.
PART TEMP RANGE PIN-PACKAGE
MAX9310AEUP
-40°C to +85°C 20 TSSOP
MAX9310A
1:5 Clock Driver with Selectable LVPECL
Inputs/Single-Ended Inputs and LVDS Outputs
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(VCC- GND = 3V to 3.6V, outputs terminated with 100Ω±1%, unless otherwise noted. Typical values are at VCC- GND = 3.3V, V
IHD
=
V
CC
- 1.0V, V
ILD
= VCC- 1.5V, unless otherwise noted.) (Notes 1, 2, and 3)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCCto GND...........................................................-0.3V to +4.1V
EN, CLKSEL, CLK_, CLK_, to GND............-0.3V to (VCC+ 0.3V)
CLK_ to CLK_.........................................................................±3V
Continuous Output Current .................................................24mA
Surge Output Current..........................................................50mA
V
BB
Sink/Source Current ...............................................±0.65mA
Continuous Power Dissipation (T
A
= +70°C)
Single-Layer PC Board
20-Pin TSSOP (derate 7.69mW/°C above +70°C) ......615mW
Multilayer PC Board
20-Pin TSSOP (derate 11mW/°C above +70°C) .........879mW
Junction-to-Ambient Thermal Resistance in Still Air
Single-Layer PC Board
20-Pin TSSOP .........................................................+130°C/W
Multilayer PC Board
20-Pin TSSOP ...........................................................+91°C/W
Junction-to-Ambient Thermal Resistance with 500LFPM
Airflow Single-Layer PC board
20-Pin TSSOP ...........................................................+96°C/W
Junction-to-Case Thermal Resistance
20-Pin TSSOP ...........................................................+20°C/W
Operating Temperature Range .......................... -40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
ESD Protection
Human Body Model (inputs and outputs) .......................±2kV
Lead Temperature (soldering, 10s) .................................+300°C
-40°C +25°C +85°C
PARAMETER
SYMBOL
CONDITIONS
UNITS
SINGLE-ENDED INPUTS (CLKSEL, EN)
Input High
Voltage
V
IH
VCC -
VCC -
VCC -
VCC -
VCC -
VCC -
V
Input Low
Voltage
V
IL
VCC -
VCC -
VCC -
VCC -
VCC -
VCC -
V
Input Current I
IN
V
IH(MAX)
,
V
IL(MAX)
µA
DIFFERENTIAL INPUTS (CLK_, CLK_)
Single-Ended
Input High
Voltage
V
IH
Figure 1
V
CC
-
VCC -
VCC -
VCC -
VCC -
VCC -
V
Single-Ended
Input Low
Voltage
V
IL
Figure 1
V
CC
-
VCC -
VCC -
VCC -
VCC -
VCC -
V
Differential Input
High Voltage
V
IHD
Figure 2
V
Differential Input
Low Voltage
V
ILD
Figure 2
VCC -
VCC -
VCC -
V
Differential Input
Voltage
V
ID
V
IHD
- V
ILD
3.0 V
Input Current
CLK_, or CLK_ =
V
IHD
or V
ILD
µA
MIN TYP MAX MIN TYP MAX MIN TYP MAX
IIH, I
IL
1.165
1.81
-10 +70 -10 +70 -10 +70
1.125
1.81
1.2 V
GND
0.095 3.0 0.095 3.0 0.095
-100 +100 -100 +100 -100 +100
0.88
1.475
0.88
1.475
CC
0.095
1.165
1.81
1.165
1.81
1.2 V
GND
0.88
1.475
0.88
1.475
CC
0.095
1.165
1.81
1.165
1.81
1.2 V
GND
0.88
1.475
0.88
1.495
CC
0.095
MAX9310A
1:5 Clock Driver with Selectable LVPECL
Inputs/Single-Ended Inputs and LVDS Outputs
_______________________________________________________________________________________ 3
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC- GND = 3V to 3.6V, outputs terminated with 100Ω±1%, unless otherwise noted. Typical values are at VCC- GND = 3.3V, V
IHD
=
V
CC
- 1.0V, V
ILD
= VCC- 1.5V, unless otherwise noted.) (Notes 1, 2, and 3)
-40°C +25°C +85°C
PARAMETER
SYMBOL
CONDITIONS
UNITS
OUTPUTS (Q_, Q_)
Output High
Voltage
V
OH
Figure 2
1.6 V
Output Low
Voltage
V
OL
Figure 2
V
Differential
Output Voltage
V
OD
VOH - VOL,
Figure 2
mV
Change in V
OD
Between
Complementary
Output States
∆V
OD
50 50 50
mV
Output Offset
Voltage
V
OS
mV
Change in VOS
Between
Complementary
Output States
25 25 25
mV
12 12 12
Output ShortCircuit Current
I
OSC
Q_ or Q_ shorted
to GND
29 29 29
mA
REFERENCE
Reference
Voltage Output
V
BB
IBB = ±0.65mA
(Note 4)
VCC -
VCC -
VCC -
VCC -
VCC -
VCC -
V
POWER SUPPLY
Power-Supply
Current
I
CC
(Note 5)
75
75 51 75
mA
MIN TYP MAX MIN TYP MAX MIN TYP MAX
0.9 0.9 0.9
250 350 450 250 350 450 250 350 450
1.125 1.25 1.375 1.125 1.25 1.375 1.125 1.25 1.375
∆VOCM
Q_ shorted to Q_
1.6 1.6
1.38
45
1.22
1.38
1.26
48
1.40
1.26
MAX9310A
4 _______________________________________________________________________________________
Note 1: Measurements are made with the device in thermal equilibrium.
Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 3: DC parameters are production tested at +25°C. DC limits are guaranteed by design and
characterized over the full operating temperature range.
Note 4: Use V
BB
only for inputs that are on the same device as the VBBreference.
Note 5: All pins are open except V
CC
and GND, all outputs are loaded with 100Ω differentially.
Note 6: Guaranteed by design and characterization. Limits are set to ±6 sigma.
Note 7: Measured between outputs of the same part at the signal crossing points for a same-edge
transition.
Note 8: Measured between outputs of different parts at the signal crossing points under identical conditions
for a same-edge transition.
Note 9: Device jitter added to the input signal.
AC ELECTRICAL CHARACTERISTICS
(VCC- GND = 3V to 3.6V, outputs terminated with 100Ω±1%, fIN≤ 1.0GHz, input transition time = 125ps (20% to 80%),
V
IHD
- V
ILD
= 0.15V to VCC, unless otherwise noted. Typical values are at VCC- GND = 3.3V, V
IHD
= VCC- 1.0V, V
ILD
= VCC- 1.5V,
unless otherwise noted.) (Notes 1 and 6)
-40°C +25°C +85°C
PARAMETER
SYMBOL
CONDITIONS
UNITS
Propagation
Delay CLK_,
CLK_ to Q_, Q_
t
PHL
,
t
PLH
Figure 2
ps
Output-toOutput Skew
(Note 7) 10 30 8 25 20 45 ps
Part-to-Part
Skew
t
SKPP
(Note 8)
ps
Added Random
Jitter
t
RJ
fIN = 1.0GHz,
clock pattern
(Note 9)
ps
(RMS)
Added
Deterministic
Jitter
t
DJ
fIN = 1.0Gsps,
2
23
- 1 PRBS
50 60 50 60 50 60
ps
(P-P)
Operating
Frequency
f
MAX
VOD ≥ 250mV
GHz
Differential
Output Rise/Fall
Time
t
R/tF
20% to 80%,
Figure 2
ps
1:5 Clock Driver with Selectable LVPECL
Inputs/Single-Ended Inputs and LVDS Outputs
MIN TYP MAX MIN TYP MAX MIN TYP MAX
250 340 600 250 340 600 250 340 600
t
SKOO
145 145 145
0.3 1.0 0.3 1.0 0.3 1.0
pattern (Note 9)
1.0 1.0 1.0
140 205 300 140 205 300 140 205 300
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