MAXIM MAX9270 Technical data

19-5657; Rev 1; 1/11
Gigabit Multimedia Deserializer with Spread
Spectrum and Full-Duplex Control Channel
The MAX9270 deserializer uses Maxim’s gigabit multimedia serial link (GMSL) technology. The device functions the same as the MAX9260 deserializer without an output enable (ENABLE) pin. Outputs are enabled or disabled by a register bit. The deserializer pairs with any GMSL serializer to form a complete digital serial link for joint transmission of high-speed video, audio, and control data.
The deserializer accepts a maximum serial payload data rate of 2.5Gbps for a 15m shielded twisted-pair (STP) cable. The 24-bit or 32-bit width parallel interface operates up to a maximum bus clock of 104MHz or 78MHz, respectively. This serial link supports display panels from QVGA (320 x 240) up to XGA (1280 x 768), or dual-view WVGA (2 x 854 x 480).
The 24-bit or 32-bit mode handles 21 or 29 bits of data, along with an I2S input, supporting 4- to 32-bit audio word lengths and an 8kHz to 192kHz sample rate. The embedded control channel forms a full-duplex, differen­tial 100kbps to 1Mbps UART link between the serializer and deserializer. The host electronic control unit (ECU) or microcontroller (FC) resides either on the serializer (for video display) or the deserializer (for image sensing). In addition, the control channel enables ECU/FC control of peripherals in the remote side of the serial link through I2C (base mode) or a user-defined full-duplex UART format (bypass mode).
The channel equalizer extends the link length and enhances the link reliability. Spread spectrum is avail­able to reduce EMI on the parallel output data signals. The differential link complies with the ISO 10605 and IEC 61000-4-2 ESD-protection standards.
This device uses a 3.3V core supply and a 1.8V to 3.3V I/O supply. The device is available in a 56-pin TQFN package (8mm x 8mm x 0.75mm) with an exposed pad. Electrical performance is guaranteed over the -40NC to +105NC automotive temperature range.
Applications
High-Speed Serial-Data Transmission for Display
High-Speed Serial-Data Transmission for Image Sensing
Automotive Navigation, Infotainment, and Image­Sensing Systems
Features
S Pairs with Any GMSL Serializer S 2.5Gbps Payload Rate, AC-Coupled Serial Link
with 8b/10b Line Coding
S 24-Bit or 32-Bit Programmable Parallel Output Bus
Supports Up to XGA (1280 x 768) or Dual-View WVGA (2 x 854 x 480) Panels with 18-Bit or 24-Bit Color
S 8.33MHz to 104MHz (24-Bit Bus) or 6.25MHz to
78MHz (32-Bit Bus) Parallel Data Rate
S Support Two/Three 10-Bit Camera Links at
104MHz/78MHz Maximum Pixel Clock
S 4-Bit to 32-Bit Word Length, 8kHz to 192kHz I
Audio Channel Supports High-Definition Audio
S Embedded Half-/Full-Duplex Bidirectional Control
Channel (100kbps to 1Mbps)
S Separate Interrupt Signal Supports Touch-Screen
Functions for Display Panels
S Remote-End I S Line Equalizer Extends Link Length S Programmable Spread Spectrum on the Parallel
Data Outputs Reduce EMI
S Does Not Require an External Clock S Auto Data-Rate Detection Allows “On-The-Fly”
Data-Rate Change
S Built-In PRBS Checker for BER Testing S ISO 10605 and IEC 61000-4-2 ESD Protection S -40NC to +105NC Operating Temperature Range S Patent Pending
2
C Master for Peripherals
2
S
Ordering Information
PART TEMP RANGE PIN-PACKAGE
MAX9270GTN/V+
/V denotes an automotive qualified part.
+Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad.
T = Tape and reel.
Typical Applications Circuit appears at end of data sheet.
-40NC to +105NC
56 TQFN-EP*
MAX9270
_______________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Gigabit Multimedia Deserializer with Spread Spectrum and Full-Duplex Control Channel
ABSOLUTE MAXIMUM RATINGS
AVDD to EP ..........................................................-0.5V to +3.9V
DVDD to EP ..........................................................-0.5V to +3.9V
IOVDD to EP .........................................................-0.5V to +3.9V
IN+, IN- to EP .......................................................-0.5V to +1.9V
All Other Pins to EP .............................. -0.5V to (IOVDD + 0.5V)
IN+, IN- Short Circuit to Ground or
Supply .................................................................... Continuous
Continuous Power Dissipation (TA = +70NC)
MAX9270
56-Pin TQFN (derate 47.6mW/NC above +70NC) ....3809.5mW
ESD Protection Human Body Model (RD = 1.5kI, CS = 100pF)
(IN+, IN-) to EP .............................................................Q8kV
All Other Pins to EP ......................................................Q4kV
PACKAGE THERMAL CHARACTERISTICS (Note 1)
56 TQFN
Junction-to-Ambient Thermal Resistance (ΘJA) ..........21NC/W
Junction-to-Case Thermal Resistance (ΘJC).................1NC/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
IEC 61000-4-2 (RD = 330I, CS = 150pF) Contact Discharge
(IN+, IN-) to EP .............................................................Q8kV
Air Discharge
(IN+, IN-) to EP ...........................................................Q10kV
ISO 10605 (RD = 2kI, CS = 330pF) Contact Discharge
(IN+, IN-) to EP ............................................................Q8kV
Air Discharge
(IN+, IN-) to EP ...........................................................Q20kV
Operating Temperature Range ........................ -40NC to +105NC
Junction Temperature .....................................................+150NC
Storage Temperature Range ............................ -65NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
= V
DVDD
TA = -40NC to +105NC, unless otherwise noted. Typical values are at V
SINGLE-ENDED INPUTS (ENABLE, INT, PWDN, SSEN, BWS, ES, DRS, MS, CDS, EQS, DCS)
High-Level Input Voltage V
Low-Level Input Voltage V
Input Current I Input Clamp Voltage V
SINGLE-ENDED OUTPUTS (DOUT_, SD, WS, SCK, PCLKOUT)
High-Level Output Voltage V
Low-Level Output Voltage V
= 3.0V to 3.6V, V
AVDD
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
= 1.7V to 3.6V, RL = 100I Q1% (differential), EP connected to PCB ground (GND),
IOVDD
IH1
IL1
IN1
CL
OH
OL1
= V
DVDD
VIN = 0 to V ICL = -18mA -1.5 V
IOH = -2mA
IOL = 2mA
IOVDD
V
DCS
V
DCS
V
DCS
V
DCS
= V
= V
= V = V
GND
IOVDD
GND
IOVDD
AVDD
= V
= 3.3V, TA = +25NC.)
IOVDD
0.65 x
V
IOVDD
-10 +10
V
IOVDD
- 0.3
V
IOVDD
- 0.2
0.35 x
V
IOVDD
0.3
0.2
V
V
FA
V
V
2 ______________________________________________________________________________________
Gigabit Multimedia Deserializer with Spread
Spectrum and Full-Duplex Control Channel
DC ELECTRICAL CHARACTERISTICS (continued)
(V
= V
DVDD
TA = -40NC to +105NC, unless otherwise noted. Typical values are at V
Output Short-Circuit Current I
I2C AND UART I/O, OPEN-DRAIN OUTPUTS (RX/SDA, TX/SCL, ERR, GPIO_, LOCK)
High-Level Input Voltage V
Low-Level Input Voltage V
Input Current I
Low-Level Open-Drain Output Voltage
DIFFERENTIAL OUTPUTS FOR REVERSE CONTROL CHANNEL (IN+, IN-)
Differential High Output Peak Voltage, (VIN+) - (VIN-)
Differential Low Output Peak Voltage, (VIN+) - (VIN-)
DIFFERENTIAL INPUTS (IN+, IN-)
Differential High Input Threshold (Peak), (VIN+) - (VIN-)
Differential Low Input Threshold (Peak), (VIN+) - (VIN-)
Input Common-Mode Voltage, ((VIN+) + (VIN-))/2
Differential Input Resistance (Internal)
= 3.0V to 3.6V, V
AVDD
= 1.7V to 3.6V, RL = 100I Q1% (differential), EP connected to PCB ground (GND),
IOVDD
= V
DVDD
AVDD
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
V
IOVDD
3.0V to 3.6V
V
IOVDD
1.7V to 1.9V
V
IOVDD
3.0V to 3.6V
V
IOVDD
DOUT_, SD, WS, SCK
VO = 0V, V
= V
DCS
VO = 0V, V
= V
DCS
GND
IOVDD
1.7V to 1.9V
OS
PCLKOUT
VO = 0V, V
= V
DCS
VO = 0V, V
= V
DCS
GND
IOVDD
V
IOVDD
3.0V to 3.6V
V
IOVDD
1.7V to 1.9V
V
IOVDD
3.0V to 3.6V
V
IOVDD
1.7V to 1.9V
IH2
IL2
IN2
V
OL2
V
ROH
V
ROL
V
IDH(P)
V
IDL(P)
V
CMR
VIN = 0 to V
IOVDD
(Note 2)
IOL = 3mA
No high-speed data transmission (Figure 1)
No high-speed data transmission (Figure 1)
(Figure 2) 40 90 mV
(Figure 2) -90 -40 mV
R
I
RX/SDA, TX/SCL -110 +1 GPIO, ERR, LOCK
V
= 1.7V to 1.9V 0.4 V
IOVDD
V
= 3.0V to 3.6V 0.3 V
IOVDD
= V
=
=
=
=
=
=
=
=
= 3.3V, TA = +25NC.)
IOVDD
15 25 39
3 7 13
20 35 63
5 10 21
15 33 50
5 10 17
30 54 97
9 16 32
0.7 x
V
IOVDD
-80 +1
30 60 mV
-60 -30 mV
1 1.3 1.6 V
80 100 130
0.3 x
V
IOVDD
MAX9270
mA
V
V
FA
I
_______________________________________________________________________________________ 3
Gigabit Multimedia Deserializer with Spread Spectrum and Full-Duplex Control Channel
DC ELECTRICAL CHARACTERISTICS (continued)
(V
= V
DVDD
TA = -40NC to +105NC, unless otherwise noted. Typical values are at V
POWER SUPPLY
MAX9270
Worst-Case Supply Current (Figure 3)
Sleep-Mode Supply Current I Power-Down Supply Current I
= 3.0V to 3.6V, V
AVDD
= 1.7V to 3.6V, RL = 100I Q1% (differential), EP connected to PCB ground (GND),
IOVDD
DVDD
= V
AVDD
= V
= 3.3V, TA = +25NC.)
IOVDD
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
I
WCS
CCS
CCZ
V
= V
BWS
f
PCLKOUT
V
= V
BWS
f
PCLKOUT
V
= V
BWS
f
PCLKOUT
V
= V
BWS
f
PCLKOUT
V
PWDN
,
GND
= 16.6MHz
,
GND
= 33.3MHz
,
GND
= 66.6MHz
,
GND
= 104MHz
= V
GND
2% spread spectrum active
Spread spectrum disabled
2% spread spectrum active
Spread spectrum disabled
2% spread spectrum active
Spread spectrum disabled
2% spread spectrum active
Spread spectrum disabled
113 166
105 155
122 181
110 165
137 211
120 188
159 247
135 214
80 130 19 70
mA
FA FA
AC ELECTRICAL CHARACTERISTICS
(V
= V
DVDD
TA = -40NC to +105NC, unless otherwise noted. Typical values are at V
PARALLEL CLOCK OUTPUT (PCLKOUT)
Clock Frequency f
Clock Duty Cycle DC t
Clock Jitter t
I2C/UART PORT TIMING
Output Rise Time t
Output Fall Time t
Input Setup Time t Input Hold Time t
4 ______________________________________________________________________________________
= 3.0V to 3.6V, V
AVDD
= 1.7V to 3.6V, RL = 100I Q1% (differential), EP connected to PCB ground (GND),
IOVDD
DVDD
= V
AVDD
= V
= 3.3V, TA = +25NC.)
IOVDD
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
V
PCLKOUT
J
R
F
SET
HOLD
= V
BWS
V
= V
BWS
V
= V
BWS
V
= V
BWS
HIGH/tT
Period jitter, RMS, spread off, 3.125Gbps, PRBS pattern, UI = 1/f
30% to 70%, CL = 10pF to 100pF, 1kI pullup to IOVDD
70% to 30%, CL = 10pF to 100pF, 1kI pullup to IOVDD
I2C only (Figure 5) 100 ns I2C only (Figure 5) 0 ns
GND
GND
IOVDD
IOVDD
or t
, V
= V
, V
, V , V
LOW/tT
DRS
DRS
IOVDD
= V
GND
= V
DRS
DRS
= V
IOVDD
GND
(Figure 4) 40 50 60 %
PCLKOUT
8.33 16.66
16.66 104
6.25 12.5
12.5 78
0.05 UI
20 150 ns
20 150 ns
MHz
Gigabit Multimedia Deserializer with Spread
Spectrum and Full-Duplex Control Channel
AC ELECTRICAL CHARACTERISTICS (continued)
(V
= V
DVDD
TA = -40NC to +105NC, unless otherwise noted. Typical values are at V
SWITCHING CHARACTERISTICS
PCLKOUT Rise-and-Fall Time tR, t
Parallel Data Rise-and-Fall Time (Figure 6)
Deserializer Delay t
Lock Time t
Power-Up Time t
Reverse Control-Channel Output Rise Time
Reverse Control-Channel Output Fall Time
I2S OUTPUT TIMING
WS Jitter t
SCK Jitter t
= 3.0V to 3.6V, V
AVDD
= 1.7V to 3.6V, RL = 100I Q1% (differential), EP connected to PCB ground (GND),
IOVDD
DVDD
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
20% to 80%, V
= 1.7V to 1.9V
IOVDD
F
20% to 80%, V
= 3.0V to 3.6V
IOVDD
20% to 80%, V
= 1.7V to 1.9V
IOVDD
tR, t
F
20% to 80%, V
= 3.0V to 3.6V
IOVDD
SD
LOCK
PU
t
t
Spread spectrum enabled (Figure 7) 2880 Spread spectrum disabled (Figure 7) 750 Spread spectrum enabled (Figure 8) 1500 Spread spectrum off (Figure 8) 1000 (Figure 9) 2500
No high-speed transmission (Figure 1) 180 400 ns
R
No high-speed transmission (Figure 1) 180 400 ns
F
fWS = 48kHz or
44.1kHz
AJ-WS
tWS = 1/fWS, rising (falling) edge to falling (rising) edge (Note 3)
fWS = 192kHz
nWS = 16 bits, fWS = 48kHz or 44.1kHz
t
AJ-SCK
= 1/f
SCK
ing edge to rising edge
SCK
, ris-
nWS = 24 bits, fWS = 96kHz
nWS = 32 bits, fWS = 192kHz
= V
AVDD
V
= V
DCS
CL = 10pF
V
= V
DCS
CL = 5pF
V
= V
DCS
CL = 10pF
V
= V
DCS
CL = 5pF
V
= V
DCS
CL = 10pF
V
= V
DCS
CL = 5pF
V
= V
DCS
CL = 10pF
V
= V
DCS
CL = 5pF
= V
IOVDD
GND
IOVDD
GND
IOVDD
GND
IOVDD
GND
IOVDD
,
,
,
,
,
,
,
,
= 3.3V, TA = +25NC.)
0.4 2.2
0.5 2.8
0.25 1.7
0.3 2.0
0.5 3.1
0.6 3.8
0.3 2.2
0.4 2.4
0.4e - 3 x t
0.8e - 3 x t
1.6e - 3 x t
13e - 3
x t
39e - 3
x t
x t
WS
WS
WS
SCK
SCK
0.1
SCK
0.5e - 3 x t
1e - 3 x t
2e - 3 x t
16e - 3
x t
SCK
48e - 3
x t
SCK
0.13
x t
SCK
WS
WS
WS
MAX9270
ns
ns
Bits
Fs
Fs
nsfWS = 96kHz
ns
_______________________________________________________________________________________ 5
Gigabit Multimedia Deserializer with Spread Spectrum and Full-Duplex Control Channel
AC ELECTRICAL CHARACTERISTICS (continued)
(V
= V
DVDD
TA = -40NC to +105NC, unless otherwise noted. Typical values are at V
Audio Skew Relative to Video
SCK, SD, WS Rise-and-Fall Time tR, t
MAX9270
SD, WS Valid Time Before SCK t
SD, WS Valid Time After SCK t
Note 2: Minimum IIN due to voltage drop across the internal pullup resistor. Note 3: Rising to rising edge jitter can be twice as large.
Typical Operating Characteristics
(V
= V
DVDD
= 3.0V to 3.6V, V
AVDD
= 1.7V to 3.6V, RL = 100I Q1% (differential), EP connected to PCB ground (GND),
IOVDD
DVDD
= V
AVDD
= V
= 3.3V, TA = +25NC.)
IOVDD
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Video and audio synchronized 3 x tWS4 x t
V
F
20% to 80%
t
= 1/f
SCK
t
SCK
= 1/f
SCK
SCK
= V
DCS
V
= V
DCS
(Figure 11)
(Figure 11)
, CL = 10pF 0.3 3.1 ns
IOVDD
, CL = 5pF 0.4 3.8 ns
GND
0.35
x t
SCK
0.35
x t
SCK
x t
x t
WS
0.5
SCK
0.5
SCK
AVDD
= V
ASK
DVB
DVA
= 3.3V, TA = +25NC, unless otherwise noted.)
IOVDD
µs
ns
ns
vs. PCLKOUT FREQUENCY (24-BIT MODE)
SUPPLY CURRENT
155
ALL EQUALIZER SETTINGS
150
145
140
135
130
125
120
SUPPLY CURRENT (mA)
115
110
105
5 105
PCLKOUT FREQUENCY (MHz)
SUPPLY CURRENT
vs. PCLKOUT FREQUENCY (32-BIT MODE)
180
170
160
150
140
130
SUPPLY CURRENT (mA)
120
110
100
2%, 4% SPREAD
NO SPREAD
5 80
PCLKOUT FREQUENCY (MHz)
vs. PCLKOUT FREQUENCY (32-BIT MODE)
155
ALL EQUALIZER SETTINGS
150
MAX9270 toc01
145
140
135
130
125
120
SUPPLY CURRENT (mA)
115
110
85654525
105
5 80
PCLKOUT FREQUENCY (MHz)
65503520
MAX9270 toc02
vs. PCLKOUT FREQUENCY (24-BIT MODE)
180
170
160
150
140
130
SUPPLY CURRENT (mA)
120
110
100
5 105
OUTPUT POWER SPECTRUM
vs. PCLKOUT FREQUENCY
SUPPLY CURRENT
0
f
= 42MHz
PCLKOUT
-10
MAX9270 toc04
655020 35
0% SPREAD
-20
-30
-40
-50
-60
PCLKOUT OUTPUT POWER (dBm)
-70
-80
2% SPREAD
39 45
PCLKOUT FREQUENCY (MHz)
4% SPREAD
444340 41 42
MAX9270 toc05
FREQUENCY (MHz)
120
100
80
60
40
20
0
0 20
SUPPLY CURRENT
2%, 4% SPREAD
NO SPREAD
856525 45
PCLKOUT FREQUENCY (MHz)
MAXIMUM PCLKIN FREQUENCY vs.
STP CABLE LENGTH (BER < 10
OPTIMUM PE/EQ
SETTINGS
NO PE, EQS = LOW
NO PE, EQS = HIGH
BER CAN BE < 10 CABLE LENGTHS LESS THAN 10m
-12
FOR
CABLE LENGTH (m)
-9
15105
MAX9270 toc03
)
MAX9270 toc06
6 ______________________________________________________________________________________
Gigabit Multimedia Deserializer with Spread
Spectrum and Full-Duplex Control Channel
Pin Configuration
TOP VIEW
DOUT20
DOUT21
EP*
MS
DVDD
DOUT22
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RX/SDA
DOUT23
DOUT24
IOVDD
DOUT25
DOUT26
DOUT27
DOUT28/MCLK
SD
SCK
WS
LOCK
ERR
PWDN
TX/SCL
DOUT12
DOUT11
DOUT10
42 41 40 39 38 37 36 35 34 33 32 31 30 29
DOUT9
43
DOUT8
44
IOVDD
45
DOUT7
46
DOUT6
47
DOUT5
48
DOUT4
49
DOUT3
50
DOUT2
51
52
DOUT1
53
DOUT0
54
SSEN
55
DRS
AVDD
*CONNECT EP TO GROUND PLANE
+
56
1 2 3 4 5 6 7 8 9 10 11 12 13 14
INT
CDS
BWS
DOUT14
DOUT13
ES
GPIO0
PCLKOUT
DOUT15
MAX9270
IN+
AVDD
TQFN
DOUT17
DOUT16
IN-
EQS
DOUT19
DOUT18
DCS
GPIO1
MAX9270
Pin Description
PIN NAME FUNCTION
Bus-Width Select. Parallel output bus-width selection input requires external pulldown
1 BWS
2 INT
3 CDS
4 GPIO0
5 ES
_______________________________________________________________________________________ 7
or pullup resistors. Set BWS = low for 24-bit bus mode. Set BWS = high for 32-bit bus mode.
Interrupt. Interrupt input requires external pulldown or pullup resistors. A transition on the INT input of the deserializer toggles the serializer’s INT output.
Control-Direction Selection. Control-link-direction selection input requires external pull­down or pullup resistors. Set CDS = low for FC use on the serializer side of the serial link. Set CDS = high for FC use on the deserializer side of the serial link.
GPIO0. Open-drain general-purpose input/output with internal 60kI pullup resistors to IOVDD. GPIO0 is high impedance during power-up and when PWDN = low.
Edge Select. PCLKOUT edge-selection input requires external pulldown or pullup resistors. Set ES = low for a rising-edge trigger. Set ES = high for a falling-edge trigger.
Gigabit Multimedia Deserializer with Spread Spectrum and Full-Duplex Control Channel
Pin Description (continued)
PIN NAME FUNCTION
6, 56 AVDD
7, 8 IN+, IN- Differential CML Input +/-. Differential inputs of the serial link.
MAX9270
9 EQS
10 GPIO1
11 DCS
12 MS
3.3V Analog Power Supply. Bypass AVDD to EP with 0.1µF and 0.001µF capacitors as close as possible to the device with the smallest value capacitor closest to AVDD.
Equalizer Select. Deserializer equalizer-selection input requires external pulldown or pullup resistors. The state of EQS latches upon power-up or rising edge of PWDN. Set EQS = low for 10.7dB equalizer boost (EQTUNE = 1001). Set EQS = high for 5.2dB equalizer boost (EQTUNE = 0100).
GPIO1. Open-drain general-purpose input/output with internal 60kI pullup resistors to IOVDD. GPIO1 is high impedance during power-up and when PWDN = low.
Drive Current Select. Driver current-selection input requires external pulldown or pullup resistors. Set DCS = high for stronger parallel data and clock output driv­ers. Set DCS = low for normal parallel data and clock drivers (see the DC Electrical Characteristics table).
Mode Select. Control-link mode-selection/autostart mode selection input requires external pulldown or pullup resistors. MS sets the control-link mode when CDS = high (see the Control-Channel and Register Programming section). Set MS = low to select base mode. Set MS = high to select the bypass mode. MS sets autostart mode when CDS = low (see Tables 13 and 14).
13 DVDD
14 RX/SDA
15 TX/SCL
16
17
18 LOCK
19 WS Word Select. I2S word-select output. 20 SCK Serial Clock. I2S serial-clock output
21 SD
PWDN
ERR
3.3V Digital Power Supply. Bypass DVDD to EP with 0.1FF and 0.001FF capacitors as close as possible to the device with the smaller value capacitor closest to DVDD.
Receive/Serial Data. UART receive or I2C serial-data input/output with internal 30kI pullup to IOVDD. In UART mode, RX/SDA is the Rx input of the deserializer’s UART. In I2C mode, RX/SDA is the SDA input/output of the serializer’s I2C master.
Transmit/Serial Clock. UART transmit or I2C serial-clock output with internal 30kI pullup to IOVDD. In UART mode, TX/SCL is the Tx output of the serializer’s UART. In I2C mode, TX/SCL is the SCL output of the deserializer’s I2C master.
Power-Down. Active-low power-down input requires external pulldown or pullup resis­tors.
Error. Active-low open-drain video data error output with internal pullup to IOVDD. ERR goes low when the number of decoding errors during normal operation exceed a programmed error threshold or when at least one PRBS error is detected during PRBS test. ERR is high impendence when PWDN = low.
Open-Drain Lock Output with Internal Pullup to IOVDD. LOCK = high indicates PLLs are locked with correct serial-word-boundary alignment. LOCK = low indicates PLLs are not locked or incorrect serial-word-boundary alignment. LOCK remains low when the configuration link is active. LOCK is high impedance when PWDN = low.
Serial Data. I2S serial-data output. Disable I2S to use SD as an additional data output latched on the selected edge of PCLKOUT.
8 ______________________________________________________________________________________
Gigabit Multimedia Deserializer with Spread
Spectrum and Full-Duplex Control Channel
Pin Description (continued)
PIN NAME FUNCTION
DOUT28/MCLK,
DOUT27, DOUT26,
22–25, 27–35,
37–44, 46–53
26, 45 IOVDD
36 PCLKOUT Parallel Clock Output. Used for DOUT0–DOUT28.
54 SSEN
55 DRS
EP
DOUT25,
DOUT24–DOUT16,
DOUT15–DOUT8,
DOUT7–DOUT0
Data Output[0:28]. Parallel data outputs. Output data can be strobed on the selected edge of PCLKOUT. Set BWS = low (24-bit mode) to use DOUT0–DOUT20 (RGB and SYNC). DOUT21–DOUT28 are not used in 24-bit mode and are set to low. Set BWS = high (32-bit mode) to use DOUT0–DOUT28 (RGB, SYNC, and two extra outputs). DOUT28 can be used to output MCLK (see the Additional MCLK Output for Audio Applications section).
1.8V to 3.3V Logic I/O Power Supply. Bypass IOVDD to EP with 0.1FF and 0.001FF capacitors as close as possible to the device with the smaller value capacitor closest to IOVDD.
Spread-Spectrum Enable. Parallel output spread-spectrum enable input requires external pulldown or pullup resistors. The state of SSEN latches upon power-up or when resuming from power-down mode (PWDN = low). Set SSEN = high for Q2% spread spectrum on the parallel outputs. Set SSEN = low to use the parallel outputs without spread spectrum.
Data-Rate Select. Data-rate range-selection input requires external pulldown or pullup resistors. Set DRS = high for parallel input data rates of 8.33MHz to 16.66MHz (24-bit mode) or 6.25MHz to 12.5MHz (32-bit mode). Set DRS = low for parallel input data rates of 16.66MHz to 104MHz (24-bit mode) or 12.5MHz to 78MHz (32-bit mode).
Exposed Pad. EP functions as the IC’s ground connection. MUST connect EP to the ground plane to maximize thermal and electrical performance.
MAX9270
_______________________________________________________________________________________ 9
Gigabit Multimedia Deserializer with Spread Spectrum and Full-Duplex Control Channel
Functional Diagram
LFLT
MAX9270
PCLKIN
DIN[N:0]
WS, SD, SCK
TX/SCL
RX/SDA
PCLKOUT
DOUT[N:0]
AUDIO
FIFO
FIFO
FIFO
PRBS
GEN
FILTER
PLL
CLKDIV
8b/10b
ENCODE
PARITY
UART/I2C
GMSL SERIALIZER
SPREAD
PLL
CLKDIV
8b/10b
DECODE
PARITY
SPREAD
PLL
P S
CDR PLL
P S
LINE-
FAULT
CML
TERM
REV CH
Rx
CML
DET
Tx
EQ
Rx
LMN0
LMN1
OUT+
OUT-
STP CABLE
= 50)
(Z
0
WS, SD, SCK
TX/SCL
RX/SDA
AUDIO
FIFO
PRBS
CHECK
UART/I2C
TERM
MAX9270
REV CH
Tx
DESERIALIZER
IN-
IN+
10 _____________________________________________________________________________________
Gigabit Multimedia Deserializer with Spread
Spectrum and Full-Duplex Control Channel
R
/2
L
V
OD
V
RL/2
CMR
MAX9270
CONTROL-CHANNEL
REVERSE
TRANSMITTER
IN+
IN-
MAX9270
IN+
V
CMR
IN-
V
ROH
0.9 x V
ROH
0.1 x V
(IN+) - (IN-)
ROH
t
R
Figure 1. Reverse Control-Channel Output Parameters
0.1 x V
0.9 x V
ROL
ROL
IN+
IN-
V
ROL
t
F
R
/2
L
RL/2
V
IN+
+
_
C
+
V
IN-
_
IN
V
V
V
ID(P) =
CMR =
ID(P)
IN+
IN-
C
IN
| V
- V
IN+
IN-
(V
+ V
IN+
IN-
Figure 2. Test Circuit for Differential Input Measurement
______________________________________________________________________________________ 11
PCLKOUT
_
DOUT_
NOTE: PCLKOUT PROGRAMMED FOR RISING LATCH EDGE.
|
)/2
Figure 3. Worst-Case Pattern Output
Gigabit Multimedia Deserializer with Spread Spectrum and Full-Duplex Control Channel
t
T
V
V
PCLKOUT
t
HIGH
OH MIN
OL MAX
MAX9270
Figure 4. Clock Output High-and-Low Times
TX/
SCL
RX/
SDA
P
Figure 5. I2C Timing Parameters
S
t
LOW
t
R
t
HOLD
t
F
t
SET
S
P
C
L
MAX9270
SINGLE-ENDED OUTPUT LOAD
0.8 x V
I0VDD
0.2 x V
I0VDD
t
R
t
F
Figure 6. Output Rise-and-Fall Times
12 _____________________________________________________________________________________
Gigabit Multimedia Deserializer with Spread
Spectrum and Full-Duplex Control Channel
SERIAL-WORD LENGTH
SERIAL WORD N
IN+/-
SERIAL WORD N+1 SERIAL WORD N+2
MAX9270
FIRST BIT
DOUT_
PCLKOUT
NOTE: PCLKOUT PROGRAMMED FOR RISING LATCHING EDGE.
Figure 7. Deserializer Delay
LAST BIT
PARALLEL WORD N-2
IN+ - IN-
LOCK
PARALLEL WORD N-1 PARALLEL WORD N
t
SD
t
LOCK
V
OH
Figure 8. Lock Time
Figure 9. Power-Up Delay
______________________________________________________________________________________ 13
IN+/-
LOCK
PWDN
PWDN MUST BE HIGH
V
IH1
t
PU
V
OH
Gigabit Multimedia Deserializer with Spread Spectrum and Full-Duplex Control Channel
WS
SCK
MAX9270
SD
Figure 10. Output I2S Timing Parameters
Detailed Description
The MAX9270 deserializer utilizes Maxim’s GMSL tech­nology. This device pairs with any GMSL serializer to form a complete digital serial link for joint transmission of high-speed video, audio, and control data for video­display or image-sensing applications. The MAX9270 functions the same as the MAX9260 without an output enable pin (ENABLE). Outputs are enabled by default and programmable by a register bit. The serial-payload data rate can reach up to 2.5Gbps for a 15m STP cable. The parallel interface is programmable for 24-bit or 32-bit width modes at the maximum bus clock of 104MHz or 78MHz, respectively. The minimum bus clock is 6.25MHz for the 32-bit mode and 8.33MHz for the 24-bit mode. With such a flexible data configuration, the GMSL is able to support XGA (1280 x 768) or dual-view WVGA (2 x 854 x 480) display panels. For image sensing, it supports three 10-bit camera links simultaneously with a pixel clock up to 78MHz. The 24-bit mode handles 21-bit data and control signals plus an I2S audio signal. The 32-bit mode handles 29-bit data and control signals plus an I2S audio signal. Any combination and sequence of color video data, video sync, and control signals make up the 21-bit or 29-bit parallel data on DOUT_. The I2S port supports the sampled audio data at a rate from 8kHz to 192kHz and the audio word length of anywhere between 4 to 32 bits. The embedded control channel forms a UART link between the serializer and deserializer. The UART link can be set to half-duplex mode or full-duplex
t
DVA
t
DVB
t
DVBtDVA
t
R
t
F
mode depending on the application. The GMSL supports UART rates from 100kbps to 1Mbps. Using this control link, a host ECU or FC communicates with the serializer and deserializer, as well as the peripherals in the remote side, such as backlight control, grayscale gamma correction, camera module, and touch screen. All serial communication (forward and reverse) uses differential signaling. The peripheral programming uses I2C format or the default GMSL UART format. A separate bypass mode enables communication using a full-duplex, user­defined UART format. The control link between the serializer/deserializer allows FC connectivity to either device or peripherals to support video-display or image­sensing applications.
The AC-coupled serial link uses 8b/10b coding. The deserializer features a programmable channel equalizer to extend the link length and enhance the link reliability. A programmable spread-spectrum feature reduces EMI on the parallel data outputs. The differential serial link input pins comply with the ISO 10605 and IEC 61000-4-2 ESD-protection standards. This device uses a 3.3V core supply and a 1.8V to 3.3V I/O supply.
Register Mapping
The FC configures various operating conditions of the GMSL through registers in the serializer/deserializer. The default device addresses stored in the R0 and R1 registers of the serializer/deserializer are 0x80. Write to the R0/R1 registers to change the device address of the serializer or deserializer.
14 _____________________________________________________________________________________
Gigabit Multimedia Deserializer with Spread
Spectrum and Full-Duplex Control Channel
Table 1. Power-Up Default Register Map (see Table 12)
MAX9270
REGISTER
ADDRESS
(hex)
0x00 0x80
0x01 0x90
0x02 0x1F or 0x5F
0x03 0x00
0x04 0x03 or 0x83
POWER-UP DEFAULT
(hex)
POWER-UP DEFAULT SETTINGS
(MSB FIRST)
SERID =1000000, serializer device identifier is 1000 000 RESERVED = 0
DESID =1001000, deserializer device identifier is 1001 000 RESERVED = 0
SS = 00 (SSEN = low), SS = 01 (SSEN = high), spread-spectrum settings depend on SSEN pin state at power-up RESERVED = 0 AUDIOEN = 1, I2S channel enabled PRNG = 11, automatically detect the pixel clock range SRNG = 11, automatically detect serial-data rate
AUTOFM = 00, calibrate spread-modulation rate only once after locking RESERVED = 0 SDIV = 00000, autocalibrate sawtooth divider
LOCKED = 0, LOCK output = low (read only) OUTENB = 0, outputs enabled PRBSEN = 0, PRBS test disabled SLEEP = 0 or 1, SLEEP setting default depends on CDS and MS pin state at pow­er-up (see the Link Startup Procedure section) INTTYPE = 00, base mode uses I2C REVCCEN = 1, reverse control channel active (sending) FWDCCEN = 1, forward control channel active (receiving)
RESERVED = 0 HPFTUNE = 01, 3.75MHz equalizer highpass cutoff frequency
0x05 0x28 or 0x29
0x06 0x0F
0x07 0x54 RESERVED = 01010100 0x08 0x30 RESERVED = 00110000
0x09 0xC8 RESERVED = 11001000 0x0A 0x12 RESERVED = 00010010 0x0B 0x20 RESERVED = 00100000
______________________________________________________________________________________ 15
PDHF = 0, high-frequency boosting disabled EQTUNE = 1000 (EQS = high, 10.7dB), EQTUNE = 1001 (EQS = low, 5.2dB), EQTUNE default setting depends on EQS pin state at power-up
DISSTAG = 0, staggered outputs enabled AUTORST = 0, error registers/output auto reset disabled DISINT = 0, INT transmission enabled INT = 0, INT output = low (read only) GPIO1OUT = 1, GPIO1 output set to high GPIO1 = 1, GPIO1 input = high (read only) GPIO0OUT = 1, GPIO0 output set to high GPIO0 = 1, GPIO0 input = high (read only)
Gigabit Multimedia Deserializer with Spread Spectrum and Full-Duplex Control Channel
Table 1. Power-Up Default Register Map (see Table 12) (continued)
REGISTER
ADDRESS
(hex)
0x0C 0x00 ERRTHR = 00000000, error threshold set to zero for decoding errors
0x0D
MAX9270
0x0E
0x12 0x00
0x1E
0x1F
POWER-UP DEFAULT
(hex)
0x00
(read only)
0x00
(read only)
0x02
(read only)
0x0X
(read only)
POWER-UP DEFAULT SETTINGS
(MSB FIRST)
DECERR = 00000000, zero decoding errors detected
PRBSERR = 00000000, zero PRBS errors detected
MCLKSRC = 0, MCLK is derived from PCLKOUT (see Table 4) MCLKDIV = 0000000, MCLK output is disabled
ID = 00000010, device ID is 0x02
RESERVED = 0000 REVISION = XXXX
Table 2. Bus-Width Selection Using BWS
BWS INPUT STATE BUS WIDTH PARALLEL BUS SIGNALS USED
Low 24 DOUT[0:20], WS, SCK, SD
High 32 DOUT[0:28], WS, SCK, SD
Parallel Outputs
The parallel bus uses two selectable bus widths, 24 bits and 32 bits. BWS selects the bus width according to Table 2. In 24-bit mode, DIN21–DIN28 are not used and are internally pulled down. For both modes, SD, SCK, and WS pins are dedicated for I2S audio data. The assign­ments of the first 21 or 29 signals are interchangeable and appear in the same order at both sides of the serial link. In image-sensing applications, disabling the I2S audio channel (through the internal registers) allows the serialization of three 10-bit camera data streams through DIN[0:28] plus SD inputs. The parallel bus accepts data clock rates from 8.33MHz to 104MHz for the 24-bit mode and 6.25MHz to 78MHz for the 32-bit mode.
Serial Link Signaling and Data Format
The serializer’s high-speed data serial output uses CML signaling with programmable preemphasis and AC-coupling. The deserializer’s high-speed receiver uses AC-coupling and programmable channel equaliza­tion. Together, the GMSL operates at up to 3.125Gbps over STP cable lengths up to 15m.
The serializer scrambles and encodes the parallel input bits, and sends the 8b/10b coded signal through the serial link. The deserializer recovers the embedded seri­al clock and then samples, decodes, and descrambles
the data onto the parallel output bus. Figures 11 and 12 show the serial-data packet format prior to scrambling and 8b/10b coding. For the 24-bit or 32-bit mode, the first 21 or 29 serial bits map to DOUT[20:0] or DOUT[28:0], respectively. The audio channel bit (ACB) contains an encoded audio signal derived from the three I2S inputs (SD, SCK, and WS). The forward control channel (FCC) bit carries the forward control data. The last bit (PCB) is the parity bit of the previous 23 or 31 bits.
The GMSL uses the reverse control channel to send I2C/UART in the opposite direction of the video stream from the deserializer to the serializer. The reverse control channel and forward video data coexist on the same twisted pair forming a bidirectional link. The reverse control channel operates independently from the forward control channel. The reverse control channel is available 500Fs after power-up. The serializer temporarily disables the reverse control channel for 350Fs after starting/stop­ping the forward serial link.
Parallel Data-Rate Selection
The deserializer uses the DRS input to set the parallel data rate. Set DRS high to use a low-speed parallel data rate in the range of 6.25MHz to 12.5MHz (32-bit mode) or 8.33MHz to 16.66MHz (24-bit mode). Set DRS low
Reverse Control Channel
16 _____________________________________________________________________________________
Gigabit Multimedia Deserializer with Spread
Spectrum and Full-Duplex Control Channel
24 BITS
32 BITS
MAX9270
DOUT0 DOUT1
18-BIT
RGB
DATA
NOTE: LOCATIONS OF THE RGB DATA AND CONTROL SIGNALS ARE INTERCHANGEABLE ACCORDINGLY ON BOTH SIDES OF THE LINK.
DOUT17 DOUT18 DOUT19 DOUT20 ACB FCC PCB
HSYNC, VSYNC,
DE
AUDIO
CHANNEL BIT
CHANNEL BIT
FORWARD CONTROL-
PACKET
PARITY
CHECK BIT
DOUT0 DOUT1 DOUT23 DOUT24 DOUT25 DOUT26 DOUT27 DOUT28 ACB FCC PCB
24-BIT
RGB DATA
NOTE: LOCATIONS OF THE RGB DATA AND CONTROL SIGNALS ARE INTERCHANGEABLE ACCORDINGLY ON BOTH SIDES OF THE LINK.
HSYNC, VSYNC,
DE
ADDITIONAL
VIDEO DATA/
CONTROL
BITS
Figure 11. 24-Bit Mode Serial Link Data Format Figure 12. 32-Bit Mode Serial Link Data Format
Table 3. Maximum Audio Sampling Rates for Various PCLK_ Frequencies
WORD LENGTH
(Bits)
8 16 18 20 24 32
PCLK_ FREQUENCY
(DRS = LOW)
(MHz)
12.5 15 16.6 > 20 6.25 7.5 8.33 > 10
> 192 > 192 > 192 > 192 > 192 > 192 > 192 > 192 > 192 > 192 > 192 > 192 > 192 > 192 > 192 > 192
185.5 > 192 > 192 > 192 185.5 > 192 > 192 > 192
174.6 > 192 > 192 > 192 174.6 > 192 > 192 > 192
152.2 182.7 > 192 > 192 152.2 182.7 > 192 > 192
123.7 148.4 164.3 > 192 123.7 148.4 164.3 > 192
PCLK_ FREQUENCY
(DRS = HIGH)
(MHz)
AUDIO
CHANNEL
BIT
FORWARD CONTROL­CHANNEL
BIT
PACKET
PARITY
CHECK BIT
for normal operation with parallel data rates higher than
12.5MHz (32-bit mode) or 16.66MHz (24-bit mode).
Audio Channel
The I2S audio channel supports audio sampling rates from 8kHz to 192kHz and audio word lengths from 4 bits to 32 bits. The audio bit clock (SCK) does not need to be synchronized with PCLKIN. The serializer automatically encodes audio data into a single bit stream synchronous with PCLKIN. The deserializer decodes the audio stream and stores audio words in a FIFO. Audio rate detection uses an internal oscillator to continuously determine the audio data rate and output the audio in I2S format. The audio channel is enabled by default. When the audio channel is disabled, the SD pins on both sides are treated as a regular parallel data pin.
PCLK_ frequencies can limit the maximum supported audio sampling rate. Table 3 lists the maximum audio sampling rate for various PCLK_ frequencies. Spread-
______________________________________________________________________________________ 17
spectrum settings do not affect the I2S data rate or WS clock frequency.
Additional MCLK Output
for Audio Applications
Some audio DACs such as the MAX9850 do not require a synchronous main clock (MCLK), while other DACs require MCLK to be a specific multiple of WS. If an audio DAC chip needs the MCLK to be a multiple of WS, syn­chronize the I2S audio data with PCLK_ of the GMSL, which is typical for most applications. Select the PCLK_ to be the multiple of WS, or use a clock synthesis chip, such as the MAX9491, to regenerate the required MCLK from PCLK_ or SCK.
For audio applications that cannot directly use the PCLKOUT output, the deserializer provides a divided MCLK output on DOUT28 at the expense of one less par­allel line in 32-bit mode (24-bit mode is not affected). By default, DOUT28 operates as a parallel data output and
Gigabit Multimedia Deserializer with Spread Spectrum and Full-Duplex Control Channel
Table 4. f
MCLKSRC SETTING
(REGISTER 0x12, D7)
SRC
0
Settings
DATA-RATE SETTING BIT-WIDTH SETTING
High speed
Low speed
MAX9270
1
MCLK is turned off. Set MCLKDIV (deserializer register 0x12, D[6:0]) to a non-zero value to enable the MCLK output. Set MCLKDIV to 0x00 to disable MCLK and set DOUT28 as a parallel data output.
The output MCLK frequency is:
f
f
MCLK
where f MCLKDIV is the divider ratio from 1 to 127.
Choose MCLKDIV values so that f than 60MHz. MCLK frequencies derived from PCLK_ (MCLKSRC = 0) are not affected by spread-spectrum settings in the deserializer. Enabling spread spectrum in the serializer, however, introduces spread spectrum into MCLK. Spread-spectrum settings of either device do not affect MCLK frequencies derived from the inter­nal oscillator. The internal oscillator frequency ranges from 100MHz to 150MHz over all process corners and operating conditions.
is the MCLK source frequency (Table 4) and
SRC
SRC
=
MCLKDIV
MCLK
Control-Channel and Register Programming
The FC uses the control link to send and receive control data over the STP link simultaneously with the high-speed data. Configuring the CDS pin allows the FC to control the link from either the serializer or the deserializer side to support video-display or image-sensing applications.
The control link between the FC and the serializer/ deserializer runs in base mode or bypass mode accord­ing to the mode selection (MS) input of the device con­nected to the FC. Base mode is a half-duplex control link and the bypass mode is a full-duplex control link. In base mode, the FC is the host and accesses the registers of both the serializer/deserializer by using the GMSL UART protocol. The FC can also program the peripherals on the remote side by sending the UART packets converted to
is not greater
MCLK SOURCE
FREQUENCY (f
24-bit mode 3 x f 32-bit mode 4 x f 24-bit mode 6 x f 32-bit mode 8 x f
I2C by the device on the remote side of the link (deserial­izer for LCD or serializer for image-sensing applications). The FC communicates with a UART peripheral in base mode (through INTTYPE register settings) using the half-duplex default GMSL UART protocol. The device addresses of the serializer and deserializer in the base mode are programmable. The default values are 0x80 and 0x90, respectively.
In base mode, when the peripheral interface uses I2C (default), the serializer/deserializer only convert packets that have device addresses different from themselves to I2C. The converted I2C bit rate is the same as the original UART bit rate.
In bypass mode, the FC bypasses the GMSL and communicates with the peripherals directly using its own defined UART protocol. The FC cannot access the GMSL registers in this mode. Peripherals accessed through the forward control channel using the UART interface need to handle at least one PCLK_ period of jitter due to the asynchronous sampling of the UART signal by PCLK_.
The serializer embeds control signals going to the dese­rializer in the high-speed forward link. Do not send a low value longer than 100Fs in either base or bypass mode. The deserializer uses a proprietary differential line coding to send signals back towards the serializer. The speed of the control link ranges from 100kbps to 1Mbps in both directions. The serializer/deserializer automati­cally detects the control-channel bit rate in base mode. Packet bit rates can vary up to 3.5x from the previous bit rate (see the Changing the Data Frequency section). Figure 13 shows the UART protocol for writing and read­ing in base mode between the FC and the serializer/ deserializer.
Figure 14 shows the UART data format. Even parity is used. Figures 15 and 16 detail the formats of the SYNC byte (0x79) and ACK byte (0xC3). The FC and the connected slave chip generate the SYNC byte and ACK
PCLKOUT
PCLKOUT
PCLKOUT
PCLKOUT
Internal oscillator
(120MHz typ)
SRC
)
18 _____________________________________________________________________________________
Gigabit Multimedia Deserializer with Spread
Spectrum and Full-Duplex Control Channel
WRITE DATA FORMAT
SYNC DEV ADDR + R/W REG ADDR NUMBER OF BYTES BYTE 1 BYTE N
MAX9270
SYNC DEV ADDR + R/W REG ADDR NUMBER OF BYTES
Figure 13. UART Protocol for Base Mode
START D0 D1 D2 D3 D4 D5 D6 D7 PARITY STOP
FRAME 1
MASTER WRITES TO SLAVE
READ DATA FRMAT
MASTER WRITES TO SLAVE
MASTER READS FROM SLAVE
1 UART FRAME
FRAME 2 FRAME 3
STOP START STOP START
ACK
MASTER READS FROM SLAVE
BYTE NBYTE 1ACK
Figure 14. UART Data Format for Base Mode
D1 D2 D3 D4 D5 D6 D7
STARTD01 0 0 1 1 1 1 0
Figure 15. SYNC Byte (0x79) Figure 16. ACK Byte (0xC3)
PARITY STOP
byte, respectively. Certain events such as device wake­up and interrupt generate signals on the control path and should be ignored by the FC. All data written to the internal registers do not take affect until after the acknowledge byte is sent. This allows the FC to verify that write commands are processed without error, even if the result of the write command directly affects the serial link. The slave uses the SYNC byte to synchronize with the host UART data rate automatically. If the INT or MS inputs of the device toggle while there is control-channel communication, the control-channel communication can be corrupted. In the event of a missed acknowledge, the
______________________________________________________________________________________ 19
STARTD01 1 0 0 0 0 1 1
FC should assume there was an error in the packet when the slave device receives it, or that an error occurred during the response from the slave device. In base mode, the FC must keep the UART Tx/Rx lines high for 16 bit times before starting to send a new packet.
As shown in Figure 17, the remote-side device converts the packets going to or coming from the peripherals from the UART format to the I2C format and vice versa. The remote device removes the byte number count and adds or receives the ACK between the data bytes of I2C. The I2C’s data rate is the same as the UART data rate.
D1 D2 D3 D4 D5 D6 D7
PARITY STOP
Gigabit Multimedia Deserializer with Spread Spectrum and Full-Duplex Control Channel
2
C CONVERSION OF WRITE PACKET (I2CMETHOD = 0)
UART-TO-I
FC
SERIALIZER/DESERIALIZER
11
SYNC FRAME REGISTER ADDRESS NUMBER OF BYTESDEVICE ID + WR DATA 0
11 11 11 11
11 11
DATA N
ACK FRAME
SERIALIZER/DESERIALIZER PERIPHERAL
MAX9270
2
C CONVERSION OF READ PACKET (I2CMETHOD = 0)
UART-TO-I FC
SERIALIZER/DESERIALIZER
SERIALIZER/DESERIALIZER
11
SYNC FRAME REGISTER ADDRESS NUMBER OF BYTESDEVICE ID + RD
11 11 11 11
PERIPHERAL
1 11
7
DEV ID A
S
1 17W1
DEV ID AS
: MASTER TO SLAVE
W1REG ADDR8A
REG ADDR8A
: SLAVE TO MASTER
1 1 8 1
ACK FRAME
1 17R1
1
DEV ID AS
S: START P: STOP A: ACKNOWLEDGE
DATA 08A
Figure 17. Format Conversion between UART and I2C with Register Address (I2CMETHOD = 0)
2
UART-TO-I
SYNC FRAME DEVICE ID + WR REGISTER ADDRESS NUMBER OF BYTES DATA 0 DATA N ACK FRAME
SERIALIZER/DESERIALIZER
C CONVERSION OF WRITE PACKET (I2CMETHOD = 1)
SERIALIZER/DESERIALIZERFC
11 11 11 11 11 11 11
PERIPHERAL
8
DATA 0 A DATA N A P
11
DATA 0
1
8 81111 7 1 1
1
DATA N P18A
DATA NADATA 0W ADEV IDS A P
11
DATA N
2
UART-TO-I
C CONVERSION OF READ PACKET (I2CMETHOD = 1)
FC
SYNC FRAME
SERIALIZER/DESERIALIZER
SERIALIZER/DESERIALIZER
1111 11 11 11 11 11
DEVICE ID + RD REGISTER ADDRESS NUMBER OF BYTES
PERIPHERAL
: MASTER TO SLAVE
: SLAVE TO MASTER S: START P: STOP A: ACKNOWLEDGE
ACK FRAME DATA 0 DATA N
1 1 1 8 S
DEV ID R A A A PDATA 0 DATA N
1 1 17
8
Figure 18. Format Conversion between UART and I2C in Command-Byte-Only Mode (I2CMETHOD = 1)
20 _____________________________________________________________________________________
Gigabit Multimedia Deserializer with Spread
Spectrum and Full-Duplex Control Channel
Interfacing Command-Byte-Only
I2C Devices
The GMSL UART-to-I2C conversion interfaces with devices that do not require register addresses, such as the MAX7324 GPIO expander. Change the communica­tion method of the I2C master using the I2CMETHOD bit. I2CMETHOD = 1 sets command-byte-only mode, while I2CMETHOD = 0 sets normal mode where the first byte in the data stream is the register address. In this mode, the I2C master ignores the register address byte and directly reads/writes the subsequent data bytes (Figure 18).
Interrupt Control
The INT of the serializer is the interrupt output and the INT of the deserializer is the interrupt input. The interrupt out­put on the serializer follows the transitions at the interrupt input of the deserializer. This interrupt function supports remote-side functions such as touch-screen peripherals,
Table 5. Cable Equalizer Boost Levels
BOOST SETTING
(0x05 D[3:0])
0000 2.1 0001 2.8 0010 3.4 0011 4.2
0100
0101 6.2 0110 7 0111 8.2 1000 9.4
1001
1010 11.7 1011 13
TYPICAL BOOST GAIN (dB)
5.2
Power-up default
(EQS = high)
10.7
Power-up default
(EQS = low)
remote power-up, or remote monitoring. Interrupts that occur during periods where the reverse control channel is disabled, such as link startup/shutdown, are automati­cally resent once the reverse control channel becomes available again. Bit D4 of register 0x06 in the deserializer also stores the interrupt input state. Writing to the SETINT register bit also sets the INT output of the serializer. In addition, the FC sets the INT output of the serializer by writing to the SETINT register bit. In normal operation, the state of the interrupt output changes when the interrupt input on the deserializer toggles.
Line Equalizer
The deserializer includes an adjustable line equalizer to further compensate cable attenuation at high frequen­cies. The cable equalizer has 11 selectable levels of compensation from 2.1dB to 13dB (Table 5). The EQS input selects the default equalization level at power-up. The state of EQS is latched upon power-up or when resuming from power-down mode. To select other equalization levels, set the corresponding register bits in the deserializer (0x05 D[3:0]). Use equalization in the deserializer, together with preemphasis in the serializer to create the most reliable link for a given cable.
Spread Spectrum
To reduce the EMI generated by the transitions on the serial link and parallel outputs, the deserializer supports spread spectrum. Turning on spread spectrum on the deserializer spreads the parallel video outputs. Do not enable spread spectrum for both the serializer and dese­rializer. The two selectable spread-spectrum rates at the parallel outputs are Q2% and Q4% (Table 6).
Set the SSEN input high to select 2% spread at power-up and SSEN input low to select no spread at power-up. The state of SSEN is latched upon power-up or when resum­ing from power-down mode.
Turning on spread spectrum does not affect the audio data stream. Changes in the serializer spread settings only affect MCLK output if it is derived from PCLK_ (MCLKSRC = 0).
MAX9270
Table 6. Parallel Output Spread
SS SPREAD (%)
00 No spread spectrum. Power-up default when SSEN = low. 01 10 No spread spectrum. 11
______________________________________________________________________________________ 21
Q2% spread spectrum. Power-up default when SSEN = high.
Q4% spread spectrum.
Gigabit Multimedia Deserializer with Spread Spectrum and Full-Duplex Control Channel
The device includes a sawtooth divider to control the spread-modulation rate. Autodetection or manual pro­gramming of the PCLK_ operation range guarantees a spread-spectrum modulation frequency within 20kHz to 40kHz. Additionally, manual configuration of the saw­tooth divider (SDIV, 0x03 D[5:0]) allows the user to set a specific modulation frequency for a specific PCLK_ rate. Always keep the modulation frequency between 20kHz
MAX9270
to 40kHz to ensure proper operation.
Manual Programming of the
Spread-Spectrum Divider
The modulation rate relates to the PCLK_ frequency as follows:
f
f 1 DRS
= +
( )
M
where:
fM = Modulation frequency.
DRS = DRS pin input value (0 or 1).
f
= Parallel clock frequency (12.5MHz to 104MHz).
PCLK_
MOD = Modulation coefficient given in Table 7.
SDIV = 5-bit SDIV setting, manually programmed by the FC.
To program the SDIV setting, first look up the modulation coefficient according to the part number and desired bit-width and spread-spectrum settings. Solve the above equation for SDIV using the desired parallel clock and modulation frequencies. If the calculated SDIV value is larger than the maximum allowed SDIV value in Table 7, set SDIV to the maximum value.
PCLK_
MOD SDIV
×
Sleep Mode
The deserializer includes a low-power sleep mode to reduce power consumption when it is not attached to the FC LCD applications. Set the SLEEP bit to 1 to initi­ate sleep mode. The deserializer sleeps after serial link inactivity or 8ms (whichever arrives first) after setting its SLEEP = 1. See the Link Startup Procedure section for details on waking up the device for different FC and starting conditions.
The FC side device cannot enter into sleep mode, and its SLEEP bit remains at 0. Use the PWDN input pin to bring the FC side device into a low-power state.
Configuration Link Mode
The GMSL includes a low-speed configuration link to allow control-data connection between the two devices in the absence of a valid parallel clock input. In either display or camera applications, the configuration link can be used to program equalizer/preemphasis or other registers before establishing the video link. An internal oscillator provides PCLK_ for establishing the serial configuration link between the serializer and deserializer. The parallel output clock and data lines are disabled in the deserializer. The LOCK output remains low even after a successful configuration link lock. Set CLINKEN = 1 on the serializer to turn on the configuration link. The configuration link remains active as long as the video link has not been enabled. The video link overrides the configuration link and attempts to lock when SEREN = 1.
Link Startup Procedure
Table 8 lists four startup cases for video-display applica­tions. Table 9 lists two startup cases for image-sensing applications. In either display or image-sensing applica­tions, the control link is always available after the high­speed data link or the configuration link is established and the GMSL registers or the peripherals are ready for programming.
Video-Display Applications
For the video-display application, with a remote display unit, connect the FC to the serializer and set CDS = low for both the serializer and deserializer. Table 8 sum­marizes the four startup cases based on the settings of AUTOS and MS.
Case 1: Autostart Mode
After power-up or when PWDN transitions from low to high for both the serializer and deserializer, the serial link establishes if a stable PCLK_ is present. The serializer locks to PCLK_ and sends the serial data to the deserial­izer. The deserializer then detects activity on the serial link and locks to the input serial data.
Table 7. Modulation Coefficients and Maximum SDIV Settings
SPREAD-SPECTRUM SETTING (%)
4 208 15 2 208 30
22 _____________________________________________________________________________________
MODULATION COEFFICIENT
(decimal)
SDIV UPPER LIMIT (decimal)
Gigabit Multimedia Deserializer with Spread
Spectrum and Full-Duplex Control Channel
Table 8. Startup Selection for Video-Display Applications (CDS = Low)
MAX9270
CASE
1 Low Serialization enabled Low
2 High
3 High
4 Low Serialization enabled High
AUTOS
(SERIALIZER)
SERIALIZER
POWER-UP STATEMS(DESERIALIZER)
Serialization
disabled
Serialization
disabled
Case 2: Standby Start Mode
After power-up, or when PWDN transitions from low to high for both the serializer and deserializer, the deserial­izer starts up in sleep mode, and the serializer stays in standby mode (does not send serial data). Use the FC and program the serializer to set SEREN = 1 to establish a video link or CLINKEN = 1 to establish the configura­tion link. After locking to a stable PCLK_ (for SEREN = 1) or the internal oscillator (for CLINKEN = 1), the serializer sends a wake-up signal to the deserializer. The deserial­izer exits sleep mode after locking to the serial data and sets SLEEP = 0. If after 8ms the deserializer does not lock to the input serial data, the deserializer goes back to sleep, and the internal sleep bit remains uncleared (SLEEP = 1).
Case 3: Remote Side Autostart Mode
After power-up, or when PWDN transitions from low to high, the remote device (deserializer) starts up and tries to lock to an incoming serial signal with sufficient power. The host side (serializer) is in standby mode and does not try to establish a link. Use the FC and program the
DESERIALIZER
High
Low
POWER-UP
STATE
Normal
(SLEEP = 0)
Sleep mode (SLEEP = 1)
Normal
(SLEEP = 0)
Sleep mode (SLEEP = 1)
LINK STARTUP MODE
Both devices power up with the serial link active (autostart).
Serial link is disabled and the deserializer powers up in sleep mode. Set SEREN = 1 or CLINKEN = 1 in the serializer to start the serial link and wake up the deserializer.
Both devices power up in nor­mal mode with the serial link disabled. Set SEREN = 1 or CLINKEN = 1 in the serializer to start the serial link.
The deserializer starts in sleep mode. Link autostarts upon the serializer power-up. Use this case when the deserializer pow­ers up before the serializer.
serializer to set SEREN = 1 (and apply a stable PCLK_) to establish a video link, or CLINKEN = 1 to establish the configuration link. In this case, the deserializer ignores the short wake-up signal sent from the serializer.
Case 4: Remote Side in Sleep Mode
After power-up or when PWDN transitions from low to high, the remote device (deserializer) starts up in sleep mode. The high-speed link establishes automatically after the serializer powers up with a stable PCLK_ and sends a wake-up signal to the deserializer. Use this mode in applications where the deserializer powers up before the serializer.
Image-Sensing Applications
For image-sensing applications, with remote camera unit(s), connect the FC to the deserializer and set CDS = high for both the serializer and deserializer. The deserial­izer powers up normally (SLEEP = 0) and continuously tries to lock to a valid serial input. Table 9 summarizes the two startup cases, based on the state of the serializer AUTOS pin.
______________________________________________________________________________________ 23
Gigabit Multimedia Deserializer with Spread Spectrum and Full-Duplex Control Channel
Table 9. Startup Selection for Image-Sensing Applications (CDS = High)
CASE
AUTOS
(SERIALIZER)
1 Low Serialization enabled
MAX9270
2 High
SERIALIZER
POWER-UP STATE
Sleep mode (SLEEP = 1)
SLEEP = 1, VIDEO LINK OR CONFIG
LINK NOT LOCKED AFTER 8ms
DESERIALIZER
POWER-UP STATE
Normal
(SLEEP = 0)
Normal
(SLEEP = 0)
LINK STARTUP MODE
Autostart.
Serializer is in sleep mode. Wake up the serializer through the control channel (FC attached to the deserializer).
MS PIN
SETTING
LOW
HIGH
SEND INT TO
SERIALIZER
SLEEP BIT
POWER-UP VALUE
0 1
SERIAL LINK ACTIVITY STOPS OR 8ms ELAPSES AFTER
INT CHANGES FROM
LOW TO HIGH OR
HIGH TO LOW
SLEEP
FC SETS SLEEP = 1
ALL STATES
WAKE-UP
SIGNAL
PWDN = LOW OR
POWER-OFF
POWER-ON
Figure 19. State Diagram, CDS = Low (LCD Application)
Case 1: Autostart Mode
After power-up, or when PWDN transitions from low to high, the serializer locks to a stable PCLKIN and sends the high-speed data to the deserializer. The deserializer locks to the serial data and outputs the parallel video data and PCLKOUT.
Case 2: Sleep Mode
After power-up, or when PWDN transitions from low to high, the serializer starts up in sleep mode. To wake up the serializer, use the FC to send a regular UART frame
IDLE
PWDN = HIGH, POWER-ON
POWER-DOWN
OR
POWER-OFF
SIGNAL
DETECTED
SERIAL PORT
VIDEO LINK
LOCKED
VIDEO LINK
OPERATING
0 SLEEP
LOCKING
CONFIG LINK
UNLOCKED
CONFIG LINK
LOCKED
PRBSEN = 0
PRBSEN = 1
VIDEO LINK UNLOCKED
CONFIG LINK
OPERATING
PROGRAM
REGISTERS
0 SLEEP
VIDEO LINK PRBS TEST
containing at least three rising edges (e.g., 0x66), at a bit rate no greater than 1Mbps. The low-power wake-up receiver of the serializer detects the wake-up frame over the reverse control channel and powers up. Reset the sleep bit (SLEEP = 0) of the serializer using a regular control-channel write packet to power up the device fully. Send the sleep bit write packet at least 500Fs after the wake-up frame. The serializer goes back to sleep mode if its sleep bit is not cleared within 8ms (typ) after detect­ing a wake-up frame.
24 _____________________________________________________________________________________
Gigabit Multimedia Deserializer with Spread
Spectrum and Full-Duplex Control Channel
MAX9270
POWER-ON
IDLE
(REVERSE CHANNEL
ACTIVE)
NO SIGNAL
DETECTED
ALL STATES
Figure 20. State Diagram, CDS = High (Camera Application)
PWDN = LOW OR
POWER-OFF
SIGNAL
DETECTED
PWDN = HIGH,
POWER ON
POWER-DOWN
OR
POWER-OFF
SERIAL PORT
VIDEO LINK
LOCKED
Applications Information
Error Checking
The deserializer checks the serial link for errors and stores the number of detected decoding errors in the 8-bit register (DECERR, 0x0D). If a large number of decoding errors are detected within a short duration, the deserializer loses lock and stops the error counter. The deserializer then attempts to relock to the serial data. DECERR resets upon successful video link lock, suc­cessful readout of DECERR (through UART), or when­ever auto-error reset is enabled. The deserializer does not check for decoding errors during the internal PRBS test and DECERR is reset to 0x00.
ERR Output
The deserializer has an open-drain ERR output. This output asserts low whenever the number of decoding errors exceed the error threshold (ERRTHR, 0x0C) dur­ing normal operation, or when at least one PRBS error is detected during PRBS test. ERR reasserts high when­ever DECERR (0x0D) resets, due to DECERR readout, video link lock, or autoerror reset.
Autoerror Reset
The default method to reset errors is to read the respec­tive error registers in the deserializer (0x0D, 0x0E). Auto­error reset clears the decoding-error counter (DECERR) and the ERR output ~1Fs after ERR goes low. Autoerror reset is disabled on power-up. Enable autoerror reset through AUTORST (0x06 D6). Autoerror reset does not run when the device is in PRBS test mode.
LOCKING
CONFIG LINK
UNLOCKED
CONFIG LINK
LOCKED
VIDEO LINK UNLOCKED
VIDEO LINK OPERATING
CONFIG
LINK OPERATING
PROGRAM
REGISTERS
PRBSEN = 0
PRBSEN = 1
VIDEO LINK PRBS TEST
Self PRBS Test
The GMSL link includes a PRBS pattern generator and bit-error verification function. Set PRBSEN = 1 (0x04 D5) first in the serializer and then the deserializer to start the PRBS test. Set PRBSEN = 0 (0x04 D5) first in the dese­rializer and then the serializer to exit the PRBS self test. The deserializer uses an 8-bit register (0x0E) to count the number of detected errors. The control link also controls the start and stop of the error counting. During PRBS mode, the device does not count decoding errors and the ERR output reflects PRBS errors only. Autoerror reset does not run when the device is in PRBS mode.
Microcontrollers on Both Sides
of the GMSL Link (Dual µC Control)
Usually the FC is either on the serializer side for video­display applications, or on the deserializer side for image-sensing applications. For the former case, both the CDS pins are set to low, and for the latter case, the CDS pins are set to high. However, if the CDS pin of the serializer is low and the CDS pin of the deserializer is high, then the serializer/deserializer can both connect to FCs simultaneously. In such a case, the FCs on either side can communicate with the GMSL UART protocol.
Contentions of the control link may happen if the FCs on both sides are using the link at the same time. The GMSL does not provide the solution for contention avoidance. The serializer/deserealizer do not send an acknowledge frame when communication fails due to contention. Users can always implement a higher-layer protocol to
______________________________________________________________________________________ 25
Gigabit Multimedia Deserializer with Spread Spectrum and Full-Duplex Control Channel
avoid the contention. In addition, if UART communica­tion across the serial link is not required, the FCs can disable the forward and reverse control channel through the FWDCCEN and REVCCEN bits (0x04 D[1:0]) in the devices. UART communication across the serial link is stopped and contention between FCs no longer occurs. During the dual FC operation, if one of the CDS pins on either side changes state, the link resumes the corre-
MAX9270
sponding state described in the Link Startup Procedure section.
As an example of dual FC use in an image-sensing link, the serializer may be in sleep mode and waiting to be waked up by the deserializer. After wake-up, the serializer-side FC sets the serializer CDS pin low and assumes master control of the serializer registers.
Changing the Data Frequency
Both the video data rate (f rate (f cations with multiple clock speeds. Slow speed/perfor­mance modes allow significant power savings when a system’s full capabilities are not required. Enable the GMSL link after PCLK_ stabilizes. Stop PCLKIN for 5µs and restart the serial link or toggle SEREN after each change in the parallel clock frequency to recalibrate any automatic settings if a clean frequency change cannot be guaranteed. The reverse control channel remains unavailable for 350Fs after serial link start or stop. Limit on-the-fly changes in f a time to ensure that the device recognizes the UART sync pattern. For example, when lowering the UART frequency from 1Mbps to 100kbps, first send data at 333kbps and then at 100kbps to have reduction ratios of 3 and 3.333, respectively.
) can be changed on-the-fly to support appli-
UART
UART
) and the control data
PCLK_
to factors of less than 3.5 at
LOCK Output Loopback
Connect the LOCK output to the INT input of the device to loopback LOCK to the serializer. The interrupt output on the serializer follows the transitions at the LOCK out­put of the deserializer. Reverse-channel communication does not require an active forward link to operate and accurately tracks the LOCK status of the video link. LOCK asserts for video link only and not for the configu­ration link.
GPIOs
The device has two open-drain GPIOs available. GPIO1OUT and GPIO0OUT (0x06 D3, D1) set the output state of the GPIOs. The GPIO input buffers are always enabled. The input states are stored in GPIO1 and GPIO0 (0x06 D2, D0). Set GPIO1OUT/GPIO0OUT to 1 when using GPIO1/GPIO0 as an input.
Staggered Parallel Data Outputs
The device staggers the parallel data outputs to reduce EMI and noise. Staggering outputs also reduce the power-supply transient requirements. By default, the deserializer staggers outputs according to Table 10. Disable output staggering through the DISSTAG bit (0x06 D7)
Choosing I2C/UART Pullup Resistors
Both I2C/UART open-drain lines require pullup resistors to provide a logic-high level. There are tradeoffs between power dissipation and speed, and a compromise must be made in choosing pullup resistor values. Every device connected to the bus introduces some capacitance even when the device is not in operation. I2C specifies 300ns rise times to go from low to high (30% to 70%) for fast mode, which is defined for data rates up to 400kbps (see the I2C specifications in the Electrical Characteristics table for details). To meet the fast-mode rise-time requirement, choose the pullup resistors so that rise time tR = 0.85 x R are not recognized if the transition time becomes too slow. The device supports I2C/UART rates up to 1Mbps.
PULLUP
x C
< 300ns. The waveforms
BUS
Table 10. Staggered Output Delay
OUTPUT DELAY RELATIVE
OUTPUT
DISSTAG = 0 DISSTAG = 1
DOUT0–DOUT5,
DOUT21, DOUT22
DOUT6–DOUT10,
DOUT23, DOUT24
DOUT11–DOUT15,
DOUT25, DOUT26
DOUT16–DOUT20,
DOUT27, DOUT28
PCLKOUT 0.75 0
TO DOUT0 (ns)
0 0
0.5 0
1 0
1.5 0
26 _____________________________________________________________________________________
Gigabit Multimedia Deserializer with Spread
Spectrum and Full-Duplex Control Channel
AC-Coupling
AC-coupling isolates the receiver from DC voltages up to the voltage rating of the capacitor. Four capacitors—two at the serializer output and two at the deserializer input— are needed for proper link operation and to provide protection if either end of the cable is shorted to a high voltage. AC-coupling blocks low-frequency ground shifts and low-frequency common-mode noise.
Selection of AC-Coupling Capacitors
Voltage droop and the digital sum variation (DSV) of transmitted symbols cause signal transitions to start from different voltage levels. Because the transition time is finite, starting the signal transition from different volt­age levels causes timing jitter. The time constant for an AC-coupled link needs to be chosen to reduce droop and jitter to an acceptable level. The RC network for an AC-coupled link consists of the CML receiver termination resistor (RTR), the CML driver termination resistor (RTD), and the series AC-coupling capacitors (C). The RC time constant for four equal-value series capacitors is (C x (RTD + RTR))/4. RTD and RTR are required to match the transmission line impedance (usually 100I). This leaves the capacitor selection to change the system time con­stant. Use at least 0.2FF (100V) high-frequency surface­mount ceramic capacitors to pass the lower speed reverse-channel signal. Use capacitors with a case size less than 3.2mm x 1.6mm to have lower parasitic effects to the high-speed signal.
Power-Supply Circuits and Bypassing
The device uses an AVDD and DVDD of 3.0V to 3.6V. All single-ended inputs and outputs on the device derive power from an IOVDD of 1.7V to 3.6V. The input levels or output levels scale with IOVDD. Proper
voltage-supply bypassing is essential for high-frequency
MAX9270
circuit stability.
Cables and Connectors
Interconnect for CML typically has a differential imped­ance of 100I. Use cables and connectors that have matched differential impedance to minimize impedance discontinuities. Twisted-pair and shielded twisted-pair cables offer superior signal quality compared to ribbon cable and tend to generate less EMI due to magnetic­field canceling effects. Balanced cables pick up noise as common mode rejected by the CML receiver. Table 11 lists the suggested cables and connectors used in the GMSL link.
Board Layout
Separate the parallel signals and CML high-speed serial signals to prevent crosstalk. Use a four-layer PCB with separate layers for power, ground, CML, and digital signals. Layout PCB traces close to each other and have a 100I differential characteristic impedance. The trace dimensions depend on the type of trace used (microstrip or stripline). Note that two 50I PCB traces do not have 100I differential impedance when brought close together—the impedance goes down when the traces are brought closer.
Route the PCB traces for a CML channel (there are two conductors per CML channel) in parallel to maintain the differential characteristic impedance. Avoid vias. If vias must be used, use only one pair per CML channel and place the via for each line at the same point along the length of the PCB traces. This way, any reflections occur at the same time. Do not make vias into test points for ATE. Keep PCB traces that make up a differential pair equal in length to avoid skew within the differential pair.
Table 11. Suggested Connectors and Cables for GMSL
SUPPLIER CONNECTOR CABLE
JAE Electronics, Inc. MX38-FF A-BW-Lxxxxx Nissei Electric Co., Ltd. GT11L-2S F-2WME AWG28 Rosenberger Hochfrequenztechnik GmbH D4S10A-40ML5-Z Dacar 538
______________________________________________________________________________________ 27
Gigabit Multimedia Deserializer with Spread Spectrum and Full-Duplex Control Channel
ESD Protection
The ESD tolerance is rated for Human Body Model, IEC 61000-4-2, and ISO 10605. The ISO 10605 and IEC 61000-4-2 standards specify ESD tolerance for electronic systems. Serial inputs meet ISO 10605 ESD protection and IEC 61000-4-2 ESD protection. All other pins meet the Human Body Model ESD tolerances. The Human Body Model discharge components are CS =
MAX9270
100pF and RD = 1.5kI (Figure 21). The IEC 61000-4-2 discharge components are CS = 150pF and RD = 330I (Figure 22). The ISO 10605 discharge components are CS = 330pF and RD = 2kI (Figure 23).
R
D
1.5kI
DISCHARGE
RESISTANCE
STORAGE CAPACITOR
DEVICE UNDER
TEST
HIGH-
VOLTAGE
DC
SOURCE
1MI
CHARGE-CURRENT-
LIMIT RESISTOR
C
S
100pF
Figure 21. Human Body Model ESD Test Circuit
Table 12. Register Table
REGISTER
ADDRESS
0x00
0x01
0x02
BITS NAME VALUE FUNCTION
D[7:1] SERID XXXXXXX Serializer device address. 1000000
D0 0 Reserved. 0
D[7:1] DESID XXXXXXX Deserializer device address. 1001000
D0 0 Reserved. 0
D[7:6] SS
D5 0 Reserved. 0
D4 AUDIOEN
D[3:2] PRNG
D[1:0] SRNG
R
D
330I
HIGH-
VOLTAGE
DC
SOURCE
CHARGE-CURRENT-
LIMIT RESISTOR
150pF
DISCHARGE
RESISTANCE
C
S
STORAGE CAPACITOR
Figure 22. IEC 61000-4-2 Contact Discharge ESD Test Circuit
R
D
2kI
HIGH-
VOLTAGE
DC
SOURCE
CHARGE-CURRENT-
LIMIT RESISTOR
330pF
C
S
DISCHARGE
RESISTANCE
STORAGE CAPACITOR
Figure 23. ISO 10605 Contact Discharge ESD Test Circuit
00
01
No spread spectrum. Power-up default when SSEN = low.
Q2% spread spectrum. Power-up default when SSEN = high.
10 No spread spectrum. 11
Q4% spread spectrum.
0 Disable I2S channel.
1 Enable I2S channel. 00 12.5MHz to 25MHz pixel clock. 01 25MHz to 50MHz pixel clock. 10 50MHz to 104MHz pixel clock. 11 Automatically detect the pixel clock range. 00 0.5 to 1Gbps serial-data rate. 01 1 to 2Gbps serial-data rate. 10 2 to 3.125Gbps serial-data rate. 11 Automatically detect serial-data rate.
DEVICE UNDER
TEST
DEVICE UNDER
TEST
DEFAULT
VALUE
00, 01
1
11
11
28 _____________________________________________________________________________________
Gigabit Multimedia Deserializer with Spread
Spectrum and Full-Duplex Control Channel
Table 12. Register Table (continued)
REGISTER
ADDRESS
0x03
0x04
BITS NAME VALUE FUNCTION
D[7:6] AUTOFM
D5 0 Reserved. 0
D[4:0] SDIV
D7 LOCKED
D6 OUTENB
D5 PRBSEN
D4 SLEEP
D[3:2] INTTYPE
D1 REVCCEN
D0 FWDCCEN
00
01
10
11
00000 Autocalibrate sawtooth divider.
XXXXX
0 LOCK output is low.
1 LOCK output is high.
0 Enable outputs.
1 Disable outputs.
0 Disable PRBS test.
1 Enable PRBS test.
0
1
00 Base mode uses I2C peripheral interface. 01 Base mode uses UART peripheral interface.
10, 11 Base mode peripheral interface disabled.
0
1
0
1
Calibrate spread-modulation rate only once after locking.
Calibrate spread-modulation rate every 2ms after locking.
Calibrate spread-modulation rate every 16ms after locking.
Calibrate spread-modulation rate every 256ms after locking.
Manual SDIV setting (see the Manual
Programming of the Spread-Spectrum Divider section).
Normal mode default value depends on CDS and MS pin values at power-up).
Activate sleep mode default value depends on CDS and MS pin values at power-up).
Disable reverse control channel to serializer (sending).
Enable reverse control channel to serializer (sending).
Disable forward control channel from serializer (receiving).
Enable forward control channel from serializer (receiving).
MAX9270
DEFAULT
VALUE
00
00000
0
(read only)
0
0
0, 1
00
1
1
______________________________________________________________________________________ 29
Gigabit Multimedia Deserializer with Spread Spectrum and Full-Duplex Control Channel
Table 12. Register Table (continued)
REGISTER
ADDRESS
MAX9270
0x05
0x06
BITS NAME VALUE FUNCTION
0 I2C conversion sends the register address.
D7 I2CMETHOD
D[6:5] HPFTUNE
D4 PDHF
D[3:0] EQTUNE
D7 DISSTAG
D6 AUTORST
D5 DISINT
D4 INT
D3 GPIO1OUT
D2 GPIO1
D1 GPIO0OUT
D0 GPIO0
1
00 7.5MHz Equalizer highpass cutoff frequency. 01 3.75MHz cutoff frequency. 10 2.5MHz cutoff frequency. 11 1.87MHz cutoff frequency.
0 High-frequency boosting enabled.
1 High-frequency boosting disabled.
0000 2.1dB equalizer boost gain. 0001 2.8dB equalizer boost gain. 0010 3.4dB equalizer boost gain. 0011 4.2dB equalizer boost gain.
0100
0101 6.2dB equalizer boost gain. 0110 7dB equalizer boost gain. 0111 8.2dB equalizer boost gain. 1000 9.4dB equalizer boost gain.
1001
1010 11.7dB equalizer boost gain. 1011 13dB equalizer boost gain. 11XX Do not use.
0 Enable staggered outputs.
1 Disable staggered outputs.
0
1
0 Enable interrupt transmission to serializer.
1 Disable interrupt transmission to serializer.
0 INT input = low (read only).
1 INT input = high (read only).
0 Output low to GPIO1.
1 Output high to GPIO1.
0 GPIO1 is low.
1 GPIO1 is high.
0 Output low to GPIO0.
1 Output high to GPIO0.
0 GPIO0 is low.
1 GPIO0 is high.
Disable sending of I2C register address (command-byte-only mode).
5.2dB equalizer boost gain. Power-up default when EQS = high.
10.7dB equalizer boost gain. Power-up default when EQS = low.
Do not automatically reset error registers and outputs.
Automatically reset error registers and outputs.
DEFAULT
VALUE
0
01
0
0100, 1001
0
0
0
0
(read only)
1
1
(read only)
1
1
(read only)
30 _____________________________________________________________________________________
Gigabit Multimedia Deserializer with Spread
Spectrum and Full-Duplex Control Channel
Table 12. Register Table (continued)
REGISTER
ADDRESS
0x07 D[7:0] 01010100 Reserved. 01010100 0x08 D[7:0] 00110000 Reserved. 00110000
0x09 D[7:0] 11001000 Reserved. 11001000 0x0A D[7:0] 00010010 Reserved. 00010010 0x0B D[7:0] 00100000 Reserved. 00100000
0x0C D[7:0] ERRTHR XXXXXXXX
0x0D D[7:0] DECERR XXXXXXXX
0x0E D[7:0] PRBSERR XXXXXXXX PRBS error counter.
0x12
0x1E D[7:0] ID 00000010 Device identifier (MAX9270 = 0x02).
0x1F
BITS NAME VALUE FUNCTION
Error threshold for decoding errors. ERR = low when DECERR > ERRTHR.
Decoding error counter. This counter remains zero while the device is in PRBS test mode.
D7 MCLKSRC
D[6:0] MCLKDIV
0 MCLK derived from PCLKOUT (see Table 4). 1 MCLK derived from internal oscillator.
0000000 MCLK disabled.
XXXXXXX MCLK divider.
D[7:4] 0000 Reserved.
D[3:0] REVISION XXXX Device revision. (read only)
MAX9270
DEFAULT
VALUE
00000000
00000000
(read only)
00000000
(read only)
0
0000000
00000010
(read only)
0000
(read only)
Typical Application Circuit
1.8V
MAX9270
45.3kI45.3kI
4.99kI4.99kI
IN+
IN-
49.9kI49.9kI
PCLKOUT
DOUT(0:27)
CDS
RX/SDA
TX/SCL
LOCK
SCK
DOUT28/MCLK
INT
WS
SD
PCLK RGB HSYNC VSYNC
TO PERIPHERALS
SCL SDA
MAX9850
WS SCK SD MCLK
DISPLAY
VIDEO
UART
AUDIO
ECU
PCLK
RGB
HSYNC
VSYNC
TX RX
LFLT LFLT
INT
IMS
WS
SCK
SD
______________________________________________________________________________________ 31
GMSL SERIALIZER
PCLKIN DIN(0:27) DIN28 CDS AUTOS
RX/SDA TX/SCL
INT MS WS
SCK SD
LMN1
LMN0
OUT+
OUT-
Gigabit Multimedia Deserializer with Spread Spectrum and Full-Duplex Control Channel
Chip Information
PROCESS: CMOS
MAX9270
Package Information
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
56 TQFN-EP T5688+2
PACKAGE
CODE
DOCUMENT
NO.
21-0135 90-0046
LAND
PATTERN NO.
32 _____________________________________________________________________________________
Gigabit Multimedia Deserializer with Spread
-Spectrum and Full-Duplex Control Channel
Revision History
MAX9270
REVISION
NUMBER
0 12/10 Initial release — 1 1/11 Added Patent Pending to Features 1
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 33
©
2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
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