MAXIM MAX9268 User Manual

19-5211; Rev 2; 1/11

EVALUATION KIT

AVAILABLE

Gigabit Multimedia Serial Link Deserializer

with LVDS System Interface

General Description

The MAX9268 deserializer utilizes Maxim’s gigabit multimedia serial link (GMSL) technology. The MAX9268 deserializer features an LVDS system interface for reduced pin count and a smaller package, and pairs with any GMSL serializer to form a complete digital serial link for joint transmission of high-speed video, audio, and bidirectional control data.

The MAX9268 allows a maximum serial payload data rate of 2.5Gbps for a 15m shielded twisted-pair (STP) cable. The deserializer operates up to a maximum output clock rate of 104MHz (3-channel LVDS) or 78MHz (4-channel LVDS). This serial link supports display panels from QVGA (320 x 240) to WXGA (1280 x 800) and higher with 24-bit color.

The 3-channel mode outputs an LVDS clock, three lanes of LVDS data (21 bits), UART control signals, and one I2S audio channel consisting of three signals. The 4-channel mode outputs an LVDS clock, four lanes of LVDS data (28 bits), UART control signals, an I2S audio channel, and auxiliary control outputs. The three audio outputs form a standard I2S interface, supporting sample rates from 8kHz to 192kHz and audio word lengths of 4 to 32 bits. The embedded control channel forms a full-duplex, differential, 100kbps to 1Mbps UART link between the serializer and deserializer. An electronic control unit (ECU), or microcontroller (FC), can be located on the serializer side of the link (typical for video display), on the MAX9268 side of the link (typical for image sensing), or on both sides. In addition, the control channel enables ECU/FC control of peripherals on the remote side, such as backlight control, grayscale gamma correction, camera module, and touch screen. Base-mode communication with peripherals uses either I2C or the GMSL UART format. In addition, the MAX9268 features a bypass mode that enables full-duplex communication using custom UART formats.

The GMSL serializer driver preemphasis, along with the MAX9268 channel equalizer, extends the link length and enhances the link reliability. Spread spectrum is available to reduce EMI on the LVDS and control outputs of the MAX9268. The serial line inputs comply with ISO 10605 and IEC 61000-4-2 ESD protection standards.

The core supply for the MAX9268 is 3.3V. The I/O supply ranges from 1.8V to 3.3V. The MAX9268 is available in a 48-pin TQFP package (7mm x 7mm) with an exposed pad, and is specified over the -40NC to +105NC automotive temperature range.

Features

S Pairs with Any GMSL Serializer

S 2.5Gbps Payload-Rate AC-Coupled Serial Link

S Scrambled 8b/10b Line Coding

S Supports WXGA (1280 x 800) with 24-Bit Color

S 8.33MHz to 104MHz (3-Channel LVDS) or 6.25MHz

to 78MHz (4-Channel LVDS) Output Clock

S 4-Bit to 32-Bit Word Length, 8kHz to 192kHz I

2

S

Audio Channel Supports High-Definition Audio

S Embedded Half-/Full-Duplex Bidirectional Control

Channel (100kbps to 1Mbps)

S Two 3-Level Inputs Support 9 Device Addresses

S Interrupt Supports Touch-Screen Functions for

Display Panels

2

S I

C Master for Peripherals

S Equalizer for Serial Link Input

S Programmable Spread Spectrum on the LVDS and

Control Outputs for Reduced EMI

S Serial-Data Clock Recovery Eliminates an External

Clock

S Automatic Data-Rate Detection Allows On-the-Fly

Data-Rate Change

S Built-In PRBS Generator for BER Testing of the

Serial Link

S ISO 10605 and IEC 61000-4-2 ESD Protection

S -40NC to +105NC Operating Temperature Range

S 1.8V to 3.3V I/O and 3.3V Core Supplies

S Patent Pending

Ordering Information

PART TEMP RANGE PIN-PACKAGE

MAX9268GCM/V+ MAX9268GCM/V+T

/V denotes an automotive qualified product.

+Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad.

T = Tape and reel.

-40NC to +105NC

48 TQFP-EP* 48 TQFP-EP*

Applications

High-Resolution Automotive Navigation

Rear-Seat Infotainment

Megapixel Camera Systems

MAX9268

_______________________________________________________________ Maxim Integrated Products 1

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Gigabit Multimedia Serial Link Deserializer with LVDS System Interface

ABSOLUTE MAXIMUM RATINGS

AVDD to AGND ....................................................-0.5V to +3.9V

DVDD, IOVDD to AGND .......................................-0.5V to +3.9V

GND to AGND ......................................................-0.5V to +0.5V

IN+, IN- to AGND ................................................. -0.5V to +1.9V

TXOUT__, TXCLKOUT_ to AGND ........................-0.5V to +3.9V

All Other Pins to GND ......................... -0.5V to (V

TXOUT__, TXCLKOUT_ Short Circuit to Ground

or Supply ...............................................................Continuous

MAX9268

Continuous Power Dissipation (TA = +70°C)

48-Pin TQFP (derate 36.2mW/°C above +70°C) .... 2898.6mW

Human Body Model (RD = 1.5kΩ, CS = 100pF)

(IN+, IN-) to AGND ..........................................................±8kV

(TXOUT__, TXCLKOUT_) to AGND .................................±8kV

All Other Pins to GND ...................................................±3.5kV

IEC 61000-4-2 (RD = 330Ω, CS = 150pF) Contact Discharge

(IN+, IN-) to AGND ..................................................±10kV

IOVDD

+ 0.5V)

PACKAGE THERMAL CHARACTERISTICS (Note 1)

48 TQFP

Junction-to-Ambient Thermal Resistance (BJA) .......27.6°C/W

Junction-to-Case Thermal Resistance (BJC).................2°C/W

Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.

(TXOUT__, TXCLKOUT_) to AGND ............................±8kV

Air Discharge

(IN+, IN-) to AGND ........................................................±12kV

(TXOUT__, TXCLKOUT_) to AGND ...............................±20kV

ISO 10605 (RD = 2kΩ, CS = 330pF) Contact Discharge

(IN+, IN-) to AGND ..........................................................±8kV

(TXOUT__, TXCLKOUT_) to AGND .................................±8kV

Air Discharge

(IN+, IN-) to AGND ........................................................±15kV

(TXOUT__, TXCLKOUT_) to AGND ...............................±30kV

Operating Temperature Range ........................ -40°C to +105°C

Junction Temperature .....................................................+150°C

Storage Temperature Range ............................ -65°C to +150°C

Lead Temperature (soldering, 10s) ................................+300°C

Soldering Temperature (reflow) ......................................+260°C

DC ELECTRICAL CHARACTERISTICS

(V

= V

AVDD

Typical values are at V

SINGLE-ENDED INPUTS (BWS, INT, CDS, EQS, MS, PWDN, SSEN, DRS)

High-Level Input Voltage V

Low-Level Input Voltage V

Input Current I Input Clamp Voltage V

SINGLE-ENDED OUTPUTS (WS, SCK, SD/CNTL0, CNTL1, CNTL2/MCLK)

High-Level Output Voltage V

Low-Level Output Voltage V

Output Short-Circuit Current I

= 3.0V to 3.6V, V

DVDD

= V

AVDD

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

= 1.7V to 3.6V, RL = 100Ω Q1% (differential), TA = -40NC to +105NC, unless otherwise noted.

IOVDD

DVDD

= V

= 3.3V, TA = +25NC.)

IOVDD

IH1

IL1

IN1

CL

OH1

OL1

OS

VIN = 0V to V ICL = -18mA -1.5 V

I

OUT

I

OUT

V

OUT

DCS = 0

V

OUT

DCS = 1

= -2mA

= 2mA

= V

GND

= V

GND

IOVDD

DCS = 0

DCS = 1

DCS = 0 0.3 DCS = 1 0.2 V

,

IOVDD

V

IOVDD

V

IOVDD

V

IOVDD

0.65 x

V

IOVDD

0.35 x

V

IOVDD

-10 +10

V

IOVDD

- 0.3

V

IOVDD

- 0.2

= 3.0V to 3.6V 15 25 39 = 1.7V to 1.9V 3 7 13 = 3.0V to 3.6V 20 35 63 = 1.7V to 1.9V 5 10 21

V

FA

V

mA

2 ______________________________________________________________________________________

Gigabit Multimedia Serial Link Deserializer

with LVDS System Interface

DC ELECTRICAL CHARACTERISTICS (continued)

(V

= V

AVDD

Typical values are at V

I2C AND UART I/O, OPEN-DRAIN OUTPUTS (RX/SDA, TX/SCL, LOCK, ERR, GPIO_)

High-Level Input Voltage V

Low-Level Input Voltage V

Input Current I

Low-Level Output Voltage V

DIFFERENTIAL OUTPUT FOR REVERSE CONTROL CHANNEL (IN+, IN-)

Differential High Output Peak Voltage, (V

Differential Low Output Peak Voltage, (V

DIFFERENTIAL INPUTS (IN+, IN-)

Differential High Input Threshold (Peak) Voltage, (V

Differential Low Input Threshold (Peak) Voltage, (V

Input Common-Mode Voltage ((V

) + (V

IN+

Differential Input Resistance (Internal)

THREE-LEVEL LOGIC INPUTS (ADD0, ADD1)

High-Level Input Voltage V

Low-Level Input Voltage V

Mid-Level Input Current I

Input Current I

Input Clamp Voltage V

LVDS OUTPUTS (TXOUT__, TXCLKOUT_)

Differential Output Voltage V

Change in VOD Between Complementary Output States

Output Offset Voltage V

Change in VOS Between Complementary Output States

= 3.0V to 3.6V, V

DVDD

AVDD

= V

= 1.7V to 3.6V, RL = 100Ω Q1% (differential), TA = -40NC to +105NC, unless otherwise noted.

IOVDD

DVDD

= V

= 3.3V, TA = +25NC.)

IOVDD

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

IH2

IL2

RX/SDA, TX/SCL -110 +1 LOCK, ERR, GPIO_

V

= 1.7V to 1.9V 0.4

IOVDD

V

= 3.0V to 3.6V 0.3

IOVDD

IN+

IN-

) - (V

))/2

IN+

IN-

)

) - (V

IN-

IN2

OL2

V

ROH

V

ROL

V

)

IDH(P)

V

IDL(P)

V

CMR

R

IH

IL

VIN = 0V to V

(Note 2)

IOVDD

I

= 3mA

OUT

No high-speed data transmission (Figure 1)

Figure 2 40 90 mV

Figure 2 -90 -40 mV

I

ADD0 and ADD1 open or connected

INM

to a driver with output in high impedance (Note 3)

ADD0 and ADD1 = high or low, PWDN = high or low

ICL = -18mA -1.5 V

Figure 3 250 450 mV

Figure 3 25 mV

Figure 3 1.125 1.375 V

Figure 3 25 mV

DV

IN

CL

OD

OS

0.7 x

V

IOVDD

0.3 x

V

IOVDD

-80 +1

30 60 mV

-60 -30 mV

1 1.3 1.6 V

80 100 130

0.7 x

V

IOVDD

0.3 x

V

IOVDD

-10 +10

-150 +150

MAX9268

V

FA

V

I

V

FA

_______________________________________________________________________________________ 3

Gigabit Multimedia Serial Link Deserializer with LVDS System Interface

DC ELECTRICAL CHARACTERISTICS (continued)

(V

= V

AVDD

Typical values are at V

Output Short-Circuit Current I

Magnitude of Differential Output

MAX9268

Short-Circuit Current

Output High-Impedance Current I

POWER SUPPLY

Worst-Case Supply Current (Figure 4)

Sleep-Mode Supply Current I Power-Down Current I

= 3.0V to 3.6V, V

DVDD

AVDD

= V

= 1.7V to 3.6V, RL = 100Ω Q1% (differential), TA = -40NC to +105NC, unless otherwise noted.

IOVDD

DVDD

= V

= 3.3V, TA = +25NC.)

IOVDD

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

OS

I

OSD

OZ

I

WCS

CCS

CCZ

V

= 0V or 3.6V

OUT

3.5mA LVDS output 7.5 7mA LVDS output 15

ADD0 and ADD1 = high or low, PWDN = high or low

BWS = low, f BWS = low, f BWS = low, f BWS = low, f

PWDN = GND

3.5mA LVDS output -7.5 +7.5 7mA LVDS output -15 +15

-0.5 +0.5

TXCLKOUT_

= 16.6MHz 142 180 = 33.3MHz 153 200 = 66.6MHz 179 240 = 104MHz 212 280

80 130 19 70

mA

FA

mA

FA FA

AC ELECTRICAL CHARACTERISTICS

(V

= V

AVDD

Typical values are at V

LVDS CLOCK OUTPUTS (TXCLKOUT+, TXCLKOUT-)

Clock Frequency f

I2C/UART PORT TIMING

Output Rise Time t

Output Fall Time t

Input Setup Time t Input Hold Time t

SWITCHING CHARACTERISTICS

CNTL_ Output Rise-and-Fall Time tR, t

LVDS Output Rise Time t LVDS Output Fall Time t

= 3.0V to 3.6V, V

DVDD

AVDD

= V

= 1.7V to 3.6V, RL = 100Ω Q1% (differential), TA = -40NC to +105NC, unless otherwise noted.

IOVDD

DVDD

= V

= 3.3V, TA = +25NC.)

IOVDD

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

BWS = GND, V

TXCLKOUT_

R

F

SET

HOLD

BWS = GND, DRS = GND 16.66 104 V

BWS

V

BWS

30% to 70%, CL = 10pF to 100pF, 1kI pullup to IOVDD (Figure 5)

70% to 30%, CL = 10pF to 100pF, 1kI pullup to IOVDD (Figure 5)

I2C only (Figure 5) 100 ns I2C only (Figure 5) 0 ns

20% to 80%, CL = 10pF, DCS = 1 (Figure 6)

F

20% to 80%, CL = 5pF, DCS = 0 (Figure 6)

R

F

20% to 80%, RL = 100I (Figure 3) 80% to 20%, RL = 100I (Figure 3)

= V = V

= V

DRS

IOVDD

, V

= V

DRS

IOVDD

, DRS = GND 12.5 78

8.33 16.66

6.25 12.5

20 150 ns

V

= 1.7V to 1.9V 0.5 3.1

IOVDD

V

= 3.0V to 3.6V 0.3 2.2

IOVDD

V

= 1.7V to 1.9V 0.6 3.8

IOVDD

V

= 3.0V to 3.6V 0.4 2.4

IOVDD

MHz

ns

200 350 ps 200 350 ps

4 ______________________________________________________________________________________

Gigabit Multimedia Serial Link Deserializer

with LVDS System Interface

AC ELECTRICAL CHARACTERISTICS (continued)

(V

= V

AVDD

Typical values are at V

LVDS Output Pulse Position t

LVDS Output Enable Time t

LVDS Output Disable Time t

Deserializer Delay t Reverse Control-Channel Output

Rise Time

Reverse Control-Channel Output Fall Time

Lock Time t Power-Up Time t

I2S OUTPUT TIMING

WS Jitter t

SCK Jitter t

Audio Skew Relative to Video t

SCK, SD, WS Rise-and-Fall Time t

SD, WS Valid Time Before SCK t

SD, WS Valid Time After SCK t

Note 2: Minimum IIN due to voltage drop across the internal pullup resistor. Note 3: Measured in serial link bit times. Bit time = 1/(30 x f

Note 4: Rising to rising-edge jitter can be twice as large.

= 3.0V to 3.6V, V

DVDD

AVDD

= V

= 1.7V to 3.6V, RL = 100Ω Q1% (differential), TA = -40NC to +105NC, unless otherwise noted.

IOVDD

DVDD

= V

= 3.3V, TA = +25NC.)

IOVDD

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

f

TXCLKOUT_

PPOSN

N = 0 to 6, t 1/f

TXCLKOUT_

f

TXCLKOUT_

104MHz

CLK

=

,

f

TXCLKOUT_

f

TXCLKOUT_

(Figure 7)

f

TXCLKOUT_

LVEN

LVDS

SD

t

R

t

F

LOCK

PU

From the last bit of the enable UART packet to VOS = 1125mV

From the last bit of the enable UART packet to VOS = 0V

Figure 8 (Note 4) 3540 Bits No forward-channel data transmission

(Figure 1)

No forward-channel data transmission (Figure 1)

Figure 9 3.6 ms Figure 10 4.1 ms

tWS = 1/fWS,

fWS = 48kHz or 44.1kHz

rising (falling)

AJ-WS

edge to falling (rising) edge (Note 5)

fWS = 192kHz

nWS = 16 bits, fWS = 48kHz or 44.1kHz

,

SCK

nWS = 24 bits, fWS = 96kHz

AJ-SCK

t

= 1/f

SCK

rising edge to rising edge

nWS = 32 bits, fWS = 192kHz

Video and audio synchronized 3 x t

20% to 80%

t

= 1/f

SCK

t

= 1/f

SCK

CL = 10pF, DCS = 1 0.3 3.1 CL = 5pF, DCS = 0 0.4 3.8

(Figure 11)

SCK

(Figure 11)

SCK

TXCLKOUT_

) for BWS = GND. Bit time = 1/(40 x f

V

IOVDD

ASK

R, tF

DVB

DVA

.

= 12.5MHz

= 33MHz

= 78MHz

= 104MHz

N/7 x t

- 250

- 200

- 125

- 100

CLK

N/7 x

t

CLK

N/7 x

t

CLK

N/7 x

t

CLK

N/7 x

t

CLK

N/7 x t

+ 250

N/7 x t

+ 200

N/7 x t

+ 125

N/7 x t

+ 100

CLK

100

180 400 ns

0.35 x t

SCK

0.35 x

t

SCK

-3

0.4e x t

WS

-3

0.8e x t

WS

-3

1.6e x t

WS

-3

13e

x t

SCK

-3

39e

x t

SCK

0.1

x t

SCK

WS

0.5 x

t

SCK

0.5 x

t

SCK

TXCLKOUT_

0.5e x t

1e

x t

2e

x t

16e

x t

48e

x t

0.13

x t

4 x t

-3

WS

-3

WS

-3

WS

-3

SCK

-3

SCK

WS

) for V

MAX9268

ps

Fs

nsfWS = 96kHz

ns

Fs

ns

=

BWS

_______________________________________________________________________________________ 5

Gigabit Multimedia Serial Link Deserializer with LVDS System Interface

Typical Operating Characteristics

(V

AVDD

= V

DVDD

= V

= 3.3V, TA = +25NC, unless otherwise noted.)

IOVDD

TOTAL SUPPLY CURRENT

vs. TXCLKOUT_ FREQUENCY

(3-CHANNEL MODE)

210

MAX9268

PRBS PATTERN

200

ALL EQUALIZER MODES ALL SPREAD MODES

190

180

170

160

TOTAL SUPPLY CURRENT (mA)

150

140

5 105

TXCLKOUT_ FREQUENCY (MHz)

OUTPUT POWER SPECTRUM vs. TXCLKOUT_ FREQUENCY

(VARIOUS MAX9268 SPREAD)

-10

-20

0% SPREAD

-30

-40

-50

-60

-70

-80

OUTPUT POWER SPECTRUM (dBm)

-90

-100 61 71

2% SPREAD

TXCLKOUT_ FREQUENCY (MHz)

f

TXCLKOUT_

4% SPREAD

85654525

= 66MHz

69676563

TOTAL SUPPLY CURRENT

vs. TXCLKOUT_ FREQUENCY

(4-CHANNEL MODE)

210

PRBS PATTERN

200

MAX9268 toc01

ALL EQUALIZER MODES ALL SPREAD MODES

190

180

170

160

TOTAL SUPPLY CURRENT (mA)

150

140

5 80

TXCLKOUT_ FREQUENCY (MHz)

MAXIMUM TXCLKOUT_ FREQUENCY vs. STP CABLE LENGTH (BER < 10

120

100

MAX9268 toc04

OPTIMUM

80

PE/EQ SETTINGS

NO PE, 10.7dB

60

EQUALIZATION

40

NO PE, 5.2dB EQUALIZATION

20

BER CAN BE AS LOW AS 10

MAXIMUM TXCLKOUT_ FREQUENCY (MHz)

CABLE LENGTHS LESS THAN 10m

0

0 20

STP CABLE LENGTH (m)

OUTPUT POWER SPECTRUM vs. TXCLKOUT_ FREQUENCY

(VARIOUS MAX9268 SPREAD)

-10

-20

MAX9268 toc02

OUTPUT POWER SPECTRUM (dBm)

65503520

0% SPREAD

-30

-40

-50

-60

-70

-80

-90

-100

30.5 35.5

2% SPREAD

TXCLKOUT_ FREQUENCY (MHz)

f

TXCLKOUT_

4% SPREAD

= 33MHz

MAX9268 toc03

34.533.532.531.5

MAXIMUM TXCLKOUT_ FREQUENCY

vs. ADDITIONAL DIFFERENTIAL

-9

)

-12

FOR

15105

120

10m STP CABLE

100

MAX9268 toc05

80

60

NO PE, 10.7dB

40

EQUALIZATION

NO PE, 5.2dB EQUALIZATION

20

BER CAN BE AS LOW AS 10

MAXIMUM TXCLKOUT_ FREQUENCY (MHz)

FOR OPTIMUM PE/EQ SETTINGS

0

ADDITIONAL DIFFERENTIAL LOAD CAPACITANCE (pF)

C

(BER < 10-9)

L

PE/EQ SETTINGS

OPTIMUM

-12

MAX9268 toc06

FOR CL < 4pF

86420 10

6 ______________________________________________________________________________________

Gigabit Multimedia Serial Link Deserializer

with LVDS System Interface

Pin Configuration

TXOUT1+

AVDD

AGND

TXOUT2-

TXOUT2+

TXCLKOUT-

TXCLKOUT+

TXOUT3-

TOP VIEW

TXOUT0-

TXOUT0+

36 35 34

TXOUT1-

33 32 31 30 29 28 27 26 25

TXOUT3+

MAX9268

AGND

GND

IOVDD

ADD0 ADD1 LOCK

ERR

MS

SSEN

DRS AVDD AGND

37

38

39

40

41

42

43

44

45

46

47

48

+

1

2

INT

BWS

MAX9268

EP

4

5

6

7

8

9

10

11

EQS

GPIO1

12

DVDD

GND

3

IN-

GPIO0

AVDD

IN+

AGND

CDS

24

23

22

21

20

19

18

17

16

15

14

13

AGND AVDD GND IOVDD CNTL2/MCLK CNTL1 SD/CNTL0 SCK WS PWDN TX/SCL RX/SDA

TQFP

Pin Description

PIN NAME FUNCTION

1

BWS

2 INT

3 CDS

4 GPIO0

5, 23, 32, 47 AVDD

6, 7 IN+, IN- Differential CML Input. Differential input of the serial link.

8, 24, 31, 37, 48 AGND Analog Ground

9 EQS

Bus-Width Select. Output width selection requires external pulldown or pullup resistor. Set BWS = low for 3-channel mode. Set BWS = high for 4-channel mode.

Interrupt Input. Requires external pulldown or pullup resistor. A transition on the MAX9268’s INT input toggles the GMSL serializer’s INT output.

Control Direction Selection. Control link direction selection input requires external pulldown or pullup resistor. Set CDS = low for FC on the GMSL serializer side of the serial link. Set CDS = high for FC on the MAX9268 side of the serial link.

General-Purpose I/O 0. Open-drain, general-purpose input/output with internal 60kI (typ) pullup resistor to IOVDD. GPIO0 is high impedance during power-up and when PWDN = low.

3.3V Analog Power Supply. Bypass AVDD to AGND with 0.1FF and 0.001FF capacitors as close as possible to the device with the smaller capacitor closest to AVDD.

Equalizer Select Input. EQS requires external pulldown or pullup resistor. The state of EQS latches upon power-up or when resuming from power-down mode (PWDN = low). Set EQS = low for 10.7dB equalizer boost (EQTUNE = 1001). Set EQS = high for 5.2dB equalizer boost (EQTUNE = 0100).

_______________________________________________________________________________________ 7

Gigabit Multimedia Serial Link Deserializer with LVDS System Interface

Pin Description (continued)

PIN NAME FUNCTION

10 GPIO1

11 DVDD

MAX9268

12, 22, 38 GND Digital and I/O Ground

13 RX/SDA

14 TX/SCL

15 PWDN Power-Down. Active-low power-down input requires external pulldown or pullup resistor. 16 WS I2S Word-Select Output 17 SCK I2S Serial-Clock Output 18 SD/CNTL0 I2S Serial-Data/Control Output. Disable I2S to use SD/CNTL0 as an additional control output.

19 CNTL1

20 CNTL2/MCLK

General-Purpose I/O 1. Open-drain general-purpose input/output with internal 60kI (typ) pullup resistor to IOVDD. GPIO1 is high impedance during power-up and when PWDN = low.

3.3V Digital Power Supply. Bypass DVDD to GND with 0.1FF and 0.001FF capacitors as close as possible to the device with the smaller capacitor closest to DVDD.

Receive/Serial Data. UART receive or I2C serial-data input/output with internal 30kI (typ) pullup to IOVDD. In UART mode, RX/SDA is the Rx input of the MAX9268’s UART. In I2C mode, RX/SDA is the SDA input/output of the MAX9268’s I2C master.

Transmit/Serial Clock. UART transmit or I2C serial-clock output with internal 30kI (typ) pullup to IOVDD. In UART mode, TX/SCL is the Tx output of the MAX9268’s UART. In I2C mode, TX/ SCL is the SCL output of the MAX9268’s I2C master.

Control Output 1. CNTL1 is not active in 3-channel mode and remains low. To use CNTL1, drive BWS high (4-channel mode) and set DISCNTL = 0. CNTL1 is mapped from DOUT27.

Control 2/MCLK Output. CNTL2/MCLK is not active in 3-channel mode and remains low. To use CNTL2/MCLK, drive BWS high (4-channel mode). CNTL2/MCLK is mapped from DOUT28. CNTL/MCLK can also be used to output MCLK (see the Additional MCLK Output for Audio Applications section).

I/O Supply Voltage. 1.8V to 3.3V logic I/O power supply. Bypass IOVDD to GND with

21, 39 IOVDD

25, 26, 29, 30,

33–36

27, 28

40 ADD0

41 ADD1

42 LOCK

43 ERR

8 ______________________________________________________________________________________

TXOUT_+,

TXOUT_-

TXCLKOUT+,

TXCLKOUT-

0.1FF and 0.001FF capacitors as close as possible to the device with the smaller capacitor closest to IOVDD.

Differential LVDS Data Outputs. Set BWS = low (3-channel mode) to use TXOUT0_ to TXOUT2_. Set BWS = high (4-channel mode) to use TXOUT0_ to TXOUT3_.

Differential LVDS Output for the LVDS Clock

Address Selection Input 0. Three-level input to select the MAX9268’s device address (see Table 2). The state of ADD0 latches upon power-up or when resuming from power-down mode (PWDN = low).

Address Selection Input 1. Three-level input to select the MAX9268’s device address (see Table 2). The state of ADD1 latches upon power-up or when resuming from power-down mode (PWDN = low).

Open-Drain Lock Output with Internal 60kI (typ) Pullup to IOVDD. LOCK = high indicates PLLs are locked with correct serial-word-boundary alignment. LOCK = low indicates PLLs are not locked or incorrect serial-word-boundary alignment. LOCK remains low when the configuration link is active. LOCK is high impedance when PWDN = low.

Active-Low, Open-Drain Video Data Error Output with Internal 60kI (typ) Pullup to IOVDD. ERR goes low when the number of decoding errors during normal operation exceeds a programmed error threshold, or when at least one PRBS error is detected during PRBS test. ERR is high impendence when PWDN = low.

Gigabit Multimedia Serial Link Deserializer

with LVDS System Interface

Pin Description (continued)

PIN NAME FUNCTION

44 MS

45 SSEN

46 DRS

— EP

Functional Diagram

Mode Select. Control link mode-selection input requires an external pulldown or pullup resistor. Set MS = low to select base mode. Set MS = high to select bypass mode.

Spread-Spectrum Enable. Serial link spread-spectrum enable input requires an external pulldown or pullup resistor. The state of SSEN latches upon power-up or when resuming from power-down mode (PWDN = low). Set SSEN = high for Q2% spread spectrum on the LVDS and control outputs. Set SSEN = low to use the LVDS and control outputs without spread spectrum.

Data-Rate Select. Data-rate range-selection input requires an external pulldown or pullup resistor. The state of DRS latches upon power-up or when resuming from power-down mode (PWDN = low). Set DRS = high for TXCLKOUT_ frequencies of 8.33MHz to 16.66MHz (3-channel mode), or

6.25MHz to 12.5MHz (4-channel mode). Set DRS = low for TXCLKOUT_ frequencies of 16.66MHz to 104MHz (3-channel mode), or 12.5MHz to 78MHz (4-channel mode).

Exposed Pad. EP internally connected to AGND. MUST externally connect EP to the plane supplying AGND for proper thermal and electrical performance.

MAX9268

TXCLKOUT+/-

TXOUT0+/-

TXOUT1+/-

TXOUT2+/-

TXOUT3+/-

CNTL1 (4-CH)

CNTL2/MCLK

(4-CH)

7x PLL

PARALLEL

TO LVDS

SSPLL

RGB[17:0]

HS HS

VS

DE

RGB[23:18] (4-CH)

RES/CNTL1

(4-CH)

VIDEO

FIFO

AUDIO

RGB

VS

DE

CNTL1/RES

CNTL2

ACB

FCC

CLK

DIV

8b/10b

DECODE/

UNSCRAMBLE

UART/I

CDR

PLL

SERIAL

TO

PARALLEL

REVERSE CONTROL

Rx/EQ

Tx

CHANNEL

IN+

IN-

MAX9268

2

C

SD/CNTL0 TX/SCL RX/SDASCK WS

_______________________________________________________________________________________ 9

Gigabit Multimedia Serial Link Deserializer with LVDS System Interface

R

/2

IN+

L

MAX9268

V

OD

REVERSE

CONTROL-CHANNEL

TRANSMITTER

IN-

RL/2

V

CMR

MAX9268

IN+

V

CMR

IN-

V

ROH

0.9 x V

ROH

0.1 x V

(IN+) - (IN-)

ROH

t

R

Figure 1. Reverse Control-Channel Output Parameters

IN-

IN+

0.1 x V

ROL

0.9 x V

ROL

t

F

R

/2

L

IN+

V

ROL

V

RL/2

V

IN+

+

_

+

V

IN-

_

ID(P)

IN-

_

C

V

ID(P) =

CMR =

| V

(V

IN

- V

|

IN+

IN-

+ V

)/2

IN+

IN-

IN

Figure 2. Test Circuit for Differential Input Measurement

10 _____________________________________________________________________________________

Gigabit Multimedia Serial Link Deserializer

TXOUT_-

TXCLKOUT-

TXOUT_+

TXCLKOUT+

(TXOUT_+) - (TXOUT_-)

(TXCLKOUT+) - (TXCLKOUT-)

with LVDS System Interface

MAX9268

TXOUT_+

TXCLKOUT+

TXOUT_-,

TXCLKOUT-

V

OS(-)

DV

OS

V

OD(-)

t

R

DVOD = |V

/2

R

L

V

OD

/2

R

L

((TXOUT_+) + (TXOUT_-))/2

((TXCLKOUT+) + (TXCLKOUT-))/2

V

OS(+)

= |V

- V

OS(-)

OD(-)

|

OS(+)

VOD(+)

OD(+)

GND

V

OS

V

OS(-)

V

= 0V

OD

V

t

F

OD(-)

Figure 3. LVDS Output Parameters

Figure 4. Worst-Case Pattern Output

TX/

SCL

RX/

SDA

P

TXCLKOUT+

TXCLKOUT-

TXOUT0+ TO TXOUT3+

TXOUT0- TO TXOUT3-

CNTL_

t

R

t

HOLD

t

F

t

SET

PSS

Figure 5. I2C Timing Parameters

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