The MAX9259/MAX9260 chipset presents Maxim’s
gigabit multimedia serial link (GMSL) technology. The
MAX9259 serializer pairs with the MAX9260 deserializer
to form a complete digital serial link for joint transmission
of high-speed video, audio, and control data.
The MAX9259/MAX9260 allow a maximum serial payload
data rate of 2.5Gbps for a 15m shielded twisted-pair
(STP) cable. The 24-bit or 32-bit width parallel interface
operates up to a maximum bus clock of 104MHz or
78MHz, respectively. This serial link supports display
panels from QVGA (320 x 240) up to XGA (1280 x 768),
or dual-view WVGA (2 x 854 x 480).
The 24-bit or 32-bit mode handles 21 or 29 bits of data,
along with an I2S input, supporting 4- to 32-bit audio
word lengths and an 8kHz to 192kHz sample rate. The
embedded control channel forms a full-duplex, differential 100kbps to 1Mbps UART link between the serializer
and deserializer. The host electronic control unit (ECU)
or microcontroller (FC) resides either on the MAX9259
(for video display) or on the MAX9260 (for image sensing). In addition, the control channel enables ECU/FC
control of peripherals in the remote side of the serial link
through I2C (base mode) or a user-defined full-duplex
UART format (bypass mode).
The MAX9259 serializer driver preemphasis and channel equalizer on the MAX9260 extend the link length and
enhance the link reliability. Spread spectrum is available
on the MAX9259/MAX9260 to reduce EMI on the serial
and parallel output data signals. The differential link
complies with the ISO 10605 and IEC 61000-4-2 ESDprotection standards.
The core supplies for the MAX9259/MAX9260 are 1.8V
and 3.3V, respectively. Both devices use an I/O supply from 1.8V to 3.3V. These devices are available in
a 64-pin TQFP package (10mm x 10mm) and a 56-pin
TQFN package (8mm x 8mm x 0.75mm) with an exposed
pad. Electrical performance is guaranteed over the
-40NC to +105NC automotive temperature range.
Applications
High-Speed Serial-Data Transmission for Display
High-Speed Serial-Data Transmission for Image
Sensing
Automotive Navigation, Infotainment, and ImageSensing Systems
Features
S 2.5Gbps Payload Rate, AC-Coupled Serial Link
with 8B/10B Line Coding
S 24-Bit or 32-Bit Programmable Parallel Input Bus
Supports Up to XGA (1280 x 768) or Dual-View
WVGA (2 x 854 x 480) Panels with 18-Bit or 24-Bit
Color
S 8.33MHz to 104MHz (24-Bit Bus) or 6.25MHz to
78MHz (32-Bit Bus) Parallel Data Rate
S Support Two/Three 10-Bit Camera Links at
104MHz/78MHz Maximum Pixel Clock
S 4-Bit to 32-Bit Word Length, 8kHz to 192kHz I
2
S
Audio Channel Supports High-Definition Audio
S Embedded Half-/Full-Duplex Bidirectional Control
Channel (100kbps to 1Mbps)
S Separate Interrupt Signal Supports Touch-Screen
Functions for Display Panels
S Remote-End I
S Preemphasis Line Driver (MAX9259)/Line
2
C Master for Peripherals
Equalizer (MAX9260)
S Programmable Spread Spectrum on the Serial or
Parallel Data Outputs Reduce EMI
S Deserializer Does Not Require an External Clock
S Auto Data-Rate Detection Allows “On-The-Fly”
Data-Rate Change
S Input Clock PLL Jitter Attenuator (MAX9259)
S Built-In PRBS Generator/Checker for BER Testing
S Line-Fault Detector Detects Wire Shorts to
Ground, Battery, or Open Link
S ISO 10605 and IEC 61000-4-2 ESD Protection
S -40NC to +105NC Operating Temperature Range
S Patent Pending
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ESD Protection
Human Body Model (RD = 1.5kI, CS = 100pF)
(OUT+, OUT-) to AGND (MAX9259) ............................Q8kV
(IN+, IN-) to AGND (MAX9260) ....................................Q8kV
All Other Pins to Any Ground (MAX9259) ....................Q4kV
All Other Pins to Any Ground (MAX9260) ....................Q4kV
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
MAX9259 Pin Description (continued)
PIN
TQFPTQFN
3631TX/SCL
3732SSEN
3833LMN1Line-Fault Monitor Input 1 (see Figure 3 for details)
40, 41
4337LMN0Line-Fault Monitor Input 0 (see Figure 3 for details)
MAX9259/MAX9260
4438LFLT
4539INT
4640DRS
4741ES
4842BWS
——EP
34, 35
NAMEFUNCTION
Transmit/Serial Clock. UART transmit or I2C serial-clock output with internal 30kI
pullup to IOVDD. In UART mode, TX/SCL is the Tx output of the MAX9259’s UART. In I2C
mode, TX/SCL is the SCL output of the MAX9259’s I2C master.
Spread-Spectrum Enable. Serial link spread-spectrum enable input requires external
pulldown or pullup resistors. The state of SSEN latches upon power-up or when resuming
from power-down mode (PWDN = low). Set SSEN = high for Q0.5% spread spectrum on
the serial link. Set SSEN = low to use the serial link without spread spectrum.
OUT-,
OUT+
Differential CML Output -/+. Differential outputs of the serial link.
Line Fault. Active-low open-drain line-fault output with a 60kI internal pullup resistor.
LFLT = low indicates a line fault. LFLT is high impedance when PWDN = low.
Interrupt Output to Indicate Remote Side Requests. INT = low upon power-up and when
PWDN = low. A transition on the INT input of the MAX9260 toggles the MAX9259’s INT
output.
Data-Rate Select. Data-rate range-selection input requires external pulldown or pullup
resistors. Set DRS = high for parallel input data rates of 8.33MHz to 16.66MHz (24-bit
mode) or 6.25MHz to 12.5MHz (32-bit mode). Set DRS = low for parallel input data rates
of 16.66MHz to 104MHz (24-bit mode) or 12.5MHz to 78MHz (32-bit mode).
Edge Select. PCLKIN trigger edge-selection input requires external pulldown or pullup
resistors. Set ES = low to trigger on the rising edge of PCLKIN. Set ES = high to trigger on
the falling edge of PCLKIN.
Bus-Width Select. Parallel input bus-width selection input requires external pulldown or
pullup resistors. Set BWS = low for 24-bit bus mode. Set BWS = high for 32-bit bus mode.
Exposed Pad. EP internally connected to AGND (TQFP package) or AGND and GND
(TQFN package). MUST externally connect EP to the AGND plane to maximize thermal
and electrical performance.
Enable. Active-low parallel output-enable input requires external pulldown or pullup
1
2BWS
3INT
4CDS
5GPIO0
6ES
7, 63AVDD
8 , 9IN+, IN-Differential CML Input +/-. Differential inputs of the serial link.
10, 64AGNDAnalog Ground
11EQS
12GPIO1
13DCS
ENABLE
resistors. Set ENABLE = low to enable PCLKOUT, SD, SCK, WS, and the parallel outputs, DOUT_. Set ENABLE = high to put PCLKOUT, SD, SCK, WS, and DOUT_ to high
impedance.
Bus-Width Select. Parallel output bus-width selection input requires external pulldown
or pullup resistors. Set BWS = low for 24-bit bus mode. Set BWS = high for 32-bit bus
mode.
Interrupt. Interrupt input requires external pulldown or pullup resistors. A transition on
the INT input of the MAX9260 toggles the MAX9259’s INT output.
Control-Direction Selection. Control-link-direction selection input requires external pulldown or pullup resistors. Set CDS = low for FC use on the MAX9259 side of the serial
link. Set CDS = high for FC use on the MAX9260 side of the serial link.
GPIO0. Open-drain general-purpose input/output with internal 60kI pullup resistors to
IOVDD. GPIO0 is high impedance during power-up and when PWDN = low.
Edge Select. PCLKOUT edge-selection input requires external pulldown or pullup
resistors. Set ES = low for a rising-edge trigger. Set ES = high for a falling-edge trigger.
3.3V Analog Power Supply. Bypass AVDD to AGND with 0.1µF and 0.001µF capacitors
as close as possible to the device with the smallest value capacitor closest to AVDD.
Equalizer Select. Deserializer equalizer-selection input requires external pulldown or
pullup resistors. The state of EQS latches upon power-up or rising edge of PWDN. Set
EQS = low for 10.7dB equalizer boost (EQTUNE = 1001). Set EQS = high for 5.2dB
equalizer boost (EQTUNE = 0100).
GPIO1. Open-drain general-purpose input/output with internal 60kI pullup resistors to
IOVDD. GPIO1 is high impedance during power-up and when PWDN = low.
Drive Current Select. Driver current-selection input requires external pulldown or pullup resistors. Set DCS = high for stronger parallel data and clock output drivers. Set
DCS = low for normal parallel data and clock drivers (see the MAX9260DC Electrical Characteristics table).
MAX9259/MAX9260
Mode Select. Control-link mode-selection/autostart mode selection input requires
external pulldown or pullup resistors. MS sets the control-link mode when CDS = high
(see the Control-Channel and Register Programming section). Set MS = low to select
base mode. Set MS = high to select the bypass mode. MS sets autostart mode when
CDS = low (see Tables 13 and 14).
3.3V Digital Power Supply. Bypass DVDD to DGND with 0.1FF and 0.001FF capacitors
as close as possible to the device with the smaller value capacitor closest to DVDD.
Receive/Serial Data. UART receive or I2C serial-data input/output with internal 30kI
pullup to IOVDD. In UART mode, RX/SDA is the Rx input of the MAX9260’s UART. In
I2C mode, RX/SDA is the SDA input/output of the MAX9259’s I2C master.
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
MAX9260 Pin Description (continued)
PINNAMEFUNCTION
Transmit/Serial Clock. UART transmit or I2C serial-clock output with internal 30kI
pullup to IOVDD. In UART mode, TX/SCL is the Tx output of the MAX9259’s UART. In
I2C mode, TX/SCL is the SCL output of the MAX9260’s I2C master.
Power-Down. Active-low power-down input requires external pulldown or pullup resistors.
Error. Active-low open-drain video data error output with internal pullup to IOVDD.
ERR goes low when the number of decoding errors during normal operation exceed a
programmed error threshold or when at least one PRBS error is detected during PRBS
test. ERR is high impendence when PWDN = low.
Open-Drain Lock Output with Internal Pullup to IOVDD. LOCK = high indicates PLLs
are locked with correct serial-word-boundary alignment. LOCK = low indicates PLLs
are not locked or incorrect serial-word-boundary alignment. LOCK remains low when
the configuration link is active. LOCK is high impedance when PWDN = low.
Serial Data. I2S serial-data output. Disable I2S to use SD as an additional data output
latched on the selected edge of PCLKOUT.
Data Output[0:28]. Parallel data outputs. Output data can be strobed on the selected
edge of PCLKOUT. Set BWS = low (24-bit mode) to use DOUT0–DOUT20 (RGB and
SYNC). DOUT21–DOUT28 are not used in 24-bit mode and are set to low. Set BWS =
high (32-bit mode) to use DOUT0–DOUT28 (RGB, SYNC, and two extra outputs).
DOUT28 can be used to output MCLK (see the Additional MCLK Output for Audio Applications section).
1.8V to 3.3V Logic I/O Power Supply. Bypass IOVDD to IOGND with 0.1FF and 0.001FF
30, 51IOVDD
41PCLKOUTParallel Clock Output. Used for DOUT0–DOUT28.
capacitors as close as possible to the device with the smaller value capacitor closest
to IOVDD.
Spread-Spectrum Enable. Parallel output spread-spectrum enable input requires
external pulldown or pullup resistors. The state of SSEN latches upon power-up or
when resuming from power-down mode (PWDN = low). Set SSEN = high for Q2%
spread spectrum on the parallel outputs. Set SSEN = low to use the parallel outputs
without spread spectrum.
Data-Rate Select. Data-rate range-selection input requires external pulldown or pullup
resistors. Set DRS = high for parallel input data rates of 8.33MHz to 16.66MHz (24-bit
mode) or 6.25MHz to 12.5MHz (32-bit mode). Set DRS = low for parallel input data
rates of 16.66MHz to 104MHz (24-bit mode) or 12.5MHz to 78MHz (32-bit mode).
Exposed Pad. EP internally connected to AGND. MUST externally connect EP to the
AGND plane to maximize thermal and electrical performance.
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
Detailed Description
The MAX9259/MAX9260 chipset presents Maxim’s
GMSL technology. The MAX9259 serializer pairs with the
MAX9260 deserializer to form a complete digital serial
link for joint transmission of high-speed video, audio,
and control data for video-display or image-sensing
applications. The serial-payload data rate can reach up
to 2.5Gbps for a 15m STP cable. The parallel interface
is programmable for 24-bit or 32-bit width modes at the
maximum bus clock of 104MHz or 78MHz, respectively.
The minimum bus clock is 6.25MHz for the 32-bit mode
and 8.33MHz for the 24-bit mode. With such a flexible
data configuration, the GMSL is able to support XGA
(1280 x 768) or dual-view WVGA (2 x 854 x 480) display
panels. For image sensing, it supports three 10-bit camera links simultaneously with a pixel clock up to 78MHz.
The 24-bit mode handles 21-bit data and control signals
MAX9259/MAX9260
plus an I2S audio signal. The 32-bit mode handles 29-bit
data and control signals plus an I2S audio signal. Any
combination and sequence of color video data, video
sync, and control signals make up the 21-bit or 29-bit
parallel data on DIN_ and DOUT_. The I2S port supports
the sampled audio data at a rate from 8kHz to 192kHz
and the audio word length of anywhere between 4 to
32 bits. The embedded control channel forms a UART
link between the serializer and deserializer. The UART
link can be set to half-duplex mode or full-duplex mode
depending on the application. The GMSL supports
UART rates from 100kbps to 1Mbps. Using this control
link, a host ECU or FC communicates with the serializer
and deserializer, as well as the peripherals in the remote
side, such as backlight control, grayscale gamma correction, camera module, and touch screen. All serial
communication (forward and reverse) uses differential
signaling. The peripheral programming uses I2C format
or the default GMSL UART format. A separate bypass
mode enables communication using a full-duplex, userdefined UART format. The control link between the
MAX9259 and MAX9260 allows FC connectivity to either
device or peripherals to support video-display or imagesensing applications.
The AC-coupled serial link uses 8B/10B coding. The
MAX9259 serializer features a programmable driver
preemphasis and the MAX9260 deserializer features
a programmable channel equalizer to extend the link
length and enhance the link reliability. Both devices have
a programmable spread-spectrum feature for reducing
EMI on the serial link output (MAX9259) and parallel data
outputs (MAX9260). The differential serial link input and
output pins comply with the ISO 10605 and IEC 610004-2 ESD-protection standards. The core supplies for the
MAX9259/MAX9260 are 1.8V and 3.3V, respectively.
Both devices use an I/O supply from 1.8V to 3.3V
Register Mapping
The FC configures various operating conditions of the
GMSL through registers in the MAX9259/MAX9260.
The default device addresses stored in the R0 and
R1 registers of the MAX9259/MAX9260 are 0x80 and
0x90, respectively. Write to the R0/R1 registers in both
devices to change the device address of the MAX9259
or MAX9260.
Table 1. MAX9259 Power-Up Default Register Map (see Table 18)
SEREN = 0 (AUTOS = high), SEREN = 1 (AUTOS = low), serial link enable default
depends on AUTOS pin state at power-up
CLINKEN = 0, configuration link disabled
PRBSEN = 0, PRBS test disabled
SLEEP = 0 or 1, sleep mode state depends on CDS and AUTOS pin state at
power-up (see the Link Startup Procedure section)
INTTYPE = 00, base mode uses I2C
REVCCEN = 1, reverse control channel active (receiving)
FWDCCEN = 1, forward control channel active (sending)
AUTOFM = 00, calibrate spread-modulation rate only once after locking
RESERVED = 0
SDIV = 00000, autocalibrate sawtooth divider
LOCKED = 0, LOCK output = low (read only)
OUTENB = 0 (ENABLE = low), OUTENB = 1 (ENABLE = high), OUTENB default
depends on ENABLE pin state at power-up
PRBSEN = 0, PRBS test disabled
SLEEP = 0 or 1, SLEEP setting default depends on CDS and MS pin state at power-up (see the Link Startup Procedure section)
INTTYPE = 00, base mode uses I2C
REVCCEN = 1, reverse control channel active (sending)
FWDCCEN = 1, forward control channel active (receiving)
The parallel bus uses two selectable bus widths, 24
bits and 32 bits. BWS selects the bus width according
to Table 3. In 24-bit mode, DIN21–DIN28 are not used
and are internally pulled down. For both modes, SD,
SCK, and WS pins are dedicated for I2S audio data. The
assignments of the first 21 or 29 signals are interchangeable and appear in the same order at both sides of the
serial link. In image-sensing applications, disabling the
I2S audio channel (through the MAX9259 and MAX9260
internal registers) allows the MAX9259 to serialize three
10-bit camera data streams through DIN[0:28] plus SD
inputs. The parallel bus accepts data clock rates from
8.33MHz to 104MHz for the 24-bit mode and 6.25MHz to
78MHz for the 32-bit mode.
Serial Link Signaling and Data Format
The MAX9259 high-speed data serial output uses
CML signaling with programmable preemphasis and
AC-coupling. The MAX9260 high-speed receiver uses
AC-coupling and programmable channel equalization.
Together, the GMSL operates at up to 3.125Gbps over
STP cable lengths up to 15m.
The MAX9259 serializer scrambles and encodes the
parallel input bits, and sends the 8B/10B coded sig-
nal through the serial link. The MAX9260 deserializer
MAX9259/MAX9260
recovers the embedded serial clock and then samples,
decodes, and descrambles the data onto the parallel output bus. Figures 22 and 23 show the serial-data
packet format prior to scrambling and 8B/10B coding.
For the 24-bit or 32-bit mode, the first 21 or 29 serial
bits come from DIN[20:0] or DIN[28:0], respectively.
The audio channel bit (ACB) contains an encoded audio
signal derived from the three I2S inputs (SD, SCK, and
WS). The forward control channel (FCC) bit carries the
forward control data. The last bit (PCB) is the parity bit of
the previous 23 or 31 bits.
Reverse Control Channel
The MAX9259/MAX9260 use the reverse control channel
to send I2C/UART and interrupt signals in the opposite
direction of the video stream from the deserializer to
the serializer. The reverse control channel and forward
video data coexist on the same twisted pair forming a
bidirectional link. The reverse control channel operates
independently from the forward control channel. The
reverse control channel is available 500Fs after powerup. The MAX9259 temporarily disables the reverse control channel for 350Fs after starting/stopping the forward
serial link.
Table 3. Bus-Width Selection Using BWS
BWS INPUT STATEBUS WIDTHPARALLEL BUS SIGNALS USED
Low24DIN[0:20]/DOUT[0:20], WS, SCK, SD
High32DIN[0:28]/DOUT[0:28], WS, SCK, SD
24 BITS
DIN0 DIN1
18-BIT
RGB
DATA
NOTE: LOCATIONS OF THE RGB DATA AND CONTROL SIGNALS ARE
INTERCHANGEABLE ACCORDINGLY ON BOTH SIDES OF THE LINK.
Figure 22. 24-Bit Mode Serial Link Data FormatFigure 23. 32-Bit Mode Serial Link Data Format
parallel data rate. Set DRS high to use a low-speed parallel data rate in the range of 6.25MHz to 12.5MHz (32-bit
mode) or 8.33MHz to 16.66MHz (24-bit mode). Set DRS
low for normal operation with parallel data rates higher
than 12.5MHz (32-bit mode) or 16.66MHz (24-bit mode).
Audio Channel
The I2S audio channel supports audio sampling rates
from 8kHz to 192kHz and audio word lengths from 4 bits
to 32 bits. The audio bit clock (SCK) does not need to be
synchronized with PCLKIN. The MAX9259 automatically
encodes audio data into a single bit stream synchronous
with PCLKIN. The MAX9260 decodes the audio stream
and stores audio words in a FIFO. Audio rate detection
uses an internal oscillator to continuously determine the
audio data rate and output the audio in I2S format. The
audio channel is enabled by default. When the audio
channel is disabled, the SD pins on both sides are
treated as a regular parallel data pin.
PCLK_ frequencies can limit the maximum supported
audio sampling rate. Table 4 lists the maximum audio
sampling rate for various PCLK_ frequencies. Spreadspectrum settings do not affect the I2S data rate or WS
clock frequency.
PCLK_ FREQUENCY
(DRS = HIGH)
(MHz)
Additional MCLK Output
for Audio Applications
Some audio DACs such as the MAX9850 do not require
a synchronous main clock (MCLK), while other DACs
require MCLK to be a specific multiple of WS. If an audio
DAC chip needs the MCLK to be a multiple of WS, synchronize the I2S audio data with PCLK_ of the GMSL,
which is typical for most applications. Select the PCLK_
to be the multiple of WS, or use a clock synthesis chip,
such as the MAX9491, to regenerate the required MCLK
from PCLK_ or SCK.
For audio applications that cannot directly use the
PCLKOUT output, the MAX9260 provides a divided
MCLK output on DOUT28 at the expense of one less
parallel line in 32-bit mode (24-bit mode is not affected).
By default, DOUT28 operates as a parallel data output
and MCLK is turned off. Set MCLKDIV (MAX9260 register 0x12, D[6:0]) to a non-zero value to enable the MCLK
output. Set MCLKDIV to 0x00 to disable MCLK and set
DOUT28 as a parallel data output.
The output MCLK frequency is:
f
f
MCLK
where f
MCLKDIV is the divider ratio from 1 to 127.
24-bit mode3 x f
32-bit mode4 x f
24-bit mode6 x f
32-bit mode8 x f
MCLK SOURCE
FREQUENCY (f
PCLKOUT
PCLKOUT
PCLKOUT
PCLKOUT
Internal oscillator
(120MHz typ)
SRC
MAX9259/MAX9260
)
Choose MCLKDIV values so that f
than 60MHz. MCLK frequencies derived from PCLK_
(MCLKSRC = 0) are not affected by spread-spectrum
settings in the deserializer (MAX9260). Enabling spread
spectrum in the serializer (MAX9259), however, introduces spread spectrum into MCLK. Spread-spectrum
settings of either device do not affect MCLK frequencies
derived from the internal oscillator. The internal oscillator frequency ranges from 100MHz to 150MHz over all
process corners and operating conditions.
is not greater
MCLK
Control-Channel and Register Programming
The FC uses the control link to send and receive control
data over the STP link simultaneously with the high-speed
data. Configuring the CDS pin allows the FC to control the
link from either the MAX9259 or the MAX9260 side to support video-display or image-sensing applications.
The control link between the FC and the MAX9259 or
MAX9260 runs in base mode or bypass mode according to the mode selection (MS) input of the device connected to the FC. Base mode is a half-duplex control link
and the bypass mode is a full-duplex control link. In base
mode, the FC is the host and accesses the registers of
both the MAX9259 and MAX9260 from either side of the
link by using the GMSL UART protocol. The FC can also
program the peripherals on the remote side by sending
the UART packets to the MAX9259 or MAX9260, with
UART packets converted to I2C by the device on the
remote side of the link (MAX9260 for LCD or MAX9259
for image-sensing applications). The FC communicates
with a UART peripheral in base mode (through INTTYPE
register settings) using the half-duplex default GMSL
UART protocol of the MAX9259 and MAX9260. The
device addresses of the MAX9259 and MAX9260 in the
base mode are programmable. The default values are
0x80 and 0x90, respectively.
In base mode, when the peripheral interface uses I2C
(default), the MAX9259/MAX9260 only convert packets
that have device addresses different from those of the
MAX9259 or MAX9260 to I2C. The converted I2C bit rate
is the same as the original UART bit rate.
In bypass mode, the FC bypasses the MAX9259/
MAX9260 and communicates with the peripherals directly using its own defined UART protocol. The FC cannot
access the MAX9259/MAX9260’s registers in this mode.
Peripherals accessed through the forward control channel using the UART interface need to handle at least one
PCLK_ period of jitter due to the asynchronous sampling
of the UART signal by PCLK_.
The MAX9259 embeds control signals going to the
MAX9260 in the high-speed forward link. Do not send
a low value longer than 100Fs in either base or bypass
mode. The MAX9260 uses a proprietary differential line
coding to send signals back towards the MAX9259. The
speed of the control link ranges from 100kbps to 1Mbps
in both directions. The MAX9259/MAX9260 automatically
detect the control-channel bit rate in base mode. Packet
bit rates can vary up to 3.5x from the previous bit rate
(see the Changing the Data Frequency section). Figure
24 shows the UART protocol for writing and reading in
base mode between the FC and the MAX9259/MAX9260.
Figure 25 shows the UART data format. Even parity is
used. Figures 26 and 27 detail the formats of the SYNC
byte (0x79) and ACK byte (0xC3). The FC and the connected slave chip generate the SYNC byte and ACK
byte, respectively. Certain events such as device wakeup and interrupt generate signals on the control path and
should be ignored by the FC. All data written to the internal registers do not take affect until after the acknowledge byte is sent. This allows the FC to verify that write
commands are processed without error, even if the result
of the write command directly affects the serial link. The
slave uses the SYNC byte to synchronize with the host
UART data rate automatically. If the INT or MS inputs of
the MAX9260 toggles while there is control-channel communication, the control-channel communication can be
corrupted. In the event of a missed acknowledge, the FC
should assume there was an error in the packet when the
D1D2D3D4D5D6D7
Interfacing Command-Byte-Only
slave device receives it, or that an error occurred during
the response from the slave device. In base mode, the
FC must keep the UART Tx/Rx lines high for 16 bit times
before starting to send a new packet.
As shown in Figure 28, the remote-side device converts
the packets going to or coming from the peripherals from
the UART format to the I2C format and vice versa. The
remote device removes the byte number count and adds
or receives the ACK between the data bytes of I2C. The
I2C’s data rate is the same as the UART data rate.
The MAX9259/MAX9260 UART-to-I2C conversion interfaces with devices that do not require register addresses, such as the MAX7324 GPIO expander. Change the
communication method of the I2C master using the
I2CMETHOD bit. I2CMETHOD = 1 sets command-byteonly mode, while I2CMETHOD = 0 sets normal mode
where the first byte in the data stream is the register
address. In this mode, the I2C master ignores the register address byte and directly reads/writes the subsequent data bytes (Figure 29).
The INT of the MAX9259 is the interrupt output and the
INT of the MAX9260 is the interrupt input. The interrupt
output on the MAX9259 follows the transitions at the
interrupt input of the MAX9260. This interrupt function
supports remote-side functions such as touch-screen
peripherals, remote power-up, or remote monitoring.
Interrupts that occur during periods where the reverse
control channel is disabled, such as link startup/shutdown, are automatically resent once the reverse control
channel becomes available again. Bit D4 of register
0x06 in the MAX9260 also stores the interrupt input state.
Writing to the SETINT register bit also sets the INT output
of the MAX9259. In addition, the FC sets the INT output
of the MAX9259 by writing to the SETINT register bit. In
normal operation, the state of the interrupt output changes when the interrupt input on the MAX9260 toggles.
Preemphasis Driver
The serial line driver in the MAX9259 employs currentmode logic (CML) signaling. The driver generates
an adjustable preemphasized waveform according to
the cable length and characteristics. There are 13
preemphasis settings, as shown in Table 6. Negative
preemphasis levels are deemphasis levels in which the
preemphasized swing level is the same as normal swing,
but the no-transition data is deemphasized. Program the
preemphasis levels through register 0x05 D[3:0] of the
MAX9259. This preemphasis function compensates the
high-frequency loss of the cable and enables reliable
transmission over longer link distances. Additionally, a
lower power drive mode can be entered by programming CMLLVL bits (0x05 D[5:4]) to reduce the driver
strength down to 75% (CMLLVL = 10), or 50% (CMLLVL
= 01) from 100% (CMLLVL = 11, default).
Line Equalizer
The MAX9260 includes an adjustable line equalizer to
further compensate cable attenuation at high frequencies. The cable equalizer has 11 selectable levels of
compensation from 2.1dB to 13dB (Table 7). The EQS
input selects the default equalization level at power-up.
The state of EQS is latched upon power-up or when
resuming from power-down mode. To select other
equalization levels, set the corresponding register bits
in the MAX9260 (0x05 D[3:0]). Use equalization in the
MAX9260, together with preemphasis in the MAX9259 to
create the most reliable link for a given cable.
To reduce the EMI generated by the transitions on the
serial link and parallel outputs, both the MAX9259 and
MAX9260 support spread spectrum. Turning on spread
spectrum on the MAX9260 spreads the parallel video
outputs. Turning on spread spectrum on the MAX9259
spreads the serial link, along with the MAX9260 parallel
outputs. Do not enable spread spectrum for both the
MAX9259 and MAX9260. The six selectable spreadspectrum rates at the MAX9259 serial output are Q0.5%,
Q1%, Q1.5%, Q2%, Q3%, and Q4% (Table 8). Some
spread-spectrum rates can only be used at lower PCLK_
frequencies (Table 9). There is no PCLK_ frequency limit
for the 0.5% spread rate. The two selectable spreadspectrum rates at the MAX9260 parallel outputs are Q2%
and Q4% (Table 10).
Set the MAX9259 SSEN input high to select 0.5% spread
at power-up and SSEN input low to select no spread at
power-up. Set the MAX9260 SSEN input high to select
2% spread at power-up and SSEN input low to select no
spread at power-up. The state of SSEN is latched upon
power-up or when resuming from power-down mode.
Whenever the MAX9259 spread spectrum is turned on
Table 11. MAX9259 Modulation Coefficients and Maximum SDIV Settings
BIT-WIDTH MODE
32-Bit
MAX9259/MAX9260
24-Bit
Q2% spread spectrum. Power-up default when SSEN = high.
Q4% spread spectrum
SPREAD-SPECTRUM
SETTING (%)
110440
0.510463
315227
1.515254
420415
220430
18052
0.58063
311237
1.511263
415221
215242
MODULATION
COEFFICIENT (decimal)
SDIV UPPER LIMIT (deci-
mal)
Table 12. MAX9260 Modulation Coefficients and Maximum SDIV Settings
SPREAD-SPECTRUM SETTING (%)
420815
220830
or off, the serial link automatically restarts and remains
unavailable while the MAX9260 relocks to the serial data.
Turning on spread spectrum on either the MAX9259 or
MAX9260 side does not affect the audio data stream.
Changes in the MAX9259 spread settings only affect
MCLK output if it is derived from PCLK_ (MCLKSRC = 0).
Both devices include a sawtooth divider to control the
spread-modulation rate. Autodetection or manual programming of the PCLK_ operation range guarantees a
spread-spectrum modulation frequency within 20kHz to
40kHz. Additionally, manual configuration of the sawtooth divider (SDIV, 0x03 D[5:0]) allows the user to set a
specific modulation frequency for a specific PCLK_ rate.
Always keep the modulation frequency between 20kHz
to 40kHz to ensure proper operation.
The modulation rates for the MAX9259 or the MAX9260
relate to the PCLK_ frequency as follows:
where:
fM = Modulation frequency
DRS = DRS pin input value (0 or 1)
f
= Parallel clock frequency (12.5MHz to 104MHz)
PCLK_
MOD = Modulation coefficient given in Table 11 for the
MAX9259 and Table 12 for the MAX9260
SDIV = 6-bit (MAX9259) or 5-bit (MAX9260) SDIV setting,
manually programmed by the FC
SDIV UPPER LIMIT (decimal)
f1 DRS
= +
()
M
Spectrum Divider
f
PCLK_
MOD SDIV
×
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
To program the SDIV setting, first look up the modulation
coefficient according to the part number and desired
bit-width and spread-spectrum settings. Solve the above
equation for SDIV using the desired parallel clock and
modulation frequencies. If the calculated SDIV value is
larger than the maximum allowed SDIV value in Tables
11 or 12, set SDIV to the maximum value.
Sleep Mode
The serializer/deserializer include a low-power sleep
mode to reduce power consumption on the device not
attached to the FC (MAX9260 in LCD applications and
MAX9259 in camera applications). Set the corresponding remote IC’s SLEEP bit to 1 to initiate sleep mode. The
MAX9259 sleeps immediately after setting its SLEEP =
1. The MAX9260 sleeps after serial link inactivity or 8ms
(whichever arrives first) after setting its SLEEP = 1. See
the Link Startup Procedure section for details on waking
up the device for different FC and starting conditions.
The FC side device cannot enter into sleep mode, and its
SLEEP bit remains at 0. Use the PWDN input pin to bring
the FC side device into a low-power state.
Configuration Link Mode
The MAX9259/MAX9260 include a low-speed configuration link to allow control-data connection between the two
devices in the absence of a valid parallel clock input. In
either display or camera applications, the configuration
link can be used to program equalizer/preemphasis
or other registers before establishing the video link.
An internal oscillator provides PCLK_ for establishing
the serial configuration link between the MAX9259 and
MAX9260. The parallel output clock and data lines are
disabled in the MAX9260. The LOCK output remains
low even after a successful configuration link lock. Set
CLINKEN = 1 on the MAX9259 to turn on the configuration link. The configuration link remains active as long as
the video link has not been enabled. The video link overrides the configuration link and attempts to lock when
SEREN = 1.
Link Startup Procedure
Table 13 lists four startup cases for video-display
applications. Table 14 lists two startup cases for imagesensing applications. In either display or image-sensing
applications, the control link is always available after
the high-speed data link or the configuration link is
established and the MAX9259/MAX9260 registers or the
peripherals are ready for programming.
Video-Display Applications
MAX9259/MAX9260
For the video-display application, with a remote display
unit, connect the FC to the serializer (MAX9259) and set
CDS = low for both the MAX9259 and MAX9260. Table
13 summarizes the four startup cases based on the settings of AUTOS and MS.
Case 1: Autostart Mode
After power-up or when PWDN transitions from low
to high for both the serializer and deserializer, the
serial link establishes if a stable PCLK_ is present. The
MAX9259 locks to PCLK_ and sends the serial data to
the MAX9260. The MAX9260 then detects activity on the
serial link and locks to the input serial data.
Case 2: Standby Start Mode
After power-up, or when PWDN transitions from low
to high for both the serializer and deserializer, the
MAX9260 starts up in sleep mode, and the MAX9259
stays in standby mode (does not send serial data). Use
the FC and program the MAX9259 to set SEREN = 1 to
establish a video link or CLINKEN = 1 to establish the
configuration link. After locking to a stable PCLK_ (for
SEREN = 1) or the internal oscillator (for CLINKEN = 1),
the MAX9259 sends a wake-up signal to the deserializer. The MAX9260 exits sleep mode after locking to the
serial data and sets SLEEP = 0. If after 8ms the deserializer does not lock to the input serial data, the MAX9260
goes back to sleep, and the internal sleep bit remains
uncleared (SLEEP = 1).
Case 3: Remote Side Autostart Mode
After power-up, or when PWDN transitions from low to
high, the remote device (MAX9260) starts up and tries
to lock to an incoming serial signal with sufficient power.
The host side (MAX9259) is in standby mode and does
not try to establish a link. Use the FC and program the
MAX9259 to set SEREN = 1 (and apply a stable PCLK_)
to establish a video link, or CLINKEN = 1 to establish the
configuration link. In this case, the MAX9260 ignores the
short wake-up signal sent from the MAX9259.
Case 4: Remote Side in Sleep Mode
After power-up or when PWDN transitions from low to
high, the remote device (MAX9260) starts up in sleep
mode. The high-speed link establishes automatically
after MAX9259 powers up with a stable PCLK_ and
sends a wake-up signal to the MAX9260. Use this mode
in applications where the MAX9260 powers up before
the MAX9259.
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
Table 13. Startup Selection for Video-Display Applications (CDS = Low)
CASE
AUTOS
(MAX9259)
MAX9259
POWER-UP STATEMS(MAX9260)
1LowSerialization enabledLow
2High
3High
Serialization dis-
abled
Serialization dis-
abled
MAX9259/MAX9260
4LowSerialization enabledHigh
High
Low
MAX9260
POWER-UP STATE
Normal
(SLEEP = 0)
Sleep mode
(SLEEP = 1)
Normal
(SLEEP = 0)
Sleep mode
(SLEEP = 1)
LINK STARTUP MODE
Both devices power up with
serial link active (autostart)
Serial link is disabled and
the MAX9260 powers up in
sleep mode. Set SEREN = 1 or
CLINKEN = 1 in the MAX9259
to start the serial link and wake
up the MAX9260.
Both devices power up in normal mode with the serial link
is disabled. Set SEREN = 1 or
CLINKEN = 1 in the MAX9259
to start the serial link.
MAX9260 starts in sleep mode.
Link autostarts upon MAX9259
power-up. Use this case when
the MAX9260 powers up before
the MAX9259.
AUTOS PIN
SETTING
LOW
HIGH
SEREN BIT
POWER-UP VALUE
PWDN = LOW OR
POWER-OFF
ALL STATES
1
0
POWER-DOWN
OR POWER-OFF
PWDN = HIGH
POWER-ON,
AUTOS = LOW
PWDN = HIGH,
POWER-ON
AUTOS = LOW
SEREN = 1,
PCLKIN RUNNING
VIDEO
LINK LOCKING
POWER-ON
IDLE
SEREN = 0, OR
NO PCLKIN
VIDEO LINK
LOCKED
VIDEO LINK
UNLOCKED
Figure 30. MAX9259 State Diagram, CDS = Low (LCD Application)
Figure 31. MAX9260 State Diagram, CDS = Low (LCD Application)
Image-Sensing Applications
For image-sensing applications, with remote camera
unit(s), connect the FC to the deserializer (MAX9260)
and set CDS = high for both the MAX9259 and MAX9260.
The MAX9260 powers up normally (SLEEP = 0) and continuously tries to lock to a valid serial input. Table 14
summarizes the two startup cases, based on the state of
the MAX9259 AUTOS pin.
Case 1: Autostart Mode
After power-up, or when PWDN transitions from low to
high, the MAX9259 locks to a stable PCLKIN and sends
the high-speed data to the MAX9260. The MAX9260
locks to the serial data and outputs the parallel video
data and PCLKOUT.
SIGNAL
DETECTED
PWDN = HIGH,
POWER-ON
OR
SERIAL PORT
VIDEO LINK
LOCKED
VIDEO LINK
OPERATING
LOCKING
0SLEEP
CONFIG LINK
UNLOCKED
CONFIG LINK
LOCKED
PRBSEN = 0
PRBSEN = 1
VIDEO LINK
UNLOCKED
VIDEO LINK
PRBS TEST
CONFIG LINK
OPERATING
PROGRAM
REGISTERS
0SLEEP
Case 2: Sleep Mode
After power-up, or when PWDN transitions from low to
high, the MAX9259 starts up in sleep mode. To wake up
the MAX9259, use the FC to send a regular UART frame
containing at least three rising edges (e.g., 0x66), at a
bit rate no greater than 1Mbps. The low-power wake-up
receiver of the MAX9259 detects the wake-up frame over
the reverse control channel and powers up. Reset the
sleep bit (SLEEP = 0) of the MAX9259 using a regular
control-channel write packet to power up the device fully.
Send the sleep bit write packet at least 500Fs after the
wake-up frame. The MAX9259 goes back to sleep mode
if its sleep bit is not cleared within 8ms (typ) after detecting a wake-up frame.
Table 14. Startup Selection for Image-Sensing Applications (CDS = High)
The MAX9260 checks the serial link for errors and stores
the number of detected decoding errors in the 8-bit
register (DECERR, 0x0D). If a large number of decoding
errors are detected within a short duration, the deserializer loses lock and stops the error counter. The deserializer then attempts to relock to the serial data. DECERR
resets upon successful video link lock, successful
readout of DECERR (through UART), or whenever autoerror reset is enabled. The MAX9260 does not check
for decoding errors during the internal PRBS test and
DECERR is reset to 0x00.
ERR Output
The MAX9260 has an open-drain ERR output. This
output asserts low whenever the number of decoding
errors exceed the error threshold (ERRTHR, 0x0C) during normal operation, or when at least one PRBS error is
detected during PRBS test. ERR reasserts high whenever DECERR (0x0D) resets, due to DECERR readout,
video link lock, or autoerror reset.
Autoerror Reset
The default method to reset errors is to read the respective error registers in the MAX9260 (0x0D, 0x0E). Autoerror reset clears the decoding-error counter (DECERR)
and the ERR output ~1Fs after ERR goes low. Autoerror
reset is disabled on power-up. Enable autoerror reset
through AUTORST (0x06 D6). Autoerror reset does not
run when the device is in PRBS test mode.
Self PRBS Test
The MAX9259/MAX9260 link includes a PRBS pattern generator and bit-error verification function. Set
PRBSEN = 1 (0x04 D5) first in the MAX9259 and then
the MAX9260 to start the PRBS test. Set PRBSEN = 0
(0x04 D5) first in the MAX9260 and then the MAX9259
to exit the PRBS self test. The MAX9260 uses an 8-bit
register (0x0E) to count the number of detected errors.
The control link also controls the start and stop of the
error counting. During PRBS mode, the device does not
count decoding errors and the ERR output reflects PRBS
errors only. Autoerror reset does not run when the device
is in PRBS mode.
Microcontrollers on Both Sides
of the GMSL Link (Dual µC Control)
Usually the FC is either on the serializer (MAX9259)
side for video-display applications, or on the deserializer (MAX9260) side for image-sensing applications. For
the former case, both the CDS pins of the MAX9259/
MAX9260 are set to low, and for the later case, the
CDS pins are set to high. However, if the CDS pin of the
MAX9259 is low and the CDS pin of the MAX9260 is high,
then the MAX9259/MAX9260 can both connect to FCs
simultaneously. In such a case, the FCs on either side
can communicate with the MAX9259/MAX9260 UART
protocol.
Contentions of the control link may happen if the FCs
on both sides are using the link at the same time. The
MAX9259/MAX9260 do not provide the solution for
contention avoidance. The serializer/deserealizer do not
send an acknowledge frame when communication fails
due to contention. Users can always implement a higherlayer protocol to avoid the contention. In addition, if UART
communication across the serial link is not required, the
FCs can disable the forward and reverse control channel
through the FWDCCEN and REVCCEN bits (0x04 D[1:0])
in the MAX9259/MAX9260. UART communication across
the serial link is stopped and contention between FCs no
longer occurs. During the dual FC operation, if one of the
CDS pins on either side changes state, the link resumes
the corresponding state described in the Link Startup Procedure section.
As an example of dual FC use in an image-sensing link,
the MAX9259 may be in sleep mode and waiting to be
waked up by the MAX9260. After wake-up, the serializerside FC sets the MAX9259 CDS pin low and assumes
master control of the MAX9259 registers.
Jitter-Filtering PLL
In some applications, the parallel bus input clock to the
MAX9259 (PCLKIN) includes noise, which reduces link
reliability. The MAX9259 has a narrow-band jitter-filtering
PLL to attenuate frequency components outside the
PLL’s bandwidth (< 100kHz typ). Enable the jitter-filtering
PLL by setting DISFPLL = 0 (0x05 D6).
Changing the Data Frequency
Both the video data rate (f
rate (f
applications with multiple clock speeds. Slow speed/
performance modes allow significant power savings
when a system’s full capabilities are not required. Enable
the MAX9259/MAX9260 link after PCLK_ stabilizes.
Stop PCLKIN for 5µs and restart the serial link or toggle
SEREN after each change in the parallel clock frequency
to recalibrate any automatic settings if a clean frequency
change cannot be guaranteed. The reverse control
channel remains unavailable for 350Fs after serial link
start or stop. Limit on-the-fly changes in f
tors of less than 3.5 at a time to ensure that the device
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
recognizes the UART sync pattern. For example, when
lowering the UART frequency from 1Mbps to 100kbps,
first send data at 333kbps and then at 100kbps to have
reduction ratios of 3 and 3.333, respectively.
LOCK Output Loopback
Connect the LOCK output to the INT input of the
MAX9260 to loopback LOCK to the MAX9259. The
interrupt output on the MAX9259 follows the transitions
at the LOCK output of the MAX9260. Reverse-channel
communication does not require an active forward link
to operate and accurately tracks the LOCK status of the
video link. LOCK asserts for video link only and not for
the configuration link.
MAX9260 GPIOs
The MAX9260 has two open-drain GPIOs available.
GPIO1OUT and GPIO0OUT (0x06 D3, D1) set the output
MAX9259/MAX9260
state of the GPIOs. The GPIO input buffers are always
enabled. The input states are stored in GPIO1 and
GPIO0 (0x06 D2, D0). Set GPIO1OUT/GPIO0OUT to 1
when using GPIO1/GPIO0 as an input.
Line-Fault Detection
The line-fault detector in the MAX9259 monitors for line
failures such as short to ground, short to power supply,
and open link for system fault diagnosis. Figure 3 shows
the required external resistor connections. LFLT = low
when a line fault is detected and LFLT = high when the
line returns to normal. The line-fault type is stored in
0x08 D[3:0] of the MAX9259. The fault-detector threshold voltages are referenced to the MAX9259 ground.
Additional passive components set the DC level of the
cable (Figure 3). If the MAX9259 and MAX9260 grounds
are different, the link DC voltage during normal operation
can vary and cross one of the fault-detection thresholds.
For the fault-detection circuit, select the resistor’s power
rating to handle a short to the battery. Table 15 lists the
mapping for line-fault types.
Staggered Parallel Data Outputs
The MAX9260 staggers the parallel data outputs to
reduce EMI and noise. Staggering outputs also reduce
the power-supply transient requirements. By default,
the deserializer staggers outputs according to Table
16. Disable output staggering through the DISSTAG bit
(0x06 D7)
Choosing I2C/UART Pullup Resistors
Both I2C/UART open-drain lines require pullup resistors
to provide a logic-high level. There are tradeoffs between
power dissipation and speed, and a compromise must
be made in choosing pullup resistor values. Every device
connected to the bus introduces some capacitance even
when the device is not in operation. I2C specifies 300ns
rise times to go from low to high (30% to 70%) for fast
mode, which is defined for data rates up to 400kbps (see
the I2C specifications in the Electrical Characteristics
table for details). To meet the fast-mode rise-time
requirement, choose the pullup resistors so that rise time
tR = 0.85 x R
are not recognized if the transition time becomes too
01Negative cable wire shorted to ground
10Normal operation
11Negative cable wire open
00Positive cable wire shorted to battery
01Positive cable wire shorted to ground
10Normal operation
11Positive cable wire open
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
slow. The MAX9259/MAX9260 support I2C/UART rates
up to 1Mbps.
AC-Coupling
AC-coupling isolates the receiver from DC voltages up to
the voltage rating of the capacitor. Four capacitors—two
at the serializer output and two at the deserializer input—
are needed for proper link operation and to provide
protection if either end of the cable is shorted to a high
voltage. AC-coupling blocks low-frequency ground shifts
and low-frequency common-mode noise.
Selection of AC-Coupling Capacitors
Voltage droop and the digital sum variation (DSV) of
transmitted symbols cause signal transitions to start
from different voltage levels. Because the transition time
is finite, starting the signal transition from different voltage levels causes timing jitter. The time constant for an
AC-coupled link needs to be chosen to reduce droop
and jitter to an acceptable level. The RC network for an
AC-coupled link consists of the CML receiver termination
resistor (RTR), the CML driver termination resistor (RTD),
and the series AC-coupling capacitors (C). The RC time
constant for four equal-value series capacitors is (C x
(RTD + RTR))/4. RTD and RTR are required to match the
transmission line impedance (usually 100I). This leaves
the capacitor selection to change the system time constant. Use at least 0.2FF (100V) high-frequency surfacemount ceramic capacitors to pass the lower speed
reverse-channel signal. Use capacitors with a case size
less than 3.2mm x 1.6mm to have lower parasitic effects
to the high-speed signal.
Power-Supply Circuits and Bypassing
The MAX9259 uses an AVDD and DVDD of 1.7V to 1.9V.
The MAX9260 uses an AVDD and DVDD of 3.0V to 3.6V.
All single-ended inputs and outputs on the MAX9259/
MAX9260 derive power from an IOVDD of 1.7V to 3.6V.
MAX9259/MAX9260
The input levels or output levels scale with IOVDD.
Proper voltage-supply bypassing is essential for highfrequency circuit stability.
Cables and Connectors
Interconnect for CML typically has a differential impedance of 100I. Use cables and connectors that have
matched differential impedance to minimize impedance
discontinuities. Twisted-pair and shielded twisted-pair
cables offer superior signal quality compared to ribbon
cable and tend to generate less EMI due to magneticfield canceling effects. Balanced cables pick up noise
as common mode rejected by the CML receiver. Table
17 lists the suggested cables and connectors used in
the GMSL link.
Board Layout
Separate the parallel signals and CML high-speed serial
signals to prevent crosstalk. Use a four-layer PCB with
separate layers for power, ground, CML, and digital
signals. Layout PCB traces close to each other and have
a 100I differential characteristic impedance. The trace
dimensions depend on the type of trace used (microstrip
or stripline). Note that two 50I PCB traces do not
have 100I differential impedance when brought close
together—the impedance goes down when the traces
are brought closer.
Route the PCB traces for a CML channel (there are two
conductors per CML channel) in parallel to maintain the
differential characteristic impedance. Avoid vias. If vias
must be used, use only one pair per CML channel and
place the via for each line at the same point along the
length of the PCB traces. This way, any reflections occur
at the same time. Do not make vias into test points for
Table 17. Suggested Connectors and Cables for GMSL
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
R
D
1.5kI
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
DEVICE
UNDER
HIGH-
VOLTAGE
DC
SOURCE
1MI
CHARGE-CURRENT-
LIMIT RESISTOR
C
S
100pF
Figure 34. Human Body Model ESD Test Circuit
R
D
330I
HIGH-
VOLTAGE
DC
SOURCE
CHARGE-CURRENT-
LIMIT RESISTOR
150pF
MAX9259/MAX9260
C
S
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
DEVICE
UNDER
Figure 35. IEC 61000-4-2 Contact Discharge ESD Test Circuit
TEST
TEST
ATE. Keep PCB traces that make up a differential pair
equal in length to avoid skew within the differential pair.
ESD Protection
The MAX9259/MAX9260 ESD tolerance is rated for
Human Body Model, IEC 61000-4-2, and ISO 10605. The
ISO 10605 and IEC 61000-4-2 standards specify ESD
tolerance for electronic systems. Serial outputs on the
MAX9259 and serial inputs on the MAX9260 meet ISO
10605 ESD protection and IEC 61000-4-2 ESD protection. All other pins meet the Human Body Model ESD
tolerances. The Human Body Model discharge components are CS = 100pF and RD = 1.5kI (Figure 34). The
IEC 61000-4-2 discharge components are CS = 150pF
and RD = 330I (Figure 35). The ISO 10605 discharge
components are CS = 330pF and RD = 2kI (Figure 36).
R
D
2kI
HIGH-
VOLTAGE
DC
SOURCE
CHARGE-CURRENT-
LIMIT RESISTOR
330pF
C
S
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
DEVICE
UNDER
TEST
Figure 36. ISO 10605 Contact Discharge ESD Test Circuit
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
Table 18. MAX9259 Register Table (see Table 1 for Default Value Details) (continued)
REGISTER
ADDRESS
MAX9259/MAX9260
0x04
BITSNAMEVALUEFUNCTION
Disable serial link. Power-up default when
AUTOS = high. Reverse-channel
D7SEREN
D6CLINKEN
D5PRBSEN
D4SLEEP
D[3:2]INTTYPE
D1REVCCEN
D0FWDCCEN
0
1
0Disable configuration link
1Enable configuration link
0Disable PRBS test
1Enable PRBS test
0
1
00Base mode uses I2C peripheral interface
10, 11Base mode peripheral interface disabled
0
1
0
1
communication remains unavailable for
350Fs after the MAX9259 starts/stops the
serial link.
Enable serial link. Power-up default when AUTOS = low. Reverse-channel
communication remains unavailable for
350Fs after the MAX9259 starts/stops the
serial link.
Normal mode. Default value depends on
CDS and AUTOS pin values at power-up.
Activate sleep mode. Default value depends
on CDS and AUTOS pin values at power-up.
Disable reverse control channel from
deserializer (receiving)
Enable reverse control channel from
deserializer (receiving)
Disable forward control channel to
deserializer (sending)
Enable forward control channel to
deserializer (sending)
1Filter PLL disabled
00Do not use
01200mV CML signal level
10300mV CML signal level
11400mV CML signal level
0000Preemphasis off
0001-1.2dB preemphasis
0010-2.5dB preemphasis
0011-4.1dB preemphasis
0100-6.0dB preemphasis
0101Do not use
0110Do not use
0111Do not use
10001.1dB preemphasis
10012.2dB preemphasis
10103.3dB preemphasis
10114.4dB preemphasis
11006.0dB preemphasis
11018.0dB preemphasis
111010.5dB preemphasis
111114.0dB preemphasis
00Negative cable wire shorted to battery
01Negative cable wire shorted to ground
10Normal operation
11Negative cable wire open
00Positive cable wire shorted to battery
01Positive cable wire shorted to ground
10Normal operation
11Positive cable wire open
Disable sending of I2C register address
(command-byte-only mode)
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
Table 19. MAX9260 Register Table (continued)
REGISTER
ADDRESS
MAX9259/MAX9260
0x05
0x06
BITSNAMEVALUEFUNCTION
0I2C conversion sends the register address
D7I2CMETHOD
D[6:5]HPFTUNE
D4PDHF
D[3:0]EQTUNE
D7DISSTAG
D6AUTORST
D5DISINT
D4INT
D3GPIO1OUT
D2GPIO1
D1GPIO0OUT
D0GPIO0
1
007.5MHz Equalizer highpass cutoff frequency
013.75MHz cutoff frequency
102.5MHz cutoff frequency
111.87MHz cutoff frequency
0High-frequency boosting enabled
1High-frequency boosting disabled
00002.1dB equalizer boost gain
00012.8dB equalizer boost gain
00103.4dB equalizer boost gain
00114.2dB equalizer boost gain
0100
01016.2dB equalizer boost gain
01107dB equalizer boost gain
01118.2dB equalizer boost gain
10009.4dB equalizer boost gain
1001
101011.7dB equalizer boost gain
101113dB equalizer boost gain
11XXDo not use
0Enable staggered outputs
1Disable staggered outputs
0
1
0Enable interrupt transmission to serializer
1Disable interrupt transmission to serializer
0INT input = low (read only)
1INT input = high (read only)
0Output low to GPIO1
1Output high to GPIO1
0GPIO1 is low
1GPIO1 is high
0Output low to GPIO0
1Output high to GPIO0
0GPIO0 is low
1GPIO0 is high
Disable sending of I2C register address
(command-byte-only mode)
5.2dB equalizer boost gain. Power-up default when EQS = high.
10.7dB equalizer boost gain. Power-up default when EQS = low.
Do not automatically reset error registers
and outputs
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
Chip Information
PROCESS: CMOS
MAX9259/MAX9260
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
17/10Added clarification of fault thresholds and updated Pin Description table
211/10
31/11Added Patent Pending to Features1
REVISION
DATE
DESCRIPTION
3, 4, 8, 11, 12, 13, 15,
16, 17, 25, 28, 33, 39,
Added TQFN package to Ordering Information, Absolute Maximum Ratings, Pin Configurations, Pin Description, and Package Information
PAGES
CHANGED
44, 48
1, 2, 10, 11, 50
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 51