MAXIM MAX9259, MAX9260 User Manual

19-4968; Rev 3; 1/11

EVALUATION KIT

AVAILABLE

Gigabit Multimedia Serial Link with Spread

Spectrum and Full-Duplex Control Channel

General Description

The MAX9259/MAX9260 chipset presents Maxim’s gigabit multimedia serial link (GMSL) technology. The MAX9259 serializer pairs with the MAX9260 deserializer to form a complete digital serial link for joint transmission of high-speed video, audio, and control data.

The MAX9259/MAX9260 allow a maximum serial payload data rate of 2.5Gbps for a 15m shielded twisted-pair (STP) cable. The 24-bit or 32-bit width parallel interface operates up to a maximum bus clock of 104MHz or 78MHz, respectively. This serial link supports display panels from QVGA (320 x 240) up to XGA (1280 x 768), or dual-view WVGA (2 x 854 x 480).

The 24-bit or 32-bit mode handles 21 or 29 bits of data, along with an I2S input, supporting 4- to 32-bit audio word lengths and an 8kHz to 192kHz sample rate. The embedded control channel forms a full-duplex, differential 100kbps to 1Mbps UART link between the serializer and deserializer. The host electronic control unit (ECU) or microcontroller (FC) resides either on the MAX9259 (for video display) or on the MAX9260 (for image sensing). In addition, the control channel enables ECU/FC control of peripherals in the remote side of the serial link through I2C (base mode) or a user-defined full-duplex UART format (bypass mode).

The MAX9259 serializer driver preemphasis and channel equalizer on the MAX9260 extend the link length and enhance the link reliability. Spread spectrum is available on the MAX9259/MAX9260 to reduce EMI on the serial and parallel output data signals. The differential link complies with the ISO 10605 and IEC 61000-4-2 ESDprotection standards.

The core supplies for the MAX9259/MAX9260 are 1.8V and 3.3V, respectively. Both devices use an I/O supply from 1.8V to 3.3V. These devices are available in a 64-pin TQFP package (10mm x 10mm) and a 56-pin TQFN package (8mm x 8mm x 0.75mm) with an exposed pad. Electrical performance is guaranteed over the

-40NC to +105NC automotive temperature range.

Applications

High-Speed Serial-Data Transmission for Display

High-Speed Serial-Data Transmission for Image Sensing

Automotive Navigation, Infotainment, and ImageSensing Systems

Features

S 2.5Gbps Payload Rate, AC-Coupled Serial Link

with 8B/10B Line Coding

S 24-Bit or 32-Bit Programmable Parallel Input Bus

Supports Up to XGA (1280 x 768) or Dual-View WVGA (2 x 854 x 480) Panels with 18-Bit or 24-Bit Color

S 8.33MHz to 104MHz (24-Bit Bus) or 6.25MHz to

78MHz (32-Bit Bus) Parallel Data Rate

S Support Two/Three 10-Bit Camera Links at

104MHz/78MHz Maximum Pixel Clock

S 4-Bit to 32-Bit Word Length, 8kHz to 192kHz I

2

S

Audio Channel Supports High-Definition Audio

S Embedded Half-/Full-Duplex Bidirectional Control

Channel (100kbps to 1Mbps)

S Separate Interrupt Signal Supports Touch-Screen

Functions for Display Panels

S Remote-End I S Preemphasis Line Driver (MAX9259)/Line

2

C Master for Peripherals

Equalizer (MAX9260)

S Programmable Spread Spectrum on the Serial or

Parallel Data Outputs Reduce EMI

S Deserializer Does Not Require an External Clock S Auto Data-Rate Detection Allows “On-The-Fly”

Data-Rate Change

S Input Clock PLL Jitter Attenuator (MAX9259) S Built-In PRBS Generator/Checker for BER Testing S Line-Fault Detector Detects Wire Shorts to

Ground, Battery, or Open Link

S ISO 10605 and IEC 61000-4-2 ESD Protection S -40NC to +105NC Operating Temperature Range S Patent Pending

Ordering Information

PART TEMP RANGE PIN-PACKAGE

MAX9259GCB/V+

MAX9259GCB/V+T MAX9259GTN/V+T MAX9260GCB/V+ MAX9260GCB/V+T

/V denotes an automotive qualified part.

+Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad.

T = Tape and reel.

-40NC to +105NC

64 TQFP-EP* 64 TQFP-EP* 56 TQFN-EP* 64 TQFP-EP* 64 TQFP-EP*

MAX9259/MAX9260

Typical Applications Circuit appears at end of data sheet.

_______________________________________________________________ Maxim Integrated Products 1

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel

ABSOLUTE MAXIMUM RATINGS

AVDD to AGND

MAX9259 ...........................................................-0.5V to +1.9V

MAX9260 ...........................................................-0.5V to +3.9V

DVDD to GND (MAX9259) ...................................-0.5V to +1.9V

DVDD to DGND (MAX9260) .................................-0.5V to +3.9V

IOVDD to GND (MAX9259) ..................................-0.5V to +3.9V

IOVDD to IOGND (MAX9260) .............................. -0.5V to +3.9V

Any Ground to Any Ground .................................-0.5V to +0.5V

OUT+, OUT- to AGND (MAX9259) ......................-0.5V to +1.9V

IN+, IN- to AGND (MAX9260) ..............................-0.5V to +1.9V

LMN_ to GND (MAX9259)

(60kI source impedance) ................................-0.5V to +3.9V

All Other Pins to GND (MAX9259) ....... -0.5V to (IOVDD + 0.5V)

All Other Pins to IOGND (MAX9260) ...-0.5V to (IOVDD + 0.5V) OUT+, OUT- Short Circuit to Ground or

Supply (MAX9259) .................................................Continuous

IN+, IN- Short Circuit to Ground or

Supply (MAX9260) .................................................Continuous

MAX9259/MAX9260

Continuous Power Dissipation (TA = +70NC)

64-Pin TQFP (derate 31.3mW/NC above +70NC) .......2508mW

56-Pin TQFN (derate 47.6mW/NC above +70NC) ....3809.5mW

PACKAGE THERMAL CHARACTERISTICS (Note 1)

64 TQFP

Junction-to-Ambient Thermal Resistance (BJA) .......31.9NC/W

Junction-to-Case Thermal Resistance (BJC) ................. 1NC/W

Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-

layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD Protection Human Body Model (RD = 1.5kI, CS = 100pF)

(OUT+, OUT-) to AGND (MAX9259) ............................Q8kV

(IN+, IN-) to AGND (MAX9260) ....................................Q8kV

All Other Pins to Any Ground (MAX9259) ....................Q4kV

All Other Pins to Any Ground (MAX9260) ....................Q4kV

IEC 61000-4-2 (RD = 330I, CS = 150pF) Contact Discharge

(OUT+, OUT-) to AGND (MAX9259) ..........................Q10kV

(IN+, IN-) to AGND (MAX9260) ....................................Q8kV

Air Discharge

(OUT+, OUT-) to AGND (MAX9259) ..........................Q12kV

(IN+, IN-) to AGND (MAX9260) ..................................Q10kV

ISO 10605 (RD = 2kI, CS = 330pF) Contact Discharge

(OUT+, OUT-) to AGND (MAX9259) ..........................Q10kV

(IN+, IN-) to AGND (MAX9260) ....................................Q8kV

Air Discharge

(OUT+, OUT-) to AGND (MAX9259) ..........................Q25kV

(IN+, IN-) to AGND (MAX9260) ..................................Q20kV

Operating Temperature Range ........................ -40NC to +105NC

Junction Temperature .....................................................+150NC

Storage Temperature Range ............................ -65NC to +150NC

Lead Temperature (soldering, 10s) ................................+300NC

Soldering Temperature (reflow) ......................................+260NC

56 TQFN

Junction-to-Ambient Thermal Resistance (BJA) ..........21NC/W

Junction-to-Case Thermal Resistance (BJC) ................. 1NC/W

MAX9259 DC ELECTRICAL CHARACTERISTICS

(V

= V

DVDD

Typical values are at V

SINGLE-ENDED INPUTS (DIN_, PCLKIN, PWDN, SSEN, BWS, ES, DRS, MS, CDS, AUTOS, SD, SCK, WS)

High-Level Input Voltage V

Low-Level Input Voltage V

Input Current I Input Clamp Voltage V

SINGLE-ENDED OUTPUT (INT)

High-Level Output Voltage V

Low-Level Output Voltage V

Output Short-Circuit Current I

2 ______________________________________________________________________________________

= 1.7V to 1.9V, V

AVDD

= V

DVDD

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

= 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted.

IOVDD

AVDD

= V

OH1IOH

= 1.8V, TA = +25NC.)

IOVDD

IH1

IL1

IN1

OL1

OS

VIN = 0 to V ICL = -18mA -1.5 V

CL

IOL = 2mA 0.2 V

VO = 0V

= -2mA

IOVDD

0.65 x

V

IOVDD

-10 +10

V

IOVDD

- 0.2

V

= 3.0V to 3.6V 16 35 64

IOVDD

V

= 1.7V to 1.9V 3 12 21

IOVDD

0.35 x

V

IOVDD

V

FA

V

mA

Gigabit Multimedia Serial Link with Spread

Spectrum and Full-Duplex Control Channel

MAX9259 DC ELECTRICAL CHARACTERISTICS (continued)

(V

= V

DVDD

Typical values are at V

I2C AND UART I/O, OPEN-DRAIN OUTPUTS (RX/SDA, TX/SCL, LFLT)

High-Level Input Voltage V

Low-Level Input Voltage V

Input Current I

Low-Level Open-Drain Output Voltage

DIFFERENTIAL OUTPUT (OUT+, OUT-)

Differential Output Voltage V

Change in VOD Between Complementary Output States

Output Offset Voltage, (V

+ + V

OUT

Change in VOS Between Complementary Output States

Output Short-Circuit Current I

Magnitude of Differential Output Short-Circuit Current

Output Termination Resistance (Internal)

REVERSE CONTROL-CHANNEL RECEIVER (OUT+, OUT-)

High Switching Threshold V Low Switching Threshold V

LINE-FAULT-DETECTION INPUT (LMN_)

Short-to-GND Threshold V Normal Thresholds V

Open Thresholds V

Open Input Voltage V Short-to-Battery Threshold V

POWER SUPPLY

Worst-Case Supply Current (Figure 4)

Sleep-Mode Supply Current I Power-Down Supply Current I

= 1.7V to 1.9V, V

AVDD

DVDD

= V

= 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted.

IOVDD

AVDD

= V

= 1.8V, TA = +25NC.)

IOVDD

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

IH2

IL2

V

IN2

OL2

VIN = 0 to V

IOL = 3mA

(Note 2) -110 +5

IOVDD

V

= 1.7V to 1.9V 0.4

IOVDD

V

= 3.0V to 3.6V 0.3

IOVDD

Preemphasis off (Figure 1) 300 400 500

OD

3.3dB preemphasis setting, V (Figure 2)

3.3dB deemphasis setting, V

OD(P)

OD(D)

(Figure 2)

DV

OD

OUT

-)/2 = V

OS

V

DV

I

OSD

R

CHR

CLR

I

WCS

CCS

CCZ

OS

TG

TN

TO

TE

Preemphasis off 1.1 1.4 1.56 V

OS

V

OUT+

V

OUT+

or V or V

= 0V -60

OUT-

= 1.9V 25

OUT-

VOD = 0V 25 mA

From OUT+, OUT- to V

O

AVDD

Figure 3 0.3 V Figure 3 0.57 1.07 V

Figure 3 1.45

Figure 3 1.47 1.75 V

IO

Figure 3 2.47 V

f

= 16.6MHz 100 125

PCLKIN

f

= 33.3MHz 105 145

BWS = GND

= GND

PWDN

PCLKIN

f

= 66.6MHz 116 155

PCLKIN

f

= 104MHz 135 175

PCLKIN

0.7 x

V

IOVDD

0.3 x

V

IOVDD

350 610

240 425

15 mV

45 54 63

27 mV

-27 mV

VIO+

0.06

40 110

5 70

mV

MAX9259/MAX9260

V

FA

V

P-P

mA

I

V

mA

FA FA

_______________________________________________________________________________________ 3

Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel

MAX9259 AC ELECTRICAL CHARACTERISTICS

(V

= V

DVDD

Typical values are at V

PARALLEL CLOCK INPUT (PCLKIN)

Clock Frequency f

Clock Duty Cycle DC t Clock Transition Time tR, t

Clock Jitter t

I2C/UART PORT TIMING (Note 3)

Output Rise Time t

MAX9259/MAX9260

Output Fall Time t

Input Setup Time t Input Hold Time t

SWITCHING CHARACTERISTICS (Note 3)

Differential Output Rise-and-Fall Time

Total Serial Output Jitter t

Deterministic Serial Output Jitter t Parallel Data Input Setup Time t Parallel Data Input Hold Time t

Serializer Delay (Note 4) t

Link Start Time t Power-Up Time t

I2S INPUT TIMING

WS Frequency f Sample Word Length n

SCK Frequency f

SCK Clock High Time (Note 3) t

SCK Clock Low Time (Note 3) t

SD, WS Setup Time t SD, WS Hold Time t

= 1.7V to 1.9V, V

AVDD

DVDD

= V

= 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted.

IOVDD

AVDD

= V

= 1.8V, TA = +25NC.)

IOVDD

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

V

PCLKIN

F

J

R

F

SET

HOLD

tR, t

F

= V

BWS

V

= V

BWS

V

= V

BWS

V

= V

BWS

HIGH/tT

(Figure 5) 4 ns

3.125Gbps, 300kHz sinusoidal jitter 800 ps

30% to 70%, CL = 10pF to 100pF, 1kI pullup to IOVDD

70% to 30%, CL = 10pF to 100pF, 1kI pullup to IOVDD

I2C only (Figure 6) 100 ns I2C only (Figure 6) 0 ns

20% to 80%, VOD ≥ 400mV, RL = 100I, serial-data rate = 3.125Gbps

GND

IOVDD

or t

, V

= V

, V

, V , V

LOW/tT

DRS

IOVDD

= V

GND

= V

DRS

= V

IOVDD

GND

(Figure 5) 35 50 65 %

8.33 16.66

16.66 104

6.25 12.5

12.5 78

20 150 ns

90 150 ps

3.125Gbps PRBS signal, measured at

TSOJ1

VOD = 0V differential, preemphasis

0.25 UI

disabled (Figure 7)

DSOJ2

SET

HOLD

SD

LOCK

PU

WS

SCK

HC

LC

SET

HOLD

3.125Gbps PRBS signal 0.15 UI (Figure 8) 1 ns (Figure 8) 1.5 ns

(Figure 9)

Spread spectrum enabled 2830

Spread spectrum disabled 270 (Figure 10) 3.5 ms (Figure 11) 3.5 ms

(Table 4) 8 192 kHz (Table 4) 4 32 Bits

f

= fWS x nWS x 2

SCK

V

≥ VIH, t

SCK

V

≤ VIL, t

SCK

= 1/f

SCK

(8 x 4)

x 2

0.35 x t

SCK

0.35 x t

SCK

(Figure 12, Note 3) 2 ns (Figure 12, Note 3) 2 ns

(192 x

32) x 2

MHz

(P-P)

Bits

kHz

ns

4 ______________________________________________________________________________________

Gigabit Multimedia Serial Link with Spread

Spectrum and Full-Duplex Control Channel

MAX9260 DC ELECTRICAL CHARACTERISTICS

(V

= V

DVDD

Typical values are at V

SINGLE-ENDED INPUTS (ENABLE, INT, PWDN, SSEN, BWS, ES, DRS, MS, CDS, EQS, DCS)

High-Level Input Voltage V

Low-Level Input Voltage V

Input Current I Input Clamp Voltage V

SINGLE-ENDED OUTPUTS (DOUT_, SD, WS, SCK, PCLKOUT)

High-Level Output Voltage V

Low-Level Output Voltage V

Output Short-Circuit Current I

I2C AND UART I/O, OPEN-DRAIN OUTPUTS (RX/SDA, TX/SCL, ERR, GPIO_, LOCK)

High-Level Input Voltage V

Low-Level Input Voltage V

Input Current I

Low-Level Open-Drain Output Voltage

= 3.0V to 3.6V, V

AVDD

DVDD

= V

= 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted.

IOVDD

AVDD

= V

= 3.3V, TA = +25NC.)

IOVDD

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

IH1

IL1

IN1

CL

OH

OL1

VIN = 0 to V

IOVDD

ICL = -18mA -1.5 V

V

= V

DCS

IOGND

IOH = -2mA

V

= V

IOL = 2mA

DOUT_, SD, WS, SCK

DCS

V

DCS

V

DCS

VO = 0V, V

= V

DCS

VO = 0V, V

= V

DCS

= V = V

IOGND

IOVDD

IOGND

IOVDD

V

3.0V to 3.6V

V

1.7V to 1.9V

V

3.0V to 3.6V

V

IOVDD

=

1.7V to 1.9V

OS

PCLKOUT

VO = 0V, V

= V

DCS

VO = 0V, V

= V

DCS

IOGND

IOVDD

V

=

IOVDD

3.0V to 3.6V

V

=

IOVDD

1.7V to 1.9V

V

=

IOVDD

3.0V to 3.6V

V

=

IOVDD

1.7V to 1.9V

IH2

IL2

RX/SDA, TX/SCL -110 +1 GPIO, ERR, LOCK

V

= 1.7V to 1.9V 0.4 V

IOVDD

V

= 3.0V to 3.6V 0.3 V

IOVDD

V

IN2

OL2

VIN = 0 to V (Note 2)

IOL = 3mA

IOVDD

0.65 x

V

IOVDD

-10 +10

V

IOVDD

- 0.3

V

IOVDD

- 0.2

15 25 39

3 7 13

20 35 63

5 10 21

15 33 50

5 10 17

30 54 97

9 16 32

0.7 x

V

IOVDD

-80 +1

0.35 x

V

IOVDD

0.3

0.2

0.3 x

V

IOVDD

MAX9259/MAX9260

V

FA

V

mA

V

FA

_______________________________________________________________________________________ 5

Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel

MAX9260 DC ELECTRICAL CHARACTERISTICS (continued)

(V

= V

DVDD

Typical values are at V

DIFFERENTIAL OUTPUTS FOR REVERSE CONTROL CHANNEL (IN+, IN-)

Differential High Output Peak Voltage, (VIN+) - (VIN-)

Differential Low Output Peak Voltage, (VIN+) - (VIN-)

DIFFERENTIAL INPUTS (IN+, IN-)

Differential High Input Threshold (Peak), (VIN+) - (VIN-)

Differential Low Input Threshold (Peak), (VIN+) - (VIN-)

Input Common-Mode Voltage,

MAX9259/MAX9260

((VIN+) + (VIN-))/2

Differential Input Resistance (Internal)

POWER SUPPLY

Worst-Case Supply Current (Figure 15)

Sleep-Mode Supply Current I Power-Down Supply Current I

= 3.0V to 3.6V, V

AVDD

= V

DVDD

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

= 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted.

IOVDD

AVDD

= V

V

ROH

V

ROL

V

IDH(P)

V

IDL(P)

V

CMR

I

WCS

CCS

CCZ

= 3.3V, TA = +25NC.)

IOVDD

No high-speed data transmission (Figure 13)

(Figure 14) 40 90 mV

(Figure 14) -90 -40 mV

R

I

V

BWS

f

PCLKOUT

V

BWS

f

PCLKOUT

V

BWS

f

PCLKOUT

V

BWS

f

PCLKOUT

V

PWDN

= V

IOGND

= 16.6MHz

= V

IOGND

= 33.3MHz

= V

IOGND

= 66.6MHz

= V

IOGND

= 104MHz

= V

IOGND

2% spread spectrum active

,

Spread spectrum disabled

2% spread spectrum active

,

Spread spectrum disabled

2% spread spectrum active

,

Spread spectrum disabled

2% spread spectrum active

,

Spread spectrum disabled

30 60 mV

-60 -30 mV

1 1.3 1.6 V

80 100 130

113 166

105 155

122 181

110 165

137 211

120 188

159 247

135 214

80 130 19 70

I

mA

FA FA

6 ______________________________________________________________________________________

Gigabit Multimedia Serial Link with Spread

Spectrum and Full-Duplex Control Channel

MAX9260 AC ELECTRICAL CHARACTERISTICS

(V

= V

DVDD

Typical values are at V

PARALLEL CLOCK OUTPUT (PCLKOUT)

Clock Frequency f

Clock Duty Cycle DC t

Clock Jitter t

I2C/UART PORT TIMING

Output Rise Time t

Output Fall Time t

Input Setup Time t Input Hold Time t

SWITCHING CHARACTERISTICS

PCLKOUT Rise-and-Fall Time tR, t

Parallel Data Rise-and-Fall Time (Figure 17)

Deserializer Delay t

Lock Time t

Power-Up Time t

Reverse Control-Channel Output Rise Time

Reverse Control-Channel Output Fall Time

= 3.0V to 3.6V, V

AVDD

DVDD

= V

= 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted.

IOVDD

AVDD

= V

= 3.3V, TA = +25NC.)

IOVDD

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

V

PCLKOUT

J

R

F

SET

HOLD

= V

BWS

V

= V

BWS

V

= V

BWS

V

= V

BWS

or t

HIGH/tT

Period jitter, RMS, spread off, 3.125Gbps, PRBS pattern, UI = 1/f

30% to 70%, CL = 10pF to 100pF, 1kI pullup to IOVDD

70% to 30%, CL = 10pF to 100pF, 1kI pullup to IOVDD

I2C only 100 ns I2C only 0 ns

IOGND

IOVDD

LOW/tT

, V

DRS

, V

DRS

, V

DRS

, V

DRS

(Figure 16) 40 50 60 %

20% to 80%, V

= 1.7V to 1.9V

IOVDD

F

20% to 80%, V

= 3.0V to 3.6V

IOVDD

20% to 80%, V

= 1.7V to 1.9V

IOVDD

tR, t

F

20% to 80%, V

= 3.0V to 3.6V

IOVDD

SD

LOCK

PU

t

Spread spectrum enabled (Figure 18) 2880 Spread spectrum disabled (Figure 18) 750 Spread spectrum enabled (Figure 19) 1500 Spread spectrum off (Figure 19) 1000 (Figure 20) 2500

No high-speed transmission (Figure 13) 180 400 ns

R

No high-speed transmission (Figure 13) 180 400 ns

F

= V

IOVDD

= V

IOGND

= V

IOVDD

= V

IOGND

PCLKOUT

V

DCS

CL = 10pF

V

DCS

CL = 5pF

V

DCS

CL = 10pF

V

DCS

CL = 5pF

V

DCS

CL = 10pF

V

DCS

CL = 5pF

V

DCS

CL = 10pF

V

DCS

CL = 5pF

= V

IOVDD

IOGND

IOVDD

IOGND

IOVDD

IOGND

IOVDD

IOGND

8.33 16.66

16.66 104

6.25 12.5

12.5 78

0.05 UI

20 150 ns

,

0.4 2.2

,

0.5 2.8

,

0.25 1.7

,

0.3 2.0

,

0.5 3.1

,

0.6 3.8

,

0.3 2.2

,

0.4 2.4

MAX9259/MAX9260

MHz

ns

Bits

Fs

_______________________________________________________________________________________ 7

Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel

MAX9260 AC ELECTRICAL CHARACTERISTICS (continued)

(V

= V

DVDD

Typical values are at V

I2S OUTPUT TIMING

WS Jitter t

SCK Jitter t

MAX9259/MAX9260

Audio Skew Relative to Video

SCK, SD, WS Rise-and-Fall Time tR, t

SD, WS Valid Time Before SCK t

SD, WS Valid Time After SCK t

= 3.0V to 3.6V, V

AVDD

DVDD

= V

= 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted.

IOVDD

AVDD

= V

= 3.3V, TA = +25NC.)

IOVDD

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

AJ-WS

AJ-SCK

ASK

F

DVB

DVA

fWS = 48kHz or

tWS = 1/fWS, rising

44.1kHz

(falling) edge to falling (rising) edge (Note 5)

fWS = 192kHz

nWS = 16 bits, fWS = 48kHz or 44.1kHz

t

= 1/f

SCK

edge to rising edge

SCK

, rising

nWS = 24 bits, fWS = 96kHz

nWS = 32 bits, fWS = 192kHz

Video and audio synchronized 3 x tWS4 x t

V

20% to 80%

t

= 1/f

SCK

t

SCK

= 1/f

SCK

= V

DCS

V

= V

DCS

(Figure 21)

, CL = 10pF 0.3 3.1 ns

IOVDD

, CL = 5pF 0.4 3.8 ns

IOGND

x t

0.35

SCK

0.35

SCK

0.4e - 3 x t

WS

0.8e - 3 x t

WS

1.6e - 3 x t

WS

13e - 3

x t

SCK

39e - 3

x t

SCK

0.1

x t

SCK

0.5

x t

SCK

0.5

x t

SCK

0.5e - 3 x t

WS

1e - 3

x t

WS

2e - 3

x t

WS

16e - 3

x t

SCK

48e - 3

x t

SCK

0.13

x t

SCK

WS

nsfWS = 96kHz

ns

µs

ns

Note 2: Minimum IIN due to voltage drop across the internal pullup resistor. Note 3: Not production tested. Note 4: Bit time = 1/(30 x f

RXCLKIN

) (BWS = 0), = 1/(40 x f

RXCLKIN

) (BWS = V

IOVDD

).

Note 5: Rising to rising edge jitter can be twice as large.

Typical Operating Characteristics

(V

= V

DVDD

vs. PCLKIN FREQUENCY (24-BIT MODE)

135

130

125

120

115

110

105

SUPPLY CURRENT (mA)

100

95

90

5 105

8 ______________________________________________________________________________________

AVDD

= V

= 1.8V (MAX9259), V

IOVDD

MAX9259 SUPPLY CURRENT

PREEMPHASIS =

0x0B TO 0x0F

PREEMPHASIS =

0x01 TO 0x04

PREEMPHASIS = 0x00

PCLKIN FREQUENCY (MHz)

= V

DVDD

vs. PCLKIN FREQUENCY (32-BIT MODE)

135

130

125

MAX9259/60 toc01

120

115

110

105

SUPPLY CURRENT (mA)

100

95

85654525

90

5 80

AVDD

= V

= 3.3V (MAX9260), TA = +25NC, unless otherwise noted.)

IOVDD

MAX9259 SUPPLY CURRENT

PREEMPHASIS =

0x0B TO 0x0F

PREEMPHASIS =

0x01 TO 0x04

PREEMPHASIS = 0x00

65503520

PCLKIN FREQUENCY (MHz)

155

150

145

MAX9259/60 toc02

140

135

130

125

120

SUPPLY CURRENT (mA)

115

110

105

MAX9260 SUPPLY CURRENT

vs. PCLKOUT FREQUENCY (24-BIT MODE)

ALL EQUALIZER SETTINGS

5 105

PCLKOUT FREQUENCY (MHz)

85654525

MAX9259/60 toc03

Gigabit Multimedia Serial Link with Spread

OUTPUT POWER SPECTRUM

Spectrum and Full-Duplex Control Channel

Typical Operating Characteristics (continued)

(V

DVDD

= V

AVDD

= V

= 1.8V (MAX9259), V

IOVDD

DVDD

= V

AVDD

= V

= 3.3V (MAX9260), TA = +25NC, unless otherwise noted.)

IOVDD

MAX9259/MAX9260

MAX9260 SUPPLY CURRENT

vs. PCLKOUT FREQUENCY (32-BIT MODE)

155

ALL EQUALIZER SETTINGS

150

145

140

135

130

125

120

SUPPLY CURRENT (mA)

115

110

105

5 80

PCLKOUT FREQUENCY (MHz)

65503520

SERIAL LINK SWITCHING PATTERN

WITHOUT PREEMPHASIS

(PARALLEL BIT RATE = 104MHz, 10m STP CABLE)

400.0mV 3.12Gbps

-400.0mV 52.00ps/div

MAX9259/60 toc07

OUTPUT POWER SPECTRUM

vs. PCLKOUT FREQUENCY

(MAX9259 SPREAD ON, MAX9260 SPREAD OFF)

0

f

= 42MHz

PCLKOUT

-10 0% SPREAD

-20

-30

-40

-50

-60

PCLKOUT OUTPUT POWER (dBm)

-70

-80

2% SPREAD

39 45

PCLKOUT FREQUENCY (MHz)

0.5% SPREAD

4% SPREAD

444340 41 42

MAX9260 SUPPLY CURRENT

vs. PCLKOUT FREQUENCY (24-BIT MODE)

180

170

MAX9259/60 toc04

160

150

140

130

SUPPLY CURRENT (mA)

120

110

100

2%, 4% SPREAD

NO SPREAD

5 105

PCLKOUT FREQUENCY (MHz)

SERIAL LINK SWITCHING PATTERN

WITH 14dB PREEMPHASIS

(PARALLEL BIT RATE = 104MHz, 10m STP CABLE)

250.0mV

-250.0mV 52.00ps/div

OUTPUT POWER SPECTRUM

vs. PCLKOUT FREQUENCY

(MAX9260 SPREAD ON, MAX9259 SPREAD OFF)

0

f

= 42MHz

PCLKOUT

-10

MAX9259/60 toc10

0% SPREAD

-20

-30

-40

-50

-60

PCLKOUT OUTPUT POWER (dBm)

-70

-80

2% SPREAD

39 45

PCLKOUT FREQUENCY (MHz)

4% SPREAD

856525 45

MAX9259/60 toc08

3.12Gbps

444340 41 42

vs. PCLKOUT FREQUENCY (32-BIT MODE)

180

170

MAX9259/60 toc05

160

150

140

130

SUPPLY CURRENT (mA)

120

110

100

5 80

(MAX9259 SPREAD ON, MAX9260 SPREAD OFF)

0

-10

-20

-30

-40

-50

-60

PCLKOUT OUTPUT POWER (dBm)

-70

-80

18.5 21.5

120

MAX9259/60 toc11

100

80

60

FREQUENCY (MHz)

40

20

0

0 20

MAX9260 SUPPLY CURRENT

2%, 4% SPREAD

NO SPREAD

655020 35

PCLKOUT FREQUENCY (MHz)

vs. PCLKOUT FREQUENCY

f

= 20MHz

PCLKOUT

0% SPREAD 0.5% SPREAD

4% SPREAD2% SPREAD

21.020.519.0 19.5 20.0

PCLKOUT FREQUENCY (MHz)

MAXIMUM PCLKIN FREQUENCY vs.

STP CABLE LENGTH (BER < 10

OPTIMUM PE/EQ

SETTINGS

NO PE, EQS = LOW

NO PE, EQS = HIGH

BER CAN BE < 10 CABLE LENGTHS LESS THAN 10m

-12

FOR

CABLE LENGTH (m)

-9

15105

MAX9259/60 toc06

MAX9259/60 toc09

)

MAX9259/60 toc12

_______________________________________________________________________________________ 9

Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel

Pin Configurations

TOP VIEW

DRS

INT

LMN0

AVDD

OUT+

OUT-

AGND

LMN1

SSEN

DIN17

DIN18

TX/SCL

DIN19

RX/SDA

DIN20

BWS

48

49

50

GND

51

IOVDD

DIN1

52

53

DIN2

54

DIN3

DIN4

55

DIN5

56

DIN6

57

DIN7

58

59

DIN8

60

DIN9

MAX9259/MAX9260

GND

DVDD

DIN10

DIN11

61

62

63

64

DIN12

ES

DIN13

EP*

DIN14

DIN15

LFLT

DIN16

PCLKIN

MAX9259

GND

IOVDD

TQFP

AGND

38394041424344454647

111098765432 16151413121

AVDD

(10mm × 10mm × 1mm)

PWDN

3334353637

DIN21

CDS

DIN22

TOP VIEW

DOUT11

DOUT12

DOUT14

DOUT15

PCLKOUT

DOUT16

DOUT17

DOUT18

DOUT19

DOUT21

DOUT22

DOUT9

48

32

MSDIN0

31

GND

30

IOVDD

29

AUTOS

28

WS

27

SCK

SD

26

25

DIN28

24

DIN27

23

DIN26

22

DIN25

21

DIN24

20

GND

19

DVDD

18

AGND

17

DIN23

IOGND

IOVDD

DOUT7

DOUT6

DOUT5

DOUT4

DOUT3

DOUT2

DOUT1

DOUT0

IOGND

SSEN

DRS

AVDD

AGND

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

ENABLE

DOUT10

INT

BWS

DOUT13

38394041424344454647

MAX9260

EP*

111098765432 16151413121

ES

IN-

IN+

CDS

GPIO0

AVDD

AGND

EQS

GPIO1

TQFP

DOUT20

MS

DCS

DVDD

3334353637

DOUT23

DGND

32

DOUT24DOUT8

31

IOGND

30

IOVDD

29

DOUT25

28

DOUT26

27

DOUT27

DOUT28/MCLK

26

25

SD

24

SCK

23

WS

22

LOCK

21

IOGND

20

ERR

19

PWDN

18

TX/SCL

17

RX/SDA

(10mm × 10mm × 1mm)

TOP VIEW

TX/SCL

RX/SDA

EP*

DIN20

DIN21

PWDN

DIN22

28

CDS

27

MS

26

IOVDD

25

AUTOS

24

WS

23

SCK

22

SD

21

DIN28

20

DIN27

19

DIN26

18

DIN25

17

DIN24

16

DVDD

15

DIN23

DRS

ES

BWS

42 41 40 39 38 37 36 35 34 33 32 31 30 29

DIN0

43

IOVDD

44

DIN1

45

DIN2

46

DIN3

47

DIN4

48

DIN5

49

DIN6

50

DIN7

51

52

DIN8

53

DIN9

54

DVDD

55

DIN10

DIN11

*CONNECT EP TO GROUND PLANE

+

56

1 2

3 4 5 6 7 8 9 10 11 12 13 14

DIN14

DIN13

DIN12

LMN1

OUT-

OUT+

AVDD

LMN0

LFLT

INT

MAX9259

AVDD

DIN18

IOVDD

TQFN

DIN17

DIN16

DIN15

PCLKIN

(8mm x 8mm x 0.75mm)

SSEN

DIN19

10 _____________________________________________________________________________________

Gigabit Multimedia Serial Link with Spread

Spectrum and Full-Duplex Control Channel

MAX9259 Pin Description

MAX9259/MAX9260

TQFP TQFN

1–5, 11–17,

21–25, 49, 52–60, 63,

64

6 6 PCLKIN Parallel Clock Input. Latches parallel data inputs and provides the PLL reference clock.

7, 30, 51 7, 26, 44 IOVDD

8, 20, 31,

50, 61

9, 18, 39 — AGND Analog Ground

10, 42 8, 36 AVDD

19, 62 16, 54 DVDD

26 22 SD

27 23 SCK I2S Serial-Clock Input with Internal Pulldown to GND 28 24 WS I2S Word-Select Input with Internal Pulldown to GND

29 25

32 27 MS

33 28 CDS

34 29

35 30 RX/SDA

1–5, 9–15, 17–21, 43, 45–53, 55,

56

— GND Digital and I/O Ground

NAME FUNCTION

Data Input[0:28]. Parallel data inputs. All pins internally pulled down to GND. Selected DIN0– DIN28

AUTOS

PWDN

edge of PCLKIN latches input data. Set BWS = low (24-bit mode) to use DIN0–DIN20

(RGB and SYNC). DIN21–DIN28 are not used in 24-bit mode. Set BWS = high (32-bit

mode) to use DIN0–DIN28 (RGB, SYNC, and two extra inputs).

I/O Supply Voltage. 1.8V to 3.3V logic I/O power supply. Bypass IOVDD to GND with

0.1FF and 0.001FF capacitors as close as possible to the device with the smaller value

capacitor closest to IOVDD.

1.8V Analog Power Supply. Bypass AVDD to AGND with 0.1FF and 0.001FF capacitors as

close as possible to the device with the smaller value capacitor closest to AVDD.

1.8V Digital Power Supply. Bypass DVDD to GND with 0.1FF and 0.001FF capacitors as

close as possible to the device with the smaller value capacitor closest to DVDD.

I2S Serial-Data Input with Internal Pulldown to GND. Disable I2S to use SD as an

additional data input latched on the selected edge of PCLKIN.

Autostart Setting. Active-low power-up mode selection input requires external pulldown or

pullup resistors. Set AUTOS = high to power up the device with no link active. Set AUTOS

= low to have the MAX9259 power up the serial link with autorange detection (see Tables

13 and 14).

Mode Select. Control-link mode-selection input requires external pulldown or pullup

resistors. Set MS = low, to select base mode. Set MS = high to select the bypass mode.

Control-Direction Selection. Control-link-direction selection input requires external

pulldown or pullup resistors. Set CDS = low for FC use on the MAX9259 side of the serial

link. Set CDS = high for FC use on the MAX9260 side of the serial link.

Power-Down. Active-low power-down input requires external pulldown or pullup

resistors.

Receive/Serial Data. UART receive or I2C serial-data input/output with internal 30kI

pullup to IOVDD. In UART mode, RX/SDA is the Rx input of the MAX9259’s UART. In I2C

mode, RX/SDA is the SDA input/output of the MAX9259’s I2C master.

______________________________________________________________________________________ 11

Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel

MAX9259 Pin Description (continued)

TQFP TQFN

36 31 TX/SCL

37 32 SSEN

38 33 LMN1 Line-Fault Monitor Input 1 (see Figure 3 for details)

40, 41

43 37 LMN0 Line-Fault Monitor Input 0 (see Figure 3 for details)

MAX9259/MAX9260

44 38 LFLT

45 39 INT

46 40 DRS

47 41 ES

48 42 BWS

— — EP

34, 35

NAME FUNCTION

Transmit/Serial Clock. UART transmit or I2C serial-clock output with internal 30kI pullup to IOVDD. In UART mode, TX/SCL is the Tx output of the MAX9259’s UART. In I2C mode, TX/SCL is the SCL output of the MAX9259’s I2C master.

Spread-Spectrum Enable. Serial link spread-spectrum enable input requires external pulldown or pullup resistors. The state of SSEN latches upon power-up or when resuming from power-down mode (PWDN = low). Set SSEN = high for Q0.5% spread spectrum on the serial link. Set SSEN = low to use the serial link without spread spectrum.

OUT-, OUT+

Differential CML Output -/+. Differential outputs of the serial link.

Line Fault. Active-low open-drain line-fault output with a 60kI internal pullup resistor. LFLT = low indicates a line fault. LFLT is high impedance when PWDN = low.

Interrupt Output to Indicate Remote Side Requests. INT = low upon power-up and when PWDN = low. A transition on the INT input of the MAX9260 toggles the MAX9259’s INT output.

Data-Rate Select. Data-rate range-selection input requires external pulldown or pullup resistors. Set DRS = high for parallel input data rates of 8.33MHz to 16.66MHz (24-bit mode) or 6.25MHz to 12.5MHz (32-bit mode). Set DRS = low for parallel input data rates of 16.66MHz to 104MHz (24-bit mode) or 12.5MHz to 78MHz (32-bit mode).

Edge Select. PCLKIN trigger edge-selection input requires external pulldown or pullup resistors. Set ES = low to trigger on the rising edge of PCLKIN. Set ES = high to trigger on the falling edge of PCLKIN.

Bus-Width Select. Parallel input bus-width selection input requires external pulldown or pullup resistors. Set BWS = low for 24-bit bus mode. Set BWS = high for 32-bit bus mode.

Exposed Pad. EP internally connected to AGND (TQFP package) or AGND and GND (TQFN package). MUST externally connect EP to the AGND plane to maximize thermal and electrical performance.

12 _____________________________________________________________________________________

Gigabit Multimedia Serial Link with Spread

Spectrum and Full-Duplex Control Channel

MAX9260 Pin Description

PIN NAME FUNCTION

Enable. Active-low parallel output-enable input requires external pulldown or pullup

1

2 BWS

3 INT

4 CDS

5 GPIO0

6 ES

7, 63 AVDD

8 , 9 IN+, IN- Differential CML Input +/-. Differential inputs of the serial link.

10, 64 AGND Analog Ground

11 EQS

12 GPIO1

13 DCS

ENABLE

resistors. Set ENABLE = low to enable PCLKOUT, SD, SCK, WS, and the parallel outputs, DOUT_. Set ENABLE = high to put PCLKOUT, SD, SCK, WS, and DOUT_ to high impedance.

Bus-Width Select. Parallel output bus-width selection input requires external pulldown or pullup resistors. Set BWS = low for 24-bit bus mode. Set BWS = high for 32-bit bus mode.

Interrupt. Interrupt input requires external pulldown or pullup resistors. A transition on the INT input of the MAX9260 toggles the MAX9259’s INT output.

Control-Direction Selection. Control-link-direction selection input requires external pulldown or pullup resistors. Set CDS = low for FC use on the MAX9259 side of the serial link. Set CDS = high for FC use on the MAX9260 side of the serial link.

GPIO0. Open-drain general-purpose input/output with internal 60kI pullup resistors to IOVDD. GPIO0 is high impedance during power-up and when PWDN = low.

Edge Select. PCLKOUT edge-selection input requires external pulldown or pullup resistors. Set ES = low for a rising-edge trigger. Set ES = high for a falling-edge trigger.

3.3V Analog Power Supply. Bypass AVDD to AGND with 0.1µF and 0.001µF capacitors as close as possible to the device with the smallest value capacitor closest to AVDD.

Equalizer Select. Deserializer equalizer-selection input requires external pulldown or pullup resistors. The state of EQS latches upon power-up or rising edge of PWDN. Set EQS = low for 10.7dB equalizer boost (EQTUNE = 1001). Set EQS = high for 5.2dB equalizer boost (EQTUNE = 0100).

GPIO1. Open-drain general-purpose input/output with internal 60kI pullup resistors to IOVDD. GPIO1 is high impedance during power-up and when PWDN = low.

Drive Current Select. Driver current-selection input requires external pulldown or pullup resistors. Set DCS = high for stronger parallel data and clock output drivers. Set DCS = low for normal parallel data and clock drivers (see the MAX9260 DC Electrical Characteristics table).

MAX9259/MAX9260

Mode Select. Control-link mode-selection/autostart mode selection input requires external pulldown or pullup resistors. MS sets the control-link mode when CDS = high

14 MS

15 DVDD

16 DGND Digital Ground

17 RX/SDA

______________________________________________________________________________________ 13

(see the Control-Channel and Register Programming section). Set MS = low to select base mode. Set MS = high to select the bypass mode. MS sets autostart mode when CDS = low (see Tables 13 and 14).

3.3V Digital Power Supply. Bypass DVDD to DGND with 0.1FF and 0.001FF capacitors as close as possible to the device with the smaller value capacitor closest to DVDD.

Receive/Serial Data. UART receive or I2C serial-data input/output with internal 30kI pullup to IOVDD. In UART mode, RX/SDA is the Rx input of the MAX9260’s UART. In I2C mode, RX/SDA is the SDA input/output of the MAX9259’s I2C master.

Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel

MAX9260 Pin Description (continued)

PIN NAME FUNCTION

Transmit/Serial Clock. UART transmit or I2C serial-clock output with internal 30kI

18 TX/SCL

19

20

21, 31, 50, 60 IOGND Input/Output Ground

22 LOCK

PWDN

ERR

MAX9259/MAX9260

23 WS Word Select. I2S word-select output. 24 SCK Serial Clock. I2S serial-clock output

25 SD

26–29, 32–40,

42–49, 52–59

DOUT0–

DOUT27,

DOUT28/MCLK

pullup to IOVDD. In UART mode, TX/SCL is the Tx output of the MAX9259’s UART. In I2C mode, TX/SCL is the SCL output of the MAX9260’s I2C master.

Power-Down. Active-low power-down input requires external pulldown or pullup resistors.

Error. Active-low open-drain video data error output with internal pullup to IOVDD. ERR goes low when the number of decoding errors during normal operation exceed a programmed error threshold or when at least one PRBS error is detected during PRBS test. ERR is high impendence when PWDN = low.

Open-Drain Lock Output with Internal Pullup to IOVDD. LOCK = high indicates PLLs are locked with correct serial-word-boundary alignment. LOCK = low indicates PLLs are not locked or incorrect serial-word-boundary alignment. LOCK remains low when the configuration link is active. LOCK is high impedance when PWDN = low.

Serial Data. I2S serial-data output. Disable I2S to use SD as an additional data output latched on the selected edge of PCLKOUT.

Data Output[0:28]. Parallel data outputs. Output data can be strobed on the selected edge of PCLKOUT. Set BWS = low (24-bit mode) to use DOUT0–DOUT20 (RGB and SYNC). DOUT21–DOUT28 are not used in 24-bit mode and are set to low. Set BWS = high (32-bit mode) to use DOUT0–DOUT28 (RGB, SYNC, and two extra outputs). DOUT28 can be used to output MCLK (see the Additional MCLK Output for Audio Applications section).

1.8V to 3.3V Logic I/O Power Supply. Bypass IOVDD to IOGND with 0.1FF and 0.001FF

30, 51 IOVDD

41 PCLKOUT Parallel Clock Output. Used for DOUT0–DOUT28.

61 SSEN

62 DRS

— EP

14 _____________________________________________________________________________________

capacitors as close as possible to the device with the smaller value capacitor closest to IOVDD.

Spread-Spectrum Enable. Parallel output spread-spectrum enable input requires external pulldown or pullup resistors. The state of SSEN latches upon power-up or when resuming from power-down mode (PWDN = low). Set SSEN = high for Q2% spread spectrum on the parallel outputs. Set SSEN = low to use the parallel outputs without spread spectrum.

Data-Rate Select. Data-rate range-selection input requires external pulldown or pullup resistors. Set DRS = high for parallel input data rates of 8.33MHz to 16.66MHz (24-bit mode) or 6.25MHz to 12.5MHz (32-bit mode). Set DRS = low for parallel input data rates of 16.66MHz to 104MHz (24-bit mode) or 12.5MHz to 78MHz (32-bit mode).

Exposed Pad. EP internally connected to AGND. MUST externally connect EP to the AGND plane to maximize thermal and electrical performance.

Gigabit Multimedia Serial Link with Spread

Spectrum and Full-Duplex Control Channel

Functional Diagram

LFLT

MAX9259/MAX9260

PCLKIN

DIN[N:0]

WS, SD, SCK

TX/SCL

RX/SDA

PCLKOUT

DOUT[N:0]

AUDIO

FIFO

PRBS

GEN

FILTER

PLL

8B/10B

ENCODE

PARITY

UART/I2C

SPREAD

PLL

8B/10B

DECODE

PARITY

CLKDIV

MAX9259

SERIALIZER

CLKDIV

SPREAD

PLL

P S

CDR

PLL

P S

LINE-

FAULT

CML

TERM

REV CH

Rx

CML

DET

Tx

EQ

Rx

LMN0

LMN1

OUT+

OUT-

STP CABLE

= 50)

(Z

0

WS, SD, SCK

TX/SCL

RX/SDA

AUDIO

FIFO

PRBS

CHECK

UART/I2C

TERM

MAX9260

REV CH

Tx

DESERIALIZER

IN-

IN+

______________________________________________________________________________________ 15

Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel

/2

R

V

= |V

L

OD

V

GND

OS

V

OS(-)

V

OS(+)

R

- V

/2

L

((OUT+) + (OUT-))/2

|

OS(-)

OUT-

OUT+

V

OS(-)

OUT+

OUT-

DV

OS

MAX9259/MAX9260

V

OD(-)

(OUT+) - (OUT-)

Figure 1. MAX9259 Serial Output Parameters

OUT+

V

OS

OUT-

Figure 2. Output Waveforms at OUT+ and OUT-

SERIAL-BIT

TIME

VOD(+)

DVOD = |V

OD(+)

- V

OD(-)

V

|

OD(P)VOD(D)

V

OD(-)

V

= 0V

OD

16 _____________________________________________________________________________________