Maxim MAX9257, MAX9258GCM+ Datasheet

General Description
The MAX9257 serializer pairs with the MAX9258 deseri­alizer to form a complete digital video serial link. The MAX9257/MAX9258 feature programmable parallel data width, parallel clock frequency range, spread spectrum, and preemphasis. An integrated control channel trans­fers data bidirectionally at power-up during video blank­ing over the same differential pair used for video data. This feature eliminates the need for external CAN or LIN interface for diagnostics or programming. The clock is recovered from input serial data at MAX9258, hence eliminating the need for an external reference clock.
The MAX9257 serializes 10, 12, 14, 16, and 18 bits with the addition of two encoding bits for AC-coupling. The MAX9258 deserializer links with the MAX9257 to deseri­alize a maximum of 20 (data + encoding) bits per pixel/parallel clock period for a maximum serial-data rate of 840Mbps. The word length can be adjusted to accommodate a higher pixel/parallel clock frequency. The pixel clock can vary from 5MHz to 70MHz, depend­ing on the serial-word length. Enabling parity adds two parity bits to the serial word. The encoding bits reduce ISI and allow AC-coupling.
The MAX9258 receives programming instructions from the electronic control unit (ECU) during the control channel and transmits to the MAX9257 over the serial video link. The instructions can program or update the MAX9257, MAX9258, or an external peripheral device, such as a camera. The MAX9257 communicates with the peripheral device with I2C or UART.
The MAX9257/MAX9258 operate from a +3.3V core supply and feature separate supplies for interfacing to +1.8V to +3.3V logic levels. These devices are avail­able in 40-lead TQFN or 48-pin LQFP packages. These devices are specified over the -40°C to +105°C temper­ature range.
Applications
Automotive Cameras
Industrial Cameras
Navigation Systems Display
In-Vehicle Entertainment Systems
Features
10/12/14/16/18-Bit Programmable Parallel Data
Width
MAX9258 Does Not Require Reference Clock
Parity Protection for Video and Control Channels
Programmable Spread Spectrum
Programmable Rising or Falling Edge for HSYNC,
VSYNC, and Clock
Up to 10 Remotely Programmable GPIO on
MAX9257
Automatic Resynchronization in Case of Loss of
Lock
MAX9257 Parallel Clock Jitter Filter PLL with
Bypass
DC-Balanced Coding Allows AC-Coupling
5 Levels of Preemphasis for Up to 20m STP Cable
Drive
Integrity Test Using On-Chip Programmable
PRBS Generator and Checker
LVDS I/O Meet ISO10605 ESD Protection (±10kV
Contact and ±30kV Air Discharge)
LVDS I/O Meet IEC61000-4-2 ESD Protection
(±8kV Contact and ±20kV Air Discharge)
LVDS I/O Meet ±200V Machine Model ESD
Protection
-40°C to +105°C Operating Temperature Range
Space-Saving, 40-Pin TQFN (5mm x 5mm) with
Exposed Pad or 48-Pin LQFP Packages
+3.3V Core Supply
MAX9257/MAX9258
Fully Programmable Serializer/Deserializer
with UART/I2C Control Channel
________________________________________________________________
Maxim Integrated Products
1
19-1044; Rev 0; 6/08
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
EVALUATION KIT
AVAILABLE
Ordering Information
PART TEMP RANGE
PIN­PACKAGE
PKG
CODE
MAX9257GTL+ -40°C to +105°C 40 TQFN-EP* T4055+1
MAX9257GCM+ -40°C to +105°C 48 LQFP C48+3
MAX9258GCM+ -40°C to +105°C 48 LQFP C48+3
+
Denotes a lead-free package.
*
EP = Exposed pad.
Typical Application Circuit and Pin Configurations appear at end of data sheet.
MAX9257/MAX9258
2 _______________________________________________________________________________________
Fully Programmable Serializer/Deserializer with UART/I2C Control Channel
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
VCC_ to GND .........................................................-0.5V to +4.0V
Any Ground to Any Ground...................................-0.5V to +0.5V
SDI+, SDI-, SDO+, SDO- to GND..........................-0.5V to +4.0V
SDO+, SDO- Short Circuit to GND or V
CCLVDS
.........Continuous
DIN[0:15], GPIO[0:9], PCLK_IN, HSYNC_IN, VSYNC_IN,
SCL/TX, SDA/RX, REM to GND............-0.5V to (V
CCIO
+ 0.5V)
DOUT[0:15], PCLK_OUT, HSYNC_OUT, VSYNC_OUT, RX,
LOCK, TX, PD, ERROR, to GND .......-0.5V to (V
CCOUT
+ 0.5V)
Continuous Power Dissipation (T
A
= +70°C)
40-Lead TQFN
Multilayer PCB (derate 35.7mW/°C above +70°C) .....2857mW
48-Lead LQFP
Multilayer PCB (derate 21.7mW/°C above +70°C) .....1739mW
Junction-to-Case Thermal Resistance (θ
JC
) (Note 1)
40-Lead TQFN .............................................................1.7°C/W
48-Lead LQFP...............................................................10°C/W
Junction-to-Ambient Thermal Resistance (θ
JA
) (Note 1)
40-Lead TQFN ..............................................................28°C/W
48-Lead LQFP...............................................................46°C/W
ESD Protection
Human Body Model (R
D
= 1.5kΩ, CS= 100pF)
All Pins to GND ..............................................................±3kV
IEC 61000-4-2 (R
D
= 330Ω, CS= 150pF)
Contact Discharge
(SDI+, SDI-, SDO+, SDO-) to GND................................±8kV
Air Discharge
(SDI+, SDI-, SDO+, SDO-) to GND..............................±20kV
ISO 10605 (R
D
= 2kΩ, CS= 330pF)
Contact Discharge
(SDI+, SDI-, SDO+, SDO-) to GND..............................±10kV
Air Discharge
(SDI+, SDI-, SDO+, SDO-) to GND..............................±30kV
Machine Model (R
D
= 0Ω, CS= 200pF)
All Pins to GND ............................................................±200V
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
MAX9257 DC ELECTRICAL CHARACTERISTICS
(V
CC_
= +3.0V to +3.6V, RL= 50Ω ±1%, TA= -40°C to +105°C, unless otherwise noted. Typical values are at V
CC_
= +3.3V,
T
A
= +25°C.) (Notes 2, 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SINGLE-ENDED INPUTS
V
CCIO
= +1.71V to +3V
0.65 x V
CCIO
V
CCIO
+
0.3
V
CCIO
= +3V to +3.6V 2
V
CCIO
+
0.3
High-Level Input Voltage V
IH
REM input 2
V
CC
+
0.3
V
V
CCIO
= +1.71V to +3V 0
0.3 x
V
CCIO
V
CCIO
= +3V to +3.6V 0 0.8
Low-Level Input Voltage V
IL
REM input 0 0.8
V
VIN = 0 to V
CCIO
V
CCIO
= +1.71V to +3.6V
-20 +20
Input Current I
IN
VIN = 0 to V
CC,
REM input -20 +20
µA
Input Clamp Voltage V
CL
ICL = -18mA -1.5 V
SINGLE-ENDED OUTPUTS
IOH = -100µA
V
CCIO
-
0.1
High-Level Output Voltage V
OH
IOH = -2mA
V
CCIO
-
0.35
V
Note 1: Package thermal resistances were obtained using the method described in JDEC specification JESD51-7, using a 4-layer
board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial
.
MAX9257/MAX9258
_______________________________________________________________________________________ 3
Fully Programmable Serializer/Deserializer
with UART/I2C Control Channel
MAX9257 DC ELECTRICAL CHARACTERISTICS (continued)
(V
CC_
= +3.0V to +3.6V, RL= 50Ω ±1%, TA= -40°C to +105°C, unless otherwise noted. Typical values are at V
CC_
= +3.3V,
T
A
= +25°C.) (Notes 2, 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
I
OL
= 100µA 0.1
Low-Level Output Voltage V
OL
I
OL
= 2mA 0.3
V
Shorted to GND -44 -10
Output Short-Circuit Current I
OS
Shorted to V
CC_
10 44
mA
I2C/UART I/O
Input Leakage Current I
ILKG
VI = V
CC
-1 +1 µA
High-Level Input Voltage SDA/RX V
IH2
0.7 x V
CC
V
Low-Level Input Voltage SDA/RX V
IL2
0.3 x V
CC
V
Low-Level Output Voltage SCL, SDA
V
OL2
R
PULLUP
= 1.6k
Ω
0.4 V
LVDS OUTPUTS (SDO+, SDO-)
Differential Output Voltage V
OD
250 350 460 mV
Change in VOD Between Complimentary Output States
Δ
V
OD
20 mV
Common-Mode Voltage V
OS
1.050 1.25 1.375 V
Change in VOS Between Complimentary Output States
Δ
V
OS
Preemphasis off (Figure 1)
20 mV
Output Short-Circuit Current I
OS
V
SDO+
or V
SDO-
= 0 or 3.6V -15 +15 mA
Magnitude of Differential Output Short-Circuit Current
I
OSD
V
OD
= 0 15 mA
CONTROL CHANNEL TRANSCEIVER
Differential Output Voltage V
OD
250 350 460 mV
V
HYST+
Differential low-to-high threshold 25 90 135
Input Hysteresis (Figure 2)
V
HYST-
Differential high-to-low threshold -25 -90 -135
mV
MAX9257/MAX9258
4 _______________________________________________________________________________________
Fully Programmable Serializer/Deserializer with UART/I2C Control Channel
MAX9257 DC ELECTRICAL CHARACTERISTICS (continued)
(V
CC_
= +3.0V to +3.6V, RL= 50Ω ±1%, TA= -40°C to +105°C, unless otherwise noted. Typical values are at V
CC_
= +3.3V,
T
A
= +25°C.) (Notes 2, 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER SUPPLY
±2% spread, preemphasis off, PRATE = 60MHz, SRATE = 840Mbps
104 126
No spread, preemphasis off, PRATE = 60MHz, SRATE = 840Mbps
99 121
N o sp r ead , p r eem p hasi s = 20%, P RATE = 60M H z, S RATE = 840M b p s
99 120
N o sp r ead , p r eem p hasi s = 60%, P RATE = 60M H z, S RATE = 840M b p s
108 127
N o sp r ead , p r eem p hasi s = 100%, P RATE = 60M H z, S RATE = 840M b p s
110 129
±2% spread, preemphasis off, PRATE = 28.57MHz, SRATE = 400Mbps
78 96
No spread, preemphasis off, PRATE = 28.57MHz, SRATE = 400Mbps
77 94
No spread, preemphasis = 100%, PRATE = 28.57MHz, SRATE = 400Mbps
86 105
±2% spread, preemphasis off, PRATE = 14.29MHz, SRATE = 200Mbps
55 68
No spread, preemphasis off, PRATE = 14.29MHz, SRATE = 200Mbps
54 67
No spread, preemphasis = 100%, PRATE = 14.29MHz, SRATE = 200Mbps
59 73
±2% spread, preemphasis off, PRATE = 7.14MHz, SRATE = 100Mbps
44 55
No spread, preemphasis off, PRATE = 7.14MHz, SRATE = 100Mbps
43 54
N o sp r ead , p r eem p hasi s = 100%, P RATE = 7.14M H z, S RATE = 100M b p s
46 57
±2% spread, preemphasis off, PRATE = 5MHz, SRATE = 70Mbps
34 43
No spread, preemphasis off, PRATE = 5MHz, SRATE = 70Mbps
34 42
Worst-Case Supply Current (Figure 3) C
L
= 8pF, 12 bits
I
CCW
No spread, preemphasis = 100%, PRATE = 5MHz, SRATE = 70Mbps
36 45
mA
Sleep Mode Supply Current I
CCS
Sleep mode 92 µA
MAX9257/MAX9258
_______________________________________________________________________________________ 5
Fully Programmable Serializer/Deserializer
with UART/I2C Control Channel
MAX9257 AC ELECTRICAL CHARACTERISTICS
(V
CC_
= +3.0V to +3.6V, RL= 50Ω ±1%, TA= -40°C to +105°C, unless otherwise noted. Typical values are at V
CC_
= +3.3V,
T
A
= +25°C.) (Notes 5, 9)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
PCLK_IN TIMING REQUIREMENTS
Clock Period t
T
14.28 200.00 ns
Clock Frequency f
CLK
1/t
T
5 70 MHz
Clock Duty Cycle DC t
HIGH/tT
or t
LOW
/t
T
35 50 65 %
Clock Transition Time tR, t
F
(Figure 7) 4 ns
SWITCHING CHARACTERISTICS
LVDS Output Rise Time t
R
20% to 80% (Figure 4) 315 370 ps
LVDS Output Fall Time t
F
20% to 80% (Figure 4) 315 370 ps
t
R1A , tF1A
642 970 1390
t
R2 , tF2
810 1140 1420
Control Transceiver Transition Time
t
R1B , tF1B
20% to 80% (Figure 16)
290 386 490
ps
Input Setup Time t
S
(Figure 5) 0 ns
Input Hold Time t
H
(Figure 5) 3 ns
t
PSD1
Spread off (Figure 6)
(4.55 x t
T) +
11
Parallel-to-Serial Delay
t
PSD2
±4% spread
( 36.55 x t
T) +
11
ns
PLL Lock Time t
LOCK
Combined FPLL and SPLL; PCLK_IN stable
32,768 x
t
T
ns
Random Jitter t
RJ
420MHz LVDS output, spread off, FPLL = bypassed
12
ps
(RMS)
Deterministic Jitter t
DJ
2
18
- 1 PRBS, SRATE = 840Mbps, 18 bits,
no spread
142 ps (p-p)
SCL/TX, SDA/RX
R
PULLUP
= 10k
Ω
400
Rise Time t
RS
0.3 x VCC to 0.7 x V
CC
, CL = 30pF
R
PULLUP
= 1.6k
Ω
60
ns
Fall Time t
FS
0.7 x VCC to 0.3 x V
CC, CL
= 30pF 40 ns
95kbps to 400kbps 100
400kbps to 1000kbps 50
1000kbps to 4250kbps 10
Pulse Width of Spike Suppressed in SDA
t
SPK
DC to 10Mbps (bypass mode) 10
ns
400kbps 100
Data Setup Time t
SETUP
4.25Mbps, CL = 10pF 60
ns
400kbps 100
Data Hold Time t
HOLD
4.25Mbps, CL = 10pF 0
ns
I2C TIMING (Note 8)
Maximum SCL Clock Frequency f
SCL
4.25 MHz
Minimum SCL Clock Frequency f
SCL
95 kHz
Start Condition Hold Time t
HD:STA
(Figure 30) 0.6 µs
MAX9257/MAX9258
6 _______________________________________________________________________________________
Fully Programmable Serializer/Deserializer with UART/I2C Control Channel
MAX9257 AC ELECTRICAL CHARACTERISTICS (continued)
(V
CC_
= +3.0V to +3.6V, RL= 50Ω ±1%, TA= -40°C to +105°C, unless otherwise noted. Typical values are at V
CC_
= +3.3V,
T
A
= +25°C.) (Notes 5, 9)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Low Period of SCL Clock t
LOW
(Figure 30) 1.1 µs
High Period of SCL Clock t
HIGH
(Figure 30) 0.6 µs
Repeated START Condition Setup Time
t
SU:STA
(Figure 30) 0.5 µs
Data Hold Time t
HD:DAT
(Figure 30) 0 0.9 µs
Data Setup Time t
SU:DAT
(Figure 30) 100 ns
Setup Time for STOP Condition t
SU:STO
(Figure 30) 0.5 µs
Bus Free Time t
BUF
(Figure 30) 1.1 µs
MAX9258 DC ELECTRICAL CHARACTERISTICS
(V
CC_
= +3.0V to +3.6V, RL= 50Ω ±1%, differential input voltage |VID| = 0.05V to 1.2V, input common-mode voltage VCM= |VID/2| to
V
CC
- |VID/2|, TA= -40°C to +105°C, unless otherwise noted. Typical values are at V
CC_
= +3.3V, |VID| = 0.2V, VCM= 1.2V,
T
A
= +25°C.) (Notes 2, 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SINGLE-ENDED INPUTS
High-Level Input Voltage V
IH
2.0 V
CC
V
Low-Level Input Voltage V
IL
00.8V
TXIN -60 +60
Input Current I
IN
VIN = 0 to V
CC
PD -20 +20
µA
Input Clamp Voltage V
CL
ICL = -18mA -1.5 V
SINGLE-ENDED OUTPUTS
IOH = -100µA
V
CCOUT
-
0.1
High-Level Output Voltage V
OH
IOH = -2mA
V
CCOUT
-
0.35
V
IOL = 100µA 0.1
Low-Level Output Voltage V
OL
IOL = 2mA 0.3
V
High-Impedance Output Current I
OZ
PD = low, VO = 0 to V
CCOUT
-1 +1 µA
VO = 0V (Note 4) -16 -65
Output Short-Circuit Current I
OS
PCLK_OUT, VO = 0V -22 -80
mA
OPEN-DRAIN OUTPUTS
Output Low Voltage V
OL
V
CCOUT
= +3V, IOL = 6.4mA 0.55 V
Output Low Voltage V
OL
V
CCOUT
= +1.71V, IOL = 1.95mA 0.3 V
Leakage Current I
LEAK
VO = 0 or V
CC
A
LVDS INPUTS (SDI+, SDI-)
Differential Input High Threshold V
TH
50 mV
Differential Input Low Threshold V
TL
-50 mV
Input Current I
IN+, IIN-
-60 +60 µA
Power-Off Input Current I
INO+, IINO-VCC_
= 0 or open -70 +70 µA
CONTROL CHANNEL TRANSCEIVER
Differential Output Voltage V
OD
250 460 mV
MAX9257/MAX9258
_______________________________________________________________________________________ 7
Fully Programmable Serializer/Deserializer
with UART/I2C Control Channel
MAX9258 DC ELECTRICAL CHARACTERISTICS (continued)
(V
CC_
= +3.0V to +3.6V, RL= 50Ω ±1%, differential input voltage |VID| = 0.05V to 1.2V, input common-mode voltage VCM= |VID/2| to
V
CC
- |VID/2|, TA= -40°C to +105°C, unless otherwise noted. Typical values are at V
CC_
= +3.3V, |VID| = 0.2V, VCM= 1.2V,
T
A
= +25°C.) (Notes 2, 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
V
HYST+
Differential low-to-high threshold 25 90 135
Input Hysteresis (Figure 2)
V
HYST-
Differential high-to-low threshold -25 -90 -135
mV
POWER SUPPLY
±4% spread, PRATE = 60MHz, SRATE = 840Mbps
85 128
Spread off, PRATE = 60MHz, SRATE = 840Mbps
71 115
±4% spread, PRATE = 28.57MHz, SRATE = 400Mbps
67 102
Spread off, PRATE = 28.57MHz, SRATE = 400Mbps
57 84
±4% spread, PRATE = 14.29MHz, SRATE = 200Mbps
55 82
Spread off, PRATE = 14.29MHz, SRATE = 200Mbps
46 67
±4% spread, PRATE = 5MHz, SRATE = 70Mbps
42 57
Worst-Case Supply Current C
L
= 8pF, 12 bits
(Figure 8)
I
CCW
Spread off, PRATE = 5MHz, SRATE = 70Mbps
34 49
mA
Power-Down Supply Current I
CCZ
PD = low 10 50 µA
MAX9258 AC ELECTRICAL CHARACTERISTICS
V
CC_
= +3.0V to +3.6V, RL= 50Ω ±1%, CL= 8pF, differential input voltage |VID| = 0.1V to 1.2V, input common-mode voltage
V
CM
= |VID/2| to VCC- |VID/2|, TA= -40°C to +105°C, unless otherwise noted. Typical values are at V
CC_
= +3.3V, |VID| = 0.2V, VCM=
1.2V, T
A
= +25°C. (Notes 5, 6, and 7)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SWITCHING CHARACTERISTICS
Output Transition Time t
R, tF
(Figure 9) 0.7 2.2 ns
Output Transition Time, PCLK_OUT
t
R, tF
(Figure 9) 0.5 1.5 ns
Output Transition Time t
R, tF
V
CCOUT
= 1.71V (Figure 9) 1.0 2.8 ns
Output Transition Time, PCLK_OUT
t
R, tF
V
CCOUT
= 1.71V (Figure 9) 0.7 2.2 ns
Control Channel Transition Time
t
R1A, tF1A,
t
R1B, tF1B
(Figure 16) 0.5 1.2 ns
Control Channel Transition Time t
R2, tF2
(Figure 16) 0.6 1.3 ns
PCLK_OUT High Time t
HIGH
(Figure 10)
0.4 x t
T
0.6 x t
T
ns
PCLK_OUT Low Time t
LOW
(Figure 10)
0.4 x t
T
0.6 x t
T
ns
MAX9257 SUPPLY CURRENT
vs. FREQUENCY
MAX9257/58 toc01
PCLK FREQUENCY (MHz)
SUPPLY CURRENT (mA)
20 4025 3515 3010
20
40
60
80
100
120
0
545
PRBS PATTERN 18-BIT
100% PREEMPHASIS
NO PREEMPHASIS
MAX9257 SUPPLY CURRENT
vs. FREQUENCY
MAX9257/58 toc02
PCLK FREQUENCY (MHz)
SUPPLY CURRENT (mA)
5515 45
60
40
20
80
100
120
140
0
57535 6525
PRBS PATTERN 10-BIT
100% PREEMPHASIS
NO PREEMPHASIS
MAX9258 SUPPLY CURRENT
vs. FREQUENCY
MAX9257/58 toc03
PCLK FREQUENCY (MHz)
SUPPLY CURRENT (mA)
4010 3515
40
20
60
80
100
120
0
5452520 30
PRBS PATTERN 18-BIT
4% SPREAD
NO SPREAD
Typical Operating Characteristics
(V
CC_
= +3.3V, RL= 50Ω, CL= 8pF, TA= +25°C, unless otherwise noted.)
MAX9257/MAX9258
8 _______________________________________________________________________________________
Fully Programmable Serializer/Deserializer with UART/I2C Control Channel
MAX9258 AC ELECTRICAL CHARACTERISTICS (continued)
V
CC_
= +3.0V to +3.6V, RL= 50Ω ±1%, CL= 8pF, differential input voltage |VID| = 0.1V to 1.2V, input common-mode voltage
V
CM
= |VID/2| to VCC- |VID/2|, TA= -40°C to +105°C, unless otherwise noted. Typical values are at V
CC_
= +3.3V, |VID| = 0.2V, VCM=
1.2V, T
A
= +25°C. (Notes 5, 6, and 7)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Data Valid Before PCLK_ OUT t
DVB
(Figure 11)
0.35 x t
T
ns
Data Valid After PCLK_OUT t
DVA
(Figure 11)
0.35 x t
T
ns
t
SPD1
Spread off (Figure 14) 8t
T
Serial-to-Parallel Delay
t
SPD2
±4% spread 40t
T
ns
Power-Up Delay t
PUD
(Figure 12) 100 ns
Power-Down to High Impedance t
PDD
(Figure 13) 100 ns
Jitter Tolerance t
JT
Each half of the UI, 12 bit, SRATE = 840Mbps, PRBS pattern (Figure 15)
No spread 0.25 0.30 UI
Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except V
TH
and VTL.
Note 3: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production
tested at T
A
= +105°C.
Note 4: One output at a time. Note 5: AC parameters are guaranteed by design and characterization, and are not production tested. Note 6: C
L
includes probe and test jig capacitance.
Note 7: t
T
is the period of the PCLK_OUT.
Note 8: For high-speed mode timing, see the
Detailed Description
section.
Note 9: I
2
C timing parameters are specified for fast-mode I2C. Max data rate = 400kbps.
MAX9257/MAX9258
_______________________________________________________________________________________ 9
MAX9258 SUPPLY CURRENT
vs. FREQUENCY
MAX9257/58 toc04
PCLK FREQUENCY (MHz)
SUPPLY CURRENT (mA)
4010 3515
40
20
60
80
100
120
0
5452520 30
PRBS PATTERN 10-BIT
4% SPREAD
NO SPREAD
SERIAL LINK SWITCHING PATTERN WITHOUT
PREEMPHASIS (BIT RATE = 840MHz, 2m STP CABLE)
MAX9257/58 toc05
MAX9257/58 toc06
SERIAL LINK SWITCHING PATTERN WITH
PREEMPHASIS (BIT RATE = 840MHz, 2m STP CABLE)
(PREEMPHASIS = 100%)
MAX9257 OUTPUT POWER
SPECTRUM vs. PCLK FREQUENCY
MAX9257/58 toc07
PCLK FREQUENCY (MHz)
OUTPUT POWER SPECTRUM (dBm)
2119
-20
-30
-10
0
-60
-70
-50
-40
10
20
-80 18 2220
10kHz BW
4% SPREAD
2% SPREAD
NO SPREAD
MAX9257 OUTPUT POWER
SPECTRUM vs. PCLK FREQUENCY
MAX9257/58 toc08
PCLK FREQUENCY (MHz)
OUTPUT POWER SPECTRUM (dBm)
4440
-20
0
-60
-40
20
-80 38 4642
10kHz BW
1.5% SPREAD
2% SPREAD
NO SPREAD
MAX9258 OUTPUT POWER
SPECTRUM vs. PCLK FREQUENCY
MAX9257/58 toc09
PCLK FREQUENCY (MHz)
OUTPUT POWER SPECTRUM (dBm)
4440
-20
0
-60
-40
20
-80 38 4642
10kHz BW
4% SPREAD
2% SPREAD
NO SPREAD
BIT ERROR RATE (< 10-9) vs.
CABLE LENGTH
MAX9257/58 toc10
CABLE LENGTH (m)
SERIAL-DATA RATE (Mbps)
700
800
500
600
900
400
0862 4 10 12 14 16 18 20
BER CAN BE AS LOW AS 10
-12
FOR
CABLE LENGTHS LESS THAN 10m.
NO SPREAD STP CABLE
NO PREEMPHASIS
100% PREEMPHASIS
BIT ERROR RATE (< 10-9) vs.
CABLE LENGTH
MAX9257/58 toc11
CABLE LENGTH (m)
SERIAL-DATA RATE (Mbps)
700
800
500
600
900
400
0862 4 10 12 14 16 18 20
BER CAN BE AS LOW AS 10
-12
FOR
CABLE LENGTHS LESS THAN 10m.
2% SPREAD ON MAX9257, STP CABLE
NO PREEMPHASIS
100% PREEMPHASIS
Typical Operating Characteristics (continued)
(V
CC_
= +3.3V, RL= 50Ω, CL= 8pF, TA= +25°C, unless otherwise noted.)
Fully Programmable Serializer/Deserializer
with UART/I2C Control Channel
MAX9257/MAX9258
10 ______________________________________________________________________________________
Fully Programmable Serializer/Deserializer with UART/I2C Control Channel
MAX9257 Pin Description
PIN
TQFN LQFP
NAME FUNCTION
1, 18 2, 21 V
CCIO
Single-Ended Input/Output Buffer Supply Voltage. Bypass V
CCIO
to GND with 0.1µF and
0.001µF capacitors in parallel as close as possible to the device with the smallest value capacitor closest to V
CCIO
.
2, 11,
19, 34
3, 14,
22, 41
GND Digital Supply Ground
3–8 4–9
DIN[9:14]/ GPIO[1:6]
Data Input/General Purpose Input/Output. When a serial-data word is less than 18 bits word length, DIN_ not programmed as data inputs becomes GPIO (Table 22). DIN[9:14] are internally pulled down to ground.
9 10 GND
FPLL
Filter PLL Ground
10 11 V
CCFPLL
Filter PLL Supply Voltage. Bypass V
CCFPLL
to GND
FPLL
with 0.1µF and 0.001µF capacitors in parallel as close as possible to the device with the smallest value capacitor closest to V
CCFPLL
.
12 15 DIN15/GPIO7
Data Input/General Purpose Input/Output. When a serial-data word is less than 18 bits word length, DIN_ not programmed as data input becomes GPIO (Table 22). DIN15 is internally pulled down to ground.
13 16 HSYNC_IN Horizontal SYNC Input. HSYNC_IN is internally pulled down to ground.
14 17 VSYNC_IN Vertical SYNC Input. VSYNC_IN is internally pulled down to ground.
15 18 PCLK_IN
Parallel Clock Input. PCLK_IN latches data and sync inputs and provides the PLL reference clock. PCLK_IN is internally pulled down to ground.
16 19 SCL/TX
O p en- D r ai n C ontr ol C hannel Outp ut. S C L/TX b ecom es S C L outp ut w hen U ART- to- I
2
C i s
acti ve. S C L/TX b ecom es TX outp ut w hen U ART- to- I
2
C i s b yp assed . E xter nal l y p ul l up to V
C C
.
17 20 SDA/RX
Open-Drain Control Channel Input/Output. SDA/RX becomes bidirectional SDA when UART-to-I2C is active. SDA/RX becomes RX input when UART-to-I2C is bypassed. SDA output requires a pullup to V
CC
.
20, 33 23, 40 V
CC
Digital Supply Voltage. Bypass VCC to ground with 0.1µF and 0.001µF capacitors in p ar al l el as cl ose as p ossi b l e to the d evi ce w i th the sm al l est val ue cap aci tor cl osest to V
C C
.
21 26 GPIO8 General Purpose Input/Output
22 27 GPIO9 General Purpose Input/Output
23 28 V
CCSPLL
Spread PLL Supply Voltage. Bypass V
CCSPLL
to GND
SPLL
with 0.1µF and 0.001µF capacitors in parallel as close as possible to the device with the smallest value capacitor closest to V
CCSPLL
.
24 29 GND
SPLL
SPLL Ground
25 30 GND
LVDS
LVDS Ground
26 31 SDO- Serial LVDS Inverting Output
27 32 SDO+ Serial LVDS Noninverting Output
28 33 V
CCLVDS
LVDS Supply Voltage. Bypass V
CCLVDS
to GND
LVDS
with 0.1µF and 0.001µF capacitors in parallel as close as possible to the device with the smallest value capacitor closest to V
CCLVDS
.
MAX9257/MAX9258
______________________________________________________________________________________ 11
Fully Programmable Serializer/Deserializer
with UART/I2C Control Channel
MAX9257 Pin Description (continued)
PIN
TQFN LQFP
NAME FUNCTION
29 34 REM
Remote Power-Up/Power-Down Select Input. Connect REM to ground for power-up to follow VCC. Connect REM high to VCC through 10kΩ resistor for remote power-up. REM is internally pulled down to GND.
30, 31, 32,
35–39
35, 38,
39, 42–46
DIN[0:7] Data Inputs. DIN[0:7] are internally pulled down to ground.
40 47 DIN8/GPIO0
Data Input/General Purpose Input/Output. When a serial-data word is less than 18 bits word length, DIN_ not programmed as data input becomes GPIO (Table 22). DIN8 is internally pulled down to ground.
1, 12, 13
24, 25,
36, 37, 48
N.C. No Connection. Not internally connected.
EP Exposed Pad for Thin QFN Package Only. Connect EP to ground.
MAX9258 Pin Description
PIN NAME FUNCTION
1, 12, 13, 24,
25, 36,
37
N.C. No Connection. Not internally connected.
2V
CC
Digital Supply Voltage. Bypass VCC to GND with 0.1µF and 0.001µF capacitors in parallel as close as possible to the device with the smallest value capacitor closest V
CC
.
3, 14 GND Digital Supply Ground
4 PD
LVCMOS/LVTTL Power-Down Input. Drive PD high to power up the device and enable all outputs. Drive PD low to put all outputs in high impedance and reduce supply current. PD is internally pulled down to ground.
5V
CCLVDS
LVDS Supply Voltage. Bypass V
CCLVDS
to GND
LVDS
with 0.1µF and 0.001µF capacitors in parallel
as close as possible to the device with the smallest value capacitor closest to V
CCLVDS
.
6 SDI- Serial LVDS Inverting Input
7 SDI+ Serial LVDS Noninverting Input
8 GND
LVDS
LVDS Supply Ground
9 GND
PLL
PLL Supply Ground
10 V
CCPLL
PLL Supply Voltage. Bypass V
CCPLL
to GND
PLL
with 0.1µF and 0.001µF capacitors in parallel as
close to the device as possible with the smallest value capacitor closest to V
CCPLL
.
11 ERROR
Active-Low, Open-Drain Error Output. ERROR asserts low to indicate a data transfer error was detected (parity, PRBS, or UART control channel error). ERROR is high to indicate no error detected. ERROR resets when the error registers are read for parity, control channel errors, and when PRBS enable bit is reset for PRBS errors. Pull up to V
CCOUT
with a 1kΩ resistor.
15 RX LVCMOS/LVTTL Control Channel UART Output
MAX9257/MAX9258
12 ______________________________________________________________________________________
Fully Programmable Serializer/Deserializer with UART/I2C Control Channel
MAX9258 Pin Description (continued)
PIN NAME FUNCTION
16 TX LVCMOS/LVTTL Control Channel UART Input. TX is internally pulled up to V
CCOUT
.
17 LOCK
Open-Drain Lock Output. LOCK asserts high to indicate PLLs are locked with correct serial-word boundary alignment. LOCK asserts low to indicate PLLs are not locked or incorrect serial-word boundary alignment was detected. Pull up to V
CCOUT
with a 1kΩ resistor.
18 PCLK_OUT LVCMOS/LVTTL Recovered Clock Output
19 VSYNC_OUT LVCMOS/LVTTL Vertical SYNC Output
20 HSYNC_OUT LVCMOS/LVTTL Horizontal SYNC Output
21, 28–35,
40–46
DOUT[15:0] LVCMOS/LVTTL Data Outputs
22, 39 V
CCOUT
Output Supply Voltage. V
CCOUT
is the supply for all output buffers. Bypass V
CCOUT
to GND
OUT
with
0.1µF and 0.001µF capacitors in parallel as close as possible to the device with the smallest value capacitor closest to V
CCOUT
.
23, 38, 48 GND
OUT
Output Supply Ground
26 V
CCSPLL
Spread-Spectrum PLL Supply Voltage. Bypass V
CCSPLL
to GND
SPLL
with 0.1µF and 0.001µF capacitors in parallel as close as possible to the device with the smallest value capacitor closest to V
CCSPLL
.
27 GND
SPLL
SPLL Ground
47 CCEN
LVCMOS/LVTTL Control Channel Enabled Output. CCEN asserts high to indicate that control channel is enabled.
MAX9257/MAX9258
______________________________________________________________________________________ 13
Fully Programmable Serializer/Deserializer
with UART/I2C Control Channel
SDO-
V
OD
V
OS
GND
R
L
/2
R
L
/2
SDO+
SDO-
SDO+
(SDO+) - (SDO-)
V
OS
(-) VOS(+)
((SDO+) + (SDO-))/2
V
OS
(-)
V
OD
(-)
V
OD
(-)
V
OD
= 0V
ΔV
OS
= |VOS(+) - VOS(-)|
ΔVOD = |VOD(+) - VOD(-)|
VOD(+)
Figure 1. MAX9257 LVDS DC Output Parameters
VID = 0V
+V
ID
-V
ID
V
OUT
V
HYST+
V
HYST-
Figure 2. Input Hysteresis
PCLK_IN
NOTE: PCLK_IN PROGRAMMED FOR RISING LATCH EDGE.
DIN
Figure 3. MAX9257 Worst-Case Pattern Input
MAX9257/MAX9258
14 ______________________________________________________________________________________
Fully Programmable Serializer/Deserializer with UART/I2C Control Channel
SDO-
C
L
C
L
R
L
SDO+
t
FALL
20%20%
(SDO+) - (SDO-)
80%
80%
t
RISE
Figure 4. MAX9257 LVDS Control Channel Output Load and Output Rise/Fall Times
V
IHMIN
V
IHMIN
V
IHMIN
V
ILMAX
V
ILMAX
V
ILMAX
PCLK_IN
DIN, VSYNC_IN, HSYNC_IN
t
HOLD
t
SET
NOTE: PCLK_IN PROGRAMMED FOR RISING LATCHING EDGE.
Figure 5. MAX9257 Input Setup and Hold Times
MAX9257/MAX9258
______________________________________________________________________________________ 15
Fully Programmable Serializer/Deserializer
with UART/I2C Control Channel
t
PSD1
FIRST BIT LAST BIT
N
N+3
EXPANDED TIME SCALE
N+4
N
N+1
N+2
N-1
DIN, HSYNC_IN,
VSYNC_IN
PCLK_IN
SDO
Figure 6. MAX9257 Parallel-to-Serial Delay
V
ILMAX
t
HIGH
t
LOW
t
T
t
R
t
F
V
IHMIN
PCLK_IN
Figure 7. MAX9257 Parallel Input Clock Requirements
PCLK_OUT
DOUT
NOTE: PCLK_OUT PROGRAMMED FOR RISING LATCH EDGE.
Figure 8. MAX9258 Worst-Case Pattern Output
0.9 x V
CCOUT
0.1 x V
CCOUT
t
F
t
R
C
L
SINGLE-ENDED OUTPUT LOAD
MAX9258
Figure 9. MAX9258 Output Rise and Fall Times
MAX9257/MAX9258
16 ______________________________________________________________________________________
Fully Programmable Serializer/Deserializer with UART/I2C Control Channel
V
OLMAX
t
HIGH
t
LOW
t
T
V
OHMIN
PCLK_OUT
Figure 10. MAX9258 Clock Output High and Low Time
PCLK_OUT
t
DVB
t
DVA
V
OHMIN
V
OLMAX
V
OHMIN
V
OLMAX
NOTE: PCLK_OUT PROGRAMMED FOR RISING LATCHING EDGE.
DOUT, VSYNC_OUT, HSYNC_OUT, LOCK
Figure 11. MAX9258 Output Data Valid Times
PD
POWERED DOWN
t
PUD
POWERED UP
(OUTPUTS ACTIVE)
V
IHMIN
Figure 12. MAX9258 Power-Up Delay
PD
HIGH IMPEDANCE
DOUT,
VSYNC,
HSYNC
POWERED DOWNPOWERED UP
t
PDD
V
ILMAX
Figure 13. MAX9258 Power-Down Delay
MAX9257/MAX9258
______________________________________________________________________________________ 17
Fully Programmable Serializer/Deserializer
with UART/I2C Control Channel
FIRST BIT
SDI
PCLK_OUT
DOUT, HSYNC_OUT, VSYNC_OUT
LAST BIT
SERIAL WORD N
SERIAL-WORD LENGTH
SERIAL WORD N+1 SERIAL WORD N+2
t
SPD1
PARALLEL WORD N-2
PARALLEL WORD N-1 PARALLEL WORD N
NOTE: PCLK_OUT PROGRAMMED FOR RISING LATCHING EDGE.
Figure 14. MAX9258 Serial-to-Parallel Delay
1.0UI0.75UI0.50UI0.25UI0.0UI
t
JT
t
S
t
S
t
JT
+25mV
-25mV
+100mV
0V
-100mV
INPUT TEMPLATE FOR LVDS SERIAL
V
SDI+
- V
SDI-
NOTE: UI IS ONE SERIAL BIT. TIME INPUT IS MEASURED DIFFERENTIALLY (V
SDI+
- V
SDI-
).
t
R1A
t
F1B
t
R1B
t
F1A
(SDO+) - (SDO-)
0.8V
OD(+)
t
F2
t
R2
0.8 x | V
OD(+)
+ V
OD(-)
| 0.8 x | V
OD(+)
+ V
OD(-)
|
0.2V
OD(-)
0.8V
OD(-)
0.2V
OD(-)
0.8V
OD(-)
0.2 x | V
OD(+)
+ V
OD(-)
| 0.2 x | V
OD(+)
+ V
OD(-)
|
1 0
0.2V
OD(+)
0.8V
OD(+)
0.2V
OD(+)
Figure 15. MAX9258 Jitter Tolerance
Figure 16. Control Channel Transition Time
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