MAXIM MAX9247 User Manual

General Description

The MAX9247 digital video parallel-to-serial converter serializes 27 bits of parallel data into a serial-data stream. Eighteen bits of video data and 9 bits of control data are encoded and multiplexed onto the serial interface, reducing the serial-data rate. The data-enable input determines when the video or control data is serialized.

The MAX9247 pairs with the MAX9248/MAX9250 deserializers to form a complete digital video serial link. Interconnect can be controlled-impedance PCB traces or twisted-pair cable. Proprietary data encoding reduces EMI and provides DC balance. DC balance allows ACcoupling, providing isolation between the transmitting and receiving ends of the interface. The LVDS output is internally terminated with 100Ω. For operating frequencies less than 35MHz, the MAX9247 can also pair with the MAX9218 deserializer.

ESD tolerance is specified for ISO 10605 with ±10kV Contact Discharge and ±30kV Air-Gap Discharge.

The MAX9247 operates from a +3.3V core supply and features a separate input supply for interfacing to 1.8V to 3.3V logic levels. This device is available in a 48-lead LQFP package and is specified from -40°C to +85°C or

-40°C to +105°C.

Applications

Navigation System Displays

In-Vehicle Entertainment Systems

Video Cameras

LCDs

Features

o Preemphasis Improves Eye Diagram and Signal

Integrity at the Output

o Proprietary Data Encoding for DC Balance and

Reduced EMI

o Control Data Sent During Video Blanking o Five Control Data Inputs are Single-Bit-Error

Tolerant

o Programmable Phase-Shifted LVDS Signaling

Reduces EMI

o Output Common-Mode Filter Reduces EMI o Greater Than 10m STP Cable Drive o Wide ±2% Reference Clock Tolerance o ISO 10605 and IEC 61000-4-2 Level 4

ESD Protection

o Separate Input Supply Allows Interface to 1.8V

to 3.3V Logic

o +3.3V Core Supply o Space-Saving LQFP Package o -40°C to +85°C and -40°C to +105°C Operating

Temperature Ranges

MAX9247

________________________________________________________________

Maxim Integrated Products

Pin Configuration

Ordering Information

19-3955; Rev 4; 4/12

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

Denotes a lead(Pb)-free/RoHS-compliant package.

/V denotes an automotive qualified part.

27-Bit, 2.5MHz-to-42MHz

DC-Balanced LVDS Serializer

PART TEMP RANGE PIN-PACKAGE

MAX9247ECM+ -40°C to +85°C 48 LQFP

MAX9247ECM/V+ -40°C to +85°C 48 LQFP

MAX9247GCM+ -40°C to +105°C 48 LQFP

MAX9247GCM/V+ -40°C to +105°C 48 LQFP

TOP VIEW

GND

CCIN

RGB_IN10 RGB_IN11 RGB_IN12 RGB_IN13 RGB_IN14 RGB_IN15 RGB_IN16 RGB_IN17 CNTL_IN0 CNTL_IN1

RGB_IN9

RGB_IN8

RGB_IN7

RGB_IN6

RGB_IN5

4847464544434241403938

1314151617181920212223

GND

CNTL_IN3

CNTL_IN2

MAX9247

CNTL_IN4

LQFP

RGB_IN4

RGB_IN3

CNTL_IN5

CNTL_IN6

RGB_IN2

RGB_IN1

CNTL_IN7

CNTL_IN8

RGB_IN0

VCCGND

DE_IN

PCLK_IN

RNG0 RNG1

CCLVDS

OUT+

OUT-

LVDSGND

CMF

PWRDWN

CCPLL

PLLGND

PRE

I.C.

MAX9247

27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Serializer

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

DC ELECTRICAL CHARACTERISTICS

CC_

= +3.0V to +3.6V, RL= 100Ω ±1%, PWRDWN = high, PRE = low, TA= -40°C to +105°C, unless otherwise noted. Typical

values are at V

CC_

= +3.3V, TA= +25°C.) (Notes 1, 2)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

CC_

to _GND........................................................-0.5V to +4.0V

Any Ground to Any Ground...................................-0.5V to +0.5V

OUT+, OUT-, CMF to LVDSGND...........................-0.5V to +4.0V

OUT+, OUT- Short Circuit to LVDSGND

or V

CCLVDS

.............................................................Continuous

OUT+, OUT- Short Through 0.125µF (or smaller),

25V Series Capacitor..........................................-0.5V to +16V

RGB_IN[17:0], CNTL_IN[8:0], DE_IN,

RNG0, RNG1, PRE, PCLK_IN,

PWRDWN to GND ...............................-0.5V to (V

CCIN

+ 0.5V)

Continuous Power Dissipation (T

= +70°C)

48-Lead LQFP (derate 20.8mW/°C above +70°C)....1666.7mW

ESD Protection

Machine Model (R

= 0Ω, CS= 200pF)

All Pins to GND ..............................................................±200V

Human Body Model (R

= 1.5kΩ, CS= 100pF)

All Pins to GND ................................................................±3kV

ISO 10605 (R

= 2kΩ, CS= 330pF)

Contact Discharge (OUT+, OUT-) to LVDSGND ...........±10kV

Air-Gap Discharge (OUT+, OUT-) to LVDSGND ...........±30kV

IEC 61000-4-2 (R

= 330Ω, CS= 150pF)

Contact Discharge (OUT+, OUT-) to LVDSGND ...........±10kV

Air-Gap Discharge (OUT+, OUT-) to LVDSGND ...........±15kV

Storage Temperature Range .............................-65°C to +150°C

Junction Temperature......................................................+150°C

Lead Temperature (soldering,10s)..................................+300°C

Soldering Temperature (reflow) .......................................+260°C

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

SINGLE-ENDED INPUTS (RGB_IN[17:0], CNTL_IN[8:0], DE_IN, PCLK_IN, PWRDWN, RNG_, PRE)

High-Level Input Voltage V

Low-Level Input Voltage V

Input Current I

Input Clamp Voltage V

LVDS OUTPUTS (OUT+, OUT-)

Differential Output Voltage V

Change in VOD Between Complementary Output States

Common-Mode Voltage V

Change in VOS Between Complementary Output States

Output Short-Circuit Current I

Magnitude of Differential Output Short-Circuit Current

Output High-Impedance Current

∆V

OSD

= 1.71V to < 3V (Note 3) 0.65 x V

CCIN

= 3.0V to 3.6V 2 0.3 + V

CCIN

= 1.71V to < 3V (Note 3) -0.3 0.3 x V

CCIN

= 3.0V to 3.6V -0.3 +0.8

CCIN

= 1.71V

CCIN

to 3.6V, PWRDWN = high or low

VIN = -0.3V to 0V (MAX9247ECM), V (MAX9247GCM)

ICL = -18mA -1.5 V

Figure 1 250 335 450 mV

Figure 1 20 mV

Figure 1 1.125 1.29 1.475 V

Figure 1 20 mV

or V

OUT+

= 0V 5.5 15 mA

= 0V or 3.6V -15 ±8 +15 mA

OUT-

PWRDWN = low or V

CC_

= 0V

CCIN

+ 0.3

CCIN

= -0.15V to 0V

= 0V to ( V

OUT+

OUT-

OU T +

OUT-

CCIN

-100 +20

+ 0.3V) -20 +20

C C IN

= 0V,

= 3.6V

= 3.6V ,

-1 +1 µA

= 0V

µA

MAX9247

27-Bit, 2.5MHz-to-42MHz

DC-Balanced LVDS Serializer

_______________________________________________________________________________________ 3

AC ELECTRICAL CHARACTERISTICS

CC_

= +3.0V to +3.6V, RL= 100Ω ±1%, CL= 5pF, PWRDWN = high, PRE = low, TA= -40°C to +105°C, unless otherwise noted.

Typical values are at V

CC_

= +3.3V, TA= +25°C.) (Note 3)

DC ELECTRICAL CHARACTERISTICS (continued)

CC_

= +3.0V to +3.6V, RL= 100Ω ±1%, PWRDWN = high, PRE = low, TA= -40°C to +105°C, unless otherwise noted. Typical

values are at V

CC_

= +3.3V, TA= +25°C.) (Notes 1, 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Differential Output Resistance R

Worst-Case Supply Current

Power-Down Supply Current I

CCW

CCZ

78 110 147 Ω

2.5MHz

5MHz

RL = 100Ω ±1%, C

= 5pF,

continuous 10 transition words

(Note 4) 50 µA

10MHz

20MHz

35MHz

42MHz

PRE = 0 15 25

PRE = 1 27

PRE = 0 18 25

PRE = 1 27

PRE = 0 23 28

PRE = 1 30

PRE = 0 33 39

PRE = 1 42

PRE = 0 50 65

PRE = 1 69

PRE = 0 60 70

PRE = 1 75

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

PCLK_IN TIMING REQUIREMENTS

Clock Period t

Clock Frequency f

Clock Frequency Difference from Deserializer Reference Clock

Clock Duty Cycle DC t

Clock Transition Time tR, t

SWITCHING CHARACTERISTICS

Output Rise Time t

Output Fall Time t

Input Setup Time t

Input Hold Time t

CLK

∆f

CLK

RISE

FALL

SET

HOLD

Figure 2

MAX9247ECM 2.5 42.0

MAX9247GCM 2.5 35.0

or t

HIGH/tT

Figure 2 2.5 ns

20% to 80%, V

80% to 20%, V

Figure 4 3 ns

LOW

≥ 250mV, Figure 3

MAX9247ECM 23.8 400.0

MAX9247GCM 28.6 400.0

-2 +2 %

/tT, Figure 2 35 50 65 %

PRE = low 280 370

PRE = high 240 320

PRE = low 280 370

PRE = high 240 320

MHz

MAX9247

27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Serializer

4 _______________________________________________________________________________________

AC ELECTRICAL CHARACTERISTICS (continued)

CC_

= +3.0V to +3.6V, RL= 100Ω±1%, CL= 5pF, PWRDWN = high, PRE = low, TA= -40°C to +105°C, unless otherwise noted.

Typical values are at V

CC_

= +3.3V, TA= +25°C.) (Note 3)

)

Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground,

except V

, ∆VOD, and ∆VOS.

Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production

tested at T

= +25°C.

Note 3: Parameters are guaranteed by design and characterization and are not production tested. Limits are set at ±6 sigma. Note 4: All LVTTL/LVCMOS inputs, except PWRDWN at ≤ 0.3V or ≥ V

CCIN

- 0.3V. PWRDWN is ≤ 0.3V.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Serializer Delay t

PLL Lock Time t

Power-Down Delay t

Peak-to-Peak Output Jitter t

Peak-to-Peak Output Offset Voltage

LOCK

JITT

OS(P-P

Figure 5

Figure 6

Figure 7 1 µs

Measured with PRBS input pattern at 840Mbps data rate

840Mbps data rate, CMF open, Figure 8

840Mbps data rate, CMF 0.1µF to ground, Figure 8

3.10 x + 2.0

22 70

12 50

3.10 x

tT + 8.0

17,100 x

150 ps

MAX9247

27-Bit, 2.5MHz-to-42MHz

DC-Balanced LVDS Serializer

_______________________________________________________________________________________ 5

Typical Operating Characteristics

CC_

= +3.3V, RL= 100Ω, TA = +25°C, unless otherwise noted.)

WORST-CASE PATTERN

SUPPLY CURRENT vs. FREQUENCY

SUPPLY CURRENT (mA)

WITH PREEMPHASIS

WITHOUT PREEMPHASIS

FREQUENCY (MHz)

MAX9247 toc01

100mV/div

40302010

BIT-ERROR RATE vs. CABLE LENGTH

1.00E-14

1.00E-13

1.00E-12

BIT-ERROR RATE

1.00E-11

1.00E-10

CAT5 CABLE

= 42MHz

REFCLK

840Mbps DATA RATE FOR CABLE LENGTH < 10m

-12

BER < 10

CAT5 CABLE LENGTH (m)

EYE DIAGRAM WITHOUT PREEMPHASIS

GND

200ps/div

MAX9247 toc04

2 METER CAT5 CABLE

100Ω TERMINATION

vs. FREQUENCY BIT-ERROR RATE < 10

FREQUENCY (MHz)

81012642

PRE = LOW f

= 42MHz

REFCLK

MAX9247 toc02

100mV/div

CABLE LENGTH

CABLE LENGTH (m)

EYE DIAGRAM WITH PREEMPHASIS

PRE = HIGH

= 42MHz

REFCLK

2 METER CAT5 CABLE

100Ω TERMINATION

GND

200ps/div

-9

MAX9247 toc05

18161412108642020

MAX9247 toc03

MAX9247

27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Serializer

6 _______________________________________________________________________________________

Pin Description

PIN NAME FUNCTION

1, 13, 37 GND Input Buffer Supply and Digital Supply Ground

RGB_IN10–

3–10,

39–48

11, 12, 15–21

14, 38 V

22 DE_IN

23 PCLK_IN

24 I.C. Internally Connected. Leave unconnected for normal operation.

25 PRE Preemphasis Enable Input. Drive PRE high to enable preemphasis.

26 PLLGND PLL Supply Ground

27 V

28 PWRDWN LVTTL/LVCMOS Power-Down Input. Internally pulled down to GND.

29 CMF

30, 31 LVDSGND LVDS Supply Ground

32 OUT- Inverting LVDS Serial-Data Output

33 OUT+ Noninverting LVDS Serial-Data Output

34 V

35 RNG1

36 RNG0

RGB_IN17,

RGB_IN0–

CNTL_IN0, CNTL_IN1,

CNTL_IN2–

CNTL_IN8

CCIN

RGB_IN9

CCPLL

CCLVDS

Input Buffer Supply Voltage. Bypass to GND with 0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin.

LVTTL/LVCMOS Red, Green, and Blue Digital Video Data Inputs. Eighteen data bits are loaded into the input latch on the rising edge of PCLK_IN when DE_IN is high. Internally pulled down to GND.

LVTTL/LVCMOS Control Data Inputs. Control data are latched on the rising edge of PCLK_IN when DE_IN is low. Internally pulled down to GND.

Digital Supply Voltage. Bypass to GND with 0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin.

LVTTL/LVCMOS Data-Enable Input. Logic-high selects RGB_IN[17:0] to be latched. Logic-low selects CNTL_IN[8:0] to be latched. DE_IN must be switching for proper operation. Internally pulled down to GND.

LVTTL/LVCMOS Parallel Clock Input. Latches data and control inputs and provides the PLL reference clock. Internally pulled down to GND.

PLL Supply Voltage. Bypass to PLLGND with 0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin.

Common-Mode Filter. Optionally connect a capacitor between CMF and LVDSGND to filter common-mode switching noise.

LVDS Supply Voltage. Bypass to LVDSGND with 0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin.

LVTTL/LVCMOS Frequency Range Select Input. Set to the frequency range that includes the PCLK_IN frequency as shown in Table 3. Internally pulled down to GND.

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