General Description
The MAX9242/MAX9244/MAX9246/MAX9254 deserialize
three LVDS serial-data inputs into 21 single-ended LVCMOS/LVTTL outputs. A separate parallel-rate LVDS clock
provides the timing for deserialization. The MAX9242/
MAX9244/MAX9246/MAX9254 feature spread-spectrum
capability, allowing the output data and clock frequency
to spread over a specified range to reduce EMI. The single-ended data and clock outputs are programmable for
a frequency spread of ±2%, ±4%, or no spread. The
spread-spectrum function is also available when the
MAX9242/MAX9244/MAX9246/MAX9254 operate in nonDC-balanced mode. The modulation rate of the spread is
32kHz for a 33MHz LVDS clock input and scales linearly
with frequency. The single-ended outputs have a separate supply, allowing +1.8V to +5V output logic levels.
The MAX9254 features high output drive current for both
data and clock outputs for faster transition times in the
presence of heavy capacitive loads.
The MAX9242/MAX9244/MAX9246/MAX9254 feature programmable DC balance, allowing isolation between a
serializer and deserializer using AC-coupling. The
MAX9242/MAX9244/MAX9246/MAX9254 operate with the
MAX9209/MAX9213 serializers and are available with a
rising-edge strobe (MAX9242) or falling-edge strobe
(MAX9244/MAX9246/MAX9254). The LVDS inputs meet
ISO 10605 ESD specifications with ±30kV Air-Gap
Discharge and ±6kV Contact Discharge ratings.
Applications
Automotive Navigation Systems
Automotive DVD Entertainment Systems
Digital Copiers
Laser Printers
Features
♦ Programmable ±4%, ±2%, or OFF Spread-Spectrum
Output for Reduced EMI
♦ Programmable DC-Balanced or Non-DC-Balanced
Modes
♦ DC Balance Allows AC-Coupling for Wider Input
Common-Mode Voltage Range
♦ Spread Spectrum Operates in DC-Balanced or
Non-DC-Balanced Mode
♦ High Output Drive (MAX9254)
♦ππ/ 4 Deskew by Oversampling
(MAX9242/MAX9244/MAX9254)
♦ 16MHz-to-34MHz (DC-Balanced) and 20MHz-to-
40MHz (Non-DC-Balanced) Operation
(MAX9242/MAX9244/MAX9254)
♦ 6MHz-to-18MHz (DC-Balanced) and 8MHz-to-20MHz
(Non-DC-Balanced) Operation (MAX9246)
♦ Rising-Edge (MAX9242) or Falling-Edge
(MAX9244/MAX9246/MAX9254) Output Strobe
♦ High-Impedance Outputs when PWRDWN is Low
Allow Output Busing
♦ Separate Output Supply Allows Interface to +1.8V,
+2.5V, +3.3V, and +5V Logic
♦ LVDS Inputs Meet ISO 10605 ESD Protection at
±30kV Air-Gap Discharge and ±6kV Contact
Discharge
♦ LVDS Inputs Meet IEC 61000-4-2 Level 4 ESD
Protection at ±15kV Air-Gap Discharge and ±8kV
Contact Discharge
♦ LVDS Inputs Conform to ANSI TIA/EIA-644 Standard
♦ +3.3V Main Power Supply
MAX9242/MAX9244/MAX9246/MAX9254
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
________________________________________________________________
Maxim Integrated Products
1
Ordering Information
19-3954; Rev 4; 7/09
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
+
Denotes a lead(Pb)-free/RoHS-compliant package.
/V denotes an automotive qualified part.
Note: All devices are available in lead(Pb)-free/RoHS-compliant
packaging. Specify lead(Pb)-free/RoHS compliant by adding a
+ symbol at the end of the part number when ordering.
Selector Guide
Pin Configuration appears at end of data sheet.
Ordering Information continued at end of data sheet.
EVALUATION KIT
AVAILABLE
FREQUENCY RANGE
PART
MAX9242 Rising Yes 20 to 40 16 to 34
MAX9244 Falling Yes 20 to 40 16 to 34
MAX9246 Falling No 8 to 20 6 to 18
MAX9254 Falling Yes 20 to 40 16 to 34
STROBE
EDGE
OVER-
SAMPLING
NON-DC
BALANCE
(MHz)
DC
BALANCE
(MHz)
PART TEMP RANGE PIN-PACKAGE
MAX9242EUM -40°C to +85°C 48 TSSOP
MAX9242EUM/V+ -40°C to +85°C 48 TSSOP
MAX9242GUM -40°C to +105°C 48 TSSOP
MAX9242GUM/V+ -40°C to +105°C 48 TSSOP
MAX9244EUM -40°C to +85°C 48 TSSOP
MAX9244EUM/V+ -40°C to +85°C 48 TSSOP
MAX9244GUM -40°C to +105°C 48 TSSOP
MAX9244GUM/V+ -40°C to +105°C 48 TSSOP
MAX9242/MAX9244/MAX9246/MAX9254
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(VCC= LVDSVCC= PLLVCC= +3.0V to +3.6V, V
CCO
= +3.0V to +5.5V, PWRDWN = high; SSG = high, open, or low; DCB = high or
low, differential input voltage |V
ID
| = 0.05V to 1.2V, input common-mode voltage VCM= |V
ID
/ 2| to 2.4V - |V
ID
/ 2|, unless otherwise
noted. Typical values are at V
CC
= V
CCO
= LVDSVCC= PLLVCC= +3.3V, |VID| = 0.2V, VCM= +1.25V, TA= +25°C.) (Notes 1, 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
(All voltages referenced to GND.)
V
CC
, LVDSVCC, PLLVCC.......................................-0.5V to +4.0V
V
CCO
......................................................................-0.5V to +6.0V
RxIN__, RxCLKIN_.................................................-0.5V to +4.0V
PWRDWN ..............................................................-0.5V to +6.0V
SSG, DCB...................................................-0.5V to (V
CC
+ 0.5V)
RxOUT_, RxCLKOUT ...............................-0.5V to (V
CCO
+ 0.5V)
Continuous Power Dissipation (T
A
= +70°C)
48-Pin TSSOP (derate 16mW/°C above +70°C) ........1282mW
ESD Protection
Human Body Model (R
D
= 1.5kΩ, CS= 100pF)
All Pins to GND .............................................................±2.5kV
IEC 61000-4-2 (R
D
= 330Ω, CS= 150pF)
LVDS Inputs to GND (Air-Gap Discharge).....................±15kV
LVDS Inputs to GND (Contact Discharge).......................±8kV
ISO 10605 (R
D
= 2.0kΩ, CS= 330pF)
LVDS Inputs to GND (Air-Gap Discharge).....................±30kV
LVDS Inputs to GND (Contact Discharge).......................±6kV
Operating Temperature Range .........................-40°C to +105°C
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER SUPPLY
Power-Supply Range
Output-Supply Range V
Worst-Case Supply Current I
,
V
CC
LVDSV
CC
PLLV
CC
CCO
CCW
,
DC-balanced
mode (SSG = low)
CL = 8pF,
worst-case pattern,
= V
V
CC
to 3.6V, Figure 2
(MAX9242,
MAX9244,
MAX9254)
CCO
= 3.0V
Non-DC-balanced
mode (SSG = low)
D C - b al anced m od e
( S SG = hi g h or op en)
N on- D C -b al anced
m ode
( S SG = hi g h or op en)
16MHz 50 68
34MHz 81 108
20MHz 55 73
33MHz 75 97
40MHz 83 110
16MHz 62 85
34MHz 101 135
20MHz 67 91
33MHz 93 123
40MHz 107 134
3.0 3.6 V
1.8 5.5 V
mA
MAX9242/MAX9244/MAX9246/MAX9254
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
_______________________________________________________________________________________ 3
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC= LVDSVCC= PLLVCC= +3.0V to +3.6V, V
CCO
= +3.0V to +5.5V, PWRDWN = high; SSG = high, open, or low; DCB = high or
low, differential input voltage |V
ID
| = 0.05V to 1.2V, input common-mode voltage VCM= |V
ID
/ 2| to 2.4V - |V
ID
/ 2|, unless otherwise
noted. Typical values are at V
CC
= V
CCO
= LVDSVCC= PLLVCC= +3.3V, |VID| = 0.2V, VCM= +1.25V, TA= +25°C.) (Notes 1, 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Worst-Case Supply Current I
Power-Down Supply Current I
5V-TOLERANT LOGIC INPUT (PWRDWN)
High-Level Input Voltage V
Low-Level Input Voltage V
Input Current I
Input Clamp Voltage V
THREE-LEVEL LOGIC INPUTS (DCB, SSG)
High-Level Input Voltage V
Mid-Level Input Current I
Low-Level Input Voltage V
Input Current I
Input Clamp Voltage V
SINGLE-ENDED OUTPUTS (RxOUT_, RxCLKOUT)
High-Level Output Voltage V
Low-Level Output Voltage V
CCW
CCZ
IH
IL
IN
CL
IH
IM
IL
IN
CL
OH
OL
DC-balanced
mode (SSG = low)
CL = 8pF,
worst-case pattern,
V
= V
CC
to 3.6V, Figure 2
(MAX9246)
PWRDWN = low 50 µA
PWRDWN = high or low level -20 +20 µA
ICL = -18mA -1.5 V
D C B, S S G op en or connected to a d r i ver w i th
outp ut i n hi g h- i m p ed ance state ( N ote 3)
DCB, SSG = high or low level,
PWRDWN = high or low
ICL = -18mA -1.5 V
IOH = -100µA
IOH = -2mA
IOL = 100µA 0.1
IOL = 2mA
CCO
= 3.0V
Non-DC-balanced
mode (SSG = low)
D C -b al anced m od e
( S SG = hi g h or op en)
N on- D C -b al anced
m ode
( S SG = hi g h or op en)
RxCLKOUT (Note 4)
RxOUT_
RxCLKOUT (Note 4) 0.2
RxOUT_
6MHz 29 45
8MHz 33 49
18MHz 48 69
8MHz 33 47
10MHz 37 52
20MHz 52 73
6MHz 37 54
8MHz 41 62
18MHz 65 91
8MHz 41 58
10MHz 46 65
20MHz 66 92
2.0 5.5 V
-0.3 +0.8 V
2.5
-10 +10 µA
-0.3 +0.8 V
-20 +20 µA
V
CCO
- 0.1
V
CCO
- 0.25
V
CCO
- 0.43
V
MAX9254
MAX9254 0.2
CCO
- 0.25
V
CC
0.3
0.26
mA
+
V
V
V
MAX9242/MAX9244/MAX9246/MAX9254
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
4 _______________________________________________________________________________________
AC ELECTRICAL CHARACTERISTICS
(VCC= LVDSVCC= PLLVCC= +3.0V to +3.6V, V
CCO
= +3.0V to +3.6V, CL= 8pF, PWRDWN = high; SSG = high, open, or low;
DCB = high or low, differential input voltage |V
ID
| = 0.1V to 1.2V, input common-mode voltage VCM= |V
ID
/ 2| to 2.4V - |V
ID
/ 2|, unless
otherwise noted. Typical values are at V
CC
= V
CCO
= LVDSVCC= PLLVCC= +3.3V, |VID| = 0.2V, VCM= +1.25V, TA= +25°C.) (Notes 6, 7, 8)
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC= LVDSVCC= PLLVCC= +3.0V to +3.6V, V
CCO
= +3.0V to +5.5V, PWRDWN = high; SSG = high, open, or low; DCB = high or
low, differential input voltage |V
ID
| = 0.05V to 1.2V, input common-mode voltage VCM= |V
ID
/ 2| to 2.4V - |V
ID
/ 2|, unless otherwise
noted. Typical values are at V
CC
= V
CCO
= LVDSVCC= PLLVCC= +3.3V, |VID| = 0.2V, VCM= +1.25V, TA= +25°C.) (Notes 1, 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
High-Impedance Output Current I
Output Short-Circuit Current
(Note 5)
Output Short-Circuit Current
(MAX9254) (Note 5)
OZ
I
OS
I
OS
LVDS INPUTS (RxIN__, RxCLKIN_)
Differential Input High Threshold V
Differential Input Low Threshold V
Input Current I
Power-Off Input Current I
Input Resistor 1 R
Input Resistor 2 R
IN+
INO+
TH
TL
, I
IN-
, I
INO-VCC
IN1
IN2
PWRDWN = low, V
V
= 3.0V to 3.6V,
CCO
V
= 0V
OUT
V
= 4.5V to 5.5V,
CCO
V
= 0V
OUT
V
= 3.0V to 3.6V,
CCO
V
= 0V
OUT
V
= 4.5V to 5.5V,
CCO
= 0V
V
OUT
= -0.3V to (V
OUT
CCO
RxCLKOUT (Note 4) -10 -40
RxOUT_ -5 -20
RxCLKOUT (Note 4) -28 -75
RxOUT_ -13 -37
RxOUT_
RxCLKOUT (Note 4)
RxOUT_
RxCLKOUT (Note 4)
+ 0.3V) -30 +30 µA
-16 -51
-34 -93
(Note 6) 50 mV
(Note 6) -50 mV
PWRDWN = high or low -25 +25 µA
= V
PWRDWN = high or low,
V
= V
CC
Figure 1
PWRDWN = high or low,
= V
V
CC
Figure 1
= 0V or open -40 +40 µA
CCO
-40°C to +85°C 42 78
= 0V or open,
CCO
-40°C to +105°C 42 85
-40°C to +85°C 246 410
= 0V or open,
CCO
-40°C to +105°C 246 440
mA
mA
kΩ
kΩ
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Rise Time CLHT
Output Fall Time CHLT
Output Rise Time (MAX9254) CLHT
Output Fall Time (MAX9254) CHLT
RxIN__ Skew Margin (Note 9) RSKM
0.1 x V
C C O
to 0.9 x V
Fi g ur e 3
0.9 x V
C C O
to 0.1 x V
Fi g ur e 3
0.1 x V
C C O
to 0.9 x V
Fi g ur e 3
0.9 x V
C C O
to 0.1 x V
Fi g ur e 3
DC-balanced mode,
Figure 4
Non-DC-balanced mode,
Figure 4
RxOUT_ 2.9 4.7 6.5
,
C C O
RxCLKOUT 2.0 3.3 4.1
RxOUT_ 2.1 3.0 4.2
,
C C O
RxCLKOUT 1.10 1.94 2.70
,
C C O
RxOUT_ 1.4 2.2 3.3 ns
,
C C O
RxCLKOUT 1.1 1.8 2.8 ns
16MHz 2560 3142
34MHz 900 1386
20MHz 2500 3164
40MHz 960 1371
ns
ns
ps
MAX9242/MAX9244/MAX9246/MAX9254
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
_______________________________________________________________________________________ 5
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground,
except V
TH
and VTL.
Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production
tested at T
A
= +25°C.
Note 3: To provide a mid level, leave the input open, or, if driven, put driver in high impedance. High-impedance leakage current
must be less than ±10µA.
Note 4: RxCLKOUT limits are scaled based on RxOUT_ measurements, design, and characterization data.
Note 5: One output shorted at a time. Current out of the pin.
Note 6: V
TH
, VTL, and AC parameters are guaranteed by design and characterization, and are not production tested. Limits are set
at ±6 sigma.
Note 7: C
L
includes probe and test jig capacitance.
Note 8: RCIP is the period of RxCLKIN_. RCOP is the period of RxCLKOUT.
Note 9: RSKM is measured with less than 150ps cycle-to-cycle jitter on RxCLKIN_.
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC= LVDSVCC= PLLVCC= +3.0V to +3.6V, V
CCO
= +3.0V to +3.6V, CL= 8pF, PWRDWN = high; SSG = high, open, or low;
DCB = high or low, differential input voltage |V
ID
| = 0.1V to 1.2V, input common-mode voltage VCM= |V
ID
/ 2| to 2.4V - |V
ID
/ 2|, unless
otherwise noted. Typical values are at V
CC
= V
CCO
= LVDSVCC= PLLVCC= +3.3V, |VID| = 0.2V, VCM= +1.25V, TA= +25°C.) (Notes 6, 7, 8)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
RxCLKOUT High Time RCOH Figures 5a, 5b
RxCLKOUT Low Time RCOL Figures 5a, 5b
RxOUT_ Setup to RxCLKOUT RSRC Figures 5a, 5b
RxOUT_ Hold from RxCLKOUT RHRC Figures 5a, 5b
RxCLKIN_ to RxCLKOUT Delay RCCD SSG = low, Figures 6a, 6b
Deserializer Phase-LockedLoop Set
Deserializer Power-Down Delay RPDD Figure 8 100 ns
Deserializer Phase-LockedLoop Set from SSG Change
Spread-Spectrum Output
Frequency
Spread-Spectrum Modulation
Frequency
RPLLS Figure 7
RPLLS2 Figure 9
f
RxCLKOUT
f
SSM
0.35 x
RCOP
0.35 x
RCOP
0.3 x
RCOP
0.45 x
RCOP
4.5 +
(RCIP / 2)
M axi m um outp ut
SSG = high,
Figure 10
SSG = open,
Figure 10
SSG = low f
Figure 10
fr eq uency
Minimum output
frequency
M axi m um outp ut
fr eq uency
Minimum output
frequency
f
RxCLKIN_
+ 3.6%
f
RxCLKIN_
- 4.4%
f
RxCLKIN_
+ 1.8%
f
RxCLKIN_
- 2.2%
RxCLKIN_
6.5 +
(RCIP / 2)
f
RxCLKIN_
+ 4.0%
f
RxCLKIN_
- 4.0%
f
RxCLKIN_
+ 2.0%
f
RxCLKIN_
- 2.0%
f
RxCLKIN_
1016
(RCIP / 2)
65,600 x
32,800 x
f
RxCLKIN_
+ 4.4%
f
RxCLKIN_
- 3.6%
f
RxCLKIN_
+ 2.2%
f
RxCLKIN_
- 1.8%
f
RxCLKIN_
/
8.2 +
RCIP
RCIP
ns
ns
ns
ns
ns
ns
ns
MHz
Hz
MAX9242/MAX9244/MAX9246/MAX9254
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
6 _______________________________________________________________________________________
Test Circuits/Timing Diagrams
Figure 1. LVDS Input Circuits
Figure 2. Worst-Case Test Pattern
Figure 3. Output Load and Transition Times
Figure 4. LVDS Receiver Input Skew Margin
Figure 5a. Rising-Edge Output Setup/Hold and High/Low Times
V
CC
R
RxIN_ + OR
RxCLKIN+
R
IN1
R
IN1
RxIN_ - OR
RxCLKIN-
FAIL-SAFE
IN2
COMPARATOR
VCC - 0.3V
RxOUT_ OR
RxCLKOUT
RxIN_ + OR
RxCLKIN+
R
IN1
R
IN1
RxIN_ - OR
RxCLKIN-
8pF
RCOP
RxCLKOUT
1.2V
DC-BALANCED MODENON-DC-BALANCED MODE
ODD RxOUT
EVEN RxOUT
90%90%
RxOUT_ OR
RxCLKOUT
10%10%
IDEAL SERIAL BIT TIME
RSKM RSKM
IDEAL
MIN MAX
INTERNAL STROBE
IDEAL
1.3V
1.1V
RCOP
RxCLK OUT
RxOUT_
2.0V
2.0V
0.8V
0.8V 0.8V
CHLTCLHT
2.0V
0.8V
2.0V
2.0V
RCOHRCOL
RHRCRSRC
MAX9242/MAX9244/MAX9246/MAX9254
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
_______________________________________________________________________________________ 7
Test Circuits/Timing Diagrams (continued)
Figure 6a. Clock-IN to Clock-OUT Delay (MAX9244/MAX9246/
MAX9254)
Figure 7. Phase-Locked-Loop Set Time
Figure 8. Power-Down Delay
Figure 6b. Clock-IN to Clock-OUT Delay (MAX9242)
Figure 5b. Falling-Edge Output Setup/Hold and High/Low Times
RCOP
RxCLKOUT
RxOUT_
RxCLKIN_
RxCLKOUT
2.0V 2.0V
0.8V 0.8V 0.8V
RCOH RCOL
2.0V
0.8V
+
-
RCIP
VID = 0V
RCCD
1.5V
RHRCRSRC
2.0V
0.8V
RCIP
RxCLKIN_
RxCLKOUT
VID = 0V
RCCD
1.5V
2V
PWRDWN
3V
V
CC
RPLLS
PWRDWN
1.5V
RxCLKIN_
RPDD
RxOUT_
RxCLKOUT
1.5V
HIGH IMPEDANCE
RxCLKIN_
RxCLKOUT
HIGH IMPEDANCE
1.5V
MAX9242/MAX9244/MAX9246/MAX9254
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
8 _______________________________________________________________________________________
Test Circuits/Timing Diagrams (continued)
Figure 10. Simplified Modulation Profile
Figure 9. Phase-Locked-Loop Set Time from SSG Change
2.5V
SSG OPEN OR LESS THAN ±10μA LEAKAGE
0.8V
RPLLS2
RxCLKIN_
RxCLKOUT
RxOUT_
TIMING SHOWN FOR FALLING-EDGE STROBE (MAX9244/MAX9246/MAX9254)
PWRDWN = HIGH
FREQUENCY
1 / f
SSM
f
(MAX)
RxCLKOUT
f
f
RxCLKOUT
RxCLKIN_
(MIN)
TIME
MAX9242/MAX9244/MAX9246/MAX9254
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
_______________________________________________________________________________________
9
Typical Operating Characteristics
(VCC= PLLVCC= LVDSVCC= V
CCO
= +3.3V, CL= 8pF, PWRDWN = high, differential input voltage |VID| = 0.2V, input common-mode
voltage V
CM
= 1.2V, TA = +25°C, MAX9244/MAX9254, unless otherwise noted.)
RxOUT_TRANSITION TIME
vs. OUTPUT SUPPLY VOLTAGE (V
CCO
)
MAX9242 toc06
OUTPUT SUPPLY VOLTAGE (V)
OUTPUT TRANSITION TIME (ns)
3.53.02.52.0
2
4
6
8
10
12
14
0
1.5 4.0 5.04.5 5.5
C
LHT
C
HLT
RxCLKOUT POWER SPECTRUM
vs. FREQUENCY
(RxCLKIN_ = 33MHz, NO SPREAD)
MAX9242 toc07
FREQUENCY (MHz)
POWER SPECTRUM (dBm)
33
-40
-30
-20
-10
0
10
20
-50
-70
-60
-80
30 36
RESOLUTION BW = 100kHz
VIDEO BW = 100kHz
ATTENUATION = 50dB
RxCLKOUT POWER SPECTRUM
vs. FREQUENCY
(RxCLKIN_ = 33MHz, 2% SPREAD)
MAX9242 toc08
FREQUENCY (MHz)
POWER SPECTRUM (dBm)
33
-40
-30
-20
-10
0
10
20
-50
-70
-60
-80
30 36
RESOLUTION BW = 100kHz
VIDEO BW = 100kHz
ATTENUATION = 50dB
RxCLKOUT POWER SPECTRUM
vs. FREQUENCY
(RxCLKIN_ = 33MHz, 4% SPREAD)
MAX9242 toc09
FREQUENCY (MHz)
POWER SPECTRUM (dBm)
33
-40
-30
-20
-10
0
10
20
-50
-70
-60
-80
30 36
RESOLUTION BW = 100kHz
VIDEO BW = 100kHz
ATTENUATION = 50dB
100
SUPPLY CURRENT (mA)
100
SUPPLY CURRENT (mA)
WORST-CASE AND PRBS SUPPLY CURRENT
(NON-DC-BALANCED MODE, NO SPREAD)
90
WORST-CASE PATTERN
80
70
60
50
40
30
15 40
WORST-CASE AND PRBS SUPPLY CURRENT
(DC-BALANCED MODE, 4% SPREAD)
90
WORST-CASE PATTERN
80
70
60
50
40
vs. FREQUENCY
FREQUENCY (MHz)
vs. FREQUENCY
27 - 1 PRBS
WORST-CASE AND PRBS SUPPLY CURRENT
(DC-BALANCED MODE, 2% SPREAD)
100
90
WORST-CASE PATTERN
80
70
60
SUPPLY CURRENT (mA)
50
40
30
15 40
vs. FREQUENCY
27 - 1 PRBS
FREQUENCY (MHz)
27 - 1 PRBS
35302520
100
90
MAX9242 toc01
80
70
60
SUPPLY CURRENT (mA)
50
40
30
3.4
3.3
MAX9242 toc04
3.2
3.1
DROPOUT (V)
3.0
2.9
WORST-CASE AND PRBS SUPPLY CURRENT
(DC-BALANCED MODE, NO SPREAD)
WORST-CASE PATTERN
15 40
vs. FREQUENCY
27 - 1 PRBS
35302520
FREQUENCY (MHz)
RxOUT_ OUTPUT LOADING
MAX9254
MAX9244
MAX9242 toc02
MAX9242 toc05
MAX9242 toc03
35302520
30
15 40
2.8
FREQUENCY (MHz)
35302520
03
LOAD (mA)
21
MAX9242/MAX9244/MAX9246/MAX9254
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
10 ______________________________________________________________________________________
Typical Operating Characteristics (continued)
(VCC= PLLVCC= LVDSVCC= V
CCO
= +3.3V, CL= 8pF, PWRDWN = high, differential input voltage |VID| = 0.2V, input common-mode
voltage V
CM
= 1.2V, TA = +25°C, MAX9244/MAX9254, unless otherwise noted.)
RxCLKOUT POWER SPECTRUM
vs. FREQUENCY
(RxCLKIN_ = 16MHz, NO SPREAD)
MAX9242 toc10
FREQUENCY (MHz)
POWER SPECTRUM (dBm)
16
-40
-30
-20
-10
0
10
20
-50
-70
-60
-80
14 18
RESOLUTION BW = 100kHz
VIDEO BW = 100kHz
ATTENUATION = 50dB
RxCLKOUT POWER SPECTRUM
vs. FREQUENCY
(RxCLKIN_ = 16MHz, 2% SPREAD)
MAX9242 toc11
FREQUENCY (MHz)
POWER SPECTRUM (dBm)
16
-40
-30
-20
-10
0
10
20
-50
-70
-60
-80
14 18
RESOLUTION BW = 100kHz
VIDEO BW = 100kHz
ATTENUATION = 50dB
RxCLKOUT POWER SPECTRUM
vs. FREQUENCY
(RxCLKIN_ = 16MHz, 4% SPREAD)
MAX9242 toc12
FREQUENCY (MHz)
POWER SPECTRUM (dBm)
16
-40
-30
-20
-10
0
10
20
-50
-70
-60
-80
14 18
RESOLUTION BW = 100kHz
VIDEO BW = 100kHz
ATTENUATION = 50dB
RxOUT_ POWER SPECTRUM
vs. FREQUENCY
(RxCLKIN_ = 33MHz, NO SPREAD)
MAX9242 toc13
FREQUENCY (MHz)
POWER SPECTRUM (dBm)
16.5
-40
-30
-20
-10
0
10
20
-50
-70
-60
-80
15.0 18.0
RESOLUTION BW = 100kHz
VIDEO BW = 100kHz
ATTENUATION = 50dB
RxOUT_ POWER SPECTRUM
vs. FREQUENCY
(RxCLKIN_ = 33MHz, 2% SPREAD)
MAX9242 toc14
FREQUENCY (MHz)
POWER SPECTRUM (dBm)
16.5
-40
-30
-20
-10
0
10
20
-50
-70
-60
-80
15.0 18.0
RESOLUTION BW = 100kHz
VIDEO BW = 100kHz
ATTENUATION = 50dB
RxOUT_ POWER SPECTRUM
vs. FREQUENCY
(RxCLKIN_ = 33MHz, 4% SPREAD)
MAX9242 toc15
FREQUENCY (MHz)
POWER SPECTRUM (dBm)
16.5
-40
-30
-20
-10
0
10
20
-50
-70
-60
-80
15.0 18.0
RESOLUTION BW = 100kHz
VIDEO BW = 100kHz
ATTENUATION = 50dB
RxOUT_ POWER SPECTRUM
vs. FREQUENCY
(RxCLKIN_ = 16MHz, NO SPREAD)
MAX9242 toc16
FREQUENCY (MHz)
POWER SPECTRUM (dBm)
8
-40
-30
-20
-10
0
10
20
-50
-70
-60
-80
79
RESOLUTION BW = 100kHz
VIDEO BW = 100kHz
ATTENUATION = 50dB
RxOUT_ POWER SPECTRUM
vs. FREQUENCY
(RxCLKIN_ = 16MHz, 2% SPREAD)
MAX9242 toc17
FREQUENCY (MHz)
POWER SPECTRUM (dBm)
8
-40
-30
-20
-10
0
10
20
-50
-70
-60
-80
79
RESOLUTION BW = 100kHz
VIDEO BW = 100kHz
ATTENUATION = 50dB
RxOUT_ POWER SPECTRUM
vs. FREQUENCY
(RxCLKIN_ = 16MHz, 4% SPREAD)
MAX9242 toc18
FREQUENCY (MHz)
POWER SPECTRUM (dBm)
8
-40
-30
-20
-10
0
10
20
-50
-70
-60
-80
79
RESOLUTION BW = 100kHz
VIDEO BW = 100kHz
ATTENUATION = 50dB
MAX9242/MAX9244/MAX9246/MAX9254
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
______________________________________________________________________________________ 11
Pin Description
PIN NAME FUNCTION
1 RxOUT17
2 RxOUT18
3, 25, 32,
38, 44
4 RxOUT19
5 RxOUT20
6 SSG
7 DCB
8 RxIN0- Inverting Channel 0 LVDS Serial-Data Input
9 RxIN0+ Noninverting Channel 0 LVDS Serial-Data Input
10 RxIN1- Inverting Channel 1 LVDS Serial-Data Input
11 RxIN1+ Noninverting Channel 1 LVDS Serial-Data Input
12 LVDSV
13, 18 LVDSGND LVDS Ground
14 RxIN2- Inverting Channel 2 LVDS Serial-Data Input
15 RxIN2+ Noninverting Channel 2 LVDS Serial-Data Input
16 RxCLKIN- Inverting LVDS Parallel-Rate Clock Input
17 RxCLKIN+ Noninverting LVDS Parallel-Rate Clock Input
19, 21 PLLGND PLL Ground
20 PLLV
22 PWRDWN
23 RxCLKOUT
24 RxOUT0
26 RxOUT1
27 RxOUT2
28, 36, 48 V
29 RxOUT3
30 RxOUT4
31 RxOUT5
33 RxOUT6
GND Ground
CCO
Channel 2 Single-Ended Outputs
Channel 2 Single-Ended Outputs
Three-Level-Logic, Spread-Spectrum Generator Control Input. SSG selects the frequency spread of
RxCLKOUT relative to RxCLKIN_ (see Table 3).
Three-Level-Logic, DC-Balance Control Input. DCB selects DC-balanced, non-DC-balanced, or reserved
operation (see Table 1).
LVDS Supply Voltage. Bypass LVDSV
CC
the pin as possible.
PLL Supply Voltage. Bypass PLLVCC to GND with 0.1µF and 0.001µF capacitors in parallel as close to
CC
the pin as possible.
5V-Tolerant LVTTL/LVCMOS Power-Down Input. PWRDWN is internally pulled down to GND. Outputs are
high impedance when PWRDWN = low or open.
P ar al l el - Rate C l ock S i ng l e- E nd ed O utp ut. The M AX 9242 has a r i si ng - ed g e str ob e. The M AX 9244/M AX 9246/
M AX 9254 have a fal l i ng - ed g e str ob e.
Channel 0 Single-Ended Outputs
Output Supply Voltage. Bypass each V
close to the pin as possible.
Channel 0 Single-Ended Outputs
to GND with 0.1µF and 0.001µF capacitors in parallel as close to
CC
to GND with 0.1µF and 0.001µF capacitors in parallel as
CCO
MAX9242/MAX9244/MAX9246/MAX9254
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
12 ______________________________________________________________________________________
Functional Diagram
Pin Description (continued)
PIN NAME FUNCTION
34 RxOUT7
35 RxOUT8
37 RxOUT9
39 RxOUT10
40 RxOUT11
41 RxOUT12
42 V
CC
43 RxOUT13 Channel 1 Single-Ended Output
45 RxOUT14
46 RxOUT15
47 RxOUT16
Channel 1 Single-Ended Outputs
Digital Supply Voltage. Bypass VCC to GND with 0.1µF and 0.001µF capacitors in parallel as close to the
pin as possible.
Channel 2 Single-Ended Outputs
CHANNEL 0
RxIN0+
RxIN0-
RxIN1+
RxIN1-
RxIN2+
RxIN2-
RxCLKIN+
RxCLKIN-
DCB
SERIAL-TO-PARALLEL
CHANNEL 1
SERIAL-TO-PARALLEL
CHANNEL 2
SERIAL-TO-PARALLEL
7x OR 9x STROBES
PLL1
PARALLEL
CLOCK
FIFO
CLKINCLK
FIFO
CONTROL
OUT
77
77
77
RxOUT0–RxOUT6
RxOUT7–RxOUT13
RxOUT14–RxOUT20
MAX9242
MAX9244
MAX9246
MAX9254
PWRDWN
SPREAD-
SPECTRUM
PLL (SSPLL)
SSG
RxCLKOUT
MAX9242/MAX9244/MAX9246/MAX9254
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
______________________________________________________________________________________ 13
Detailed Description
The MAX9242/MAX9244/MAX9246/MAX9254 deserialize
three LVDS serial-data inputs into 21 single-ended LVCMOS/LVTTL outputs. The outputs are programmable for
no spread or for a spread of ±2% or ±4%, relative to the
LVDS input clock frequency. The MAX9242/MAX9244/
MAX9254 operate at a parallel clock frequency of 16MHz
to 34MHz in DC-balanced mode and 20MHz to 40MHz in
non-DC-balanced mode. The MAX9246 operates at a
6MHz-to-18MHz parallel clock frequency in DC-balanced
mode and 8MHz-to-20MHz parallel clock frequency in
non-DC-balanced mode. DC-balanced or non-DC-balanced operation is controlled by the DCB input. The
MAX9242 has a rising-edge strobe and the MAX9244/
MAX9246/MAX9254 have a falling-edge strobe.
DC Balance (DCB)
DC-balanced or non-DC-balanced operation is controlled by the DCB input (see Table 1). In the non-DCbalanced mode, each channel deserializes 7 bits every
cycle of the parallel clock. In DC-balanced mode, 9 bits
are deserialized every clock cycle (7 data bits + 2
DC-balanced bits). The highest serial-data rate on each
channel in DC-balanced mode is 34MHz x 9 = 306Mbps.
In non-DC-balanced mode, the maximum data rate is
40MHz x 7 = 280Mbps.
Data coding by the MAX9209/MAX9213 serializers (that
are companion devices to the MAX9242/MAX9244/
MAX9246/MAX9254 deserializers) limits the imbalance
of ones and zeros transmitted on each channel. If +1 is
assigned to each binary 1 transmitted and -1 is
assigned to each binary 0 transmitted, the variation in
the running sum of assigned values is called the digital
sum variation (DSV). The maximum DSV for the data
channels is 10. At most, 10 more zeros than ones, or 10
more ones than zeros, are ever transmitted. The maximum DSV for the clock channel is 5. Limiting the DSV
and choosing the correct coupling capacitors maintain
differential signal amplitude and reduces jitter due to
droop on AC-coupled links.
To obtain DC balance on the data channels, the serializer parallel data is inverted or not inverted, depending
on the sign of the digital sum at the word boundary.
Two complementary bits are appended to each group
of 7 parallel-input data bits to indicate to the MAX9242/
MAX9244/MAX9246/MAX9254 deserializer whether the
data bits are inverted (see Figures 11 and 12). The
deserializer restores the original state of the parallel
data. The LVDS clock signal alternates duty cycles of
4/9 and 5/9 to maintain DC balance.
Spread-Spectrum Generator (SSG)
The MAX9242/MAX9244/MAX9246/MAX9254 singleended data and clock outputs are programmable for a
variation of ±2% or ±4% around the LVDS input clock frequency. The modulation rate of the frequency variation is
32.48kHz for a 33MHz LVDS clock input and scales linearly with the input clock frequency (see Table 2). The
spread spectrum can also be turned off. The output
spread is controlled through the SSG input (see Table 3).
Table 1. DCB Function
DCB INPUT LEVEL FUNCTION
High Non-DC-balanced mode
Mid Reserved
Low DC-balanced mode
Figure 11. Deserializer Serial Input in Non-DC-Balanced Mode
+
RxCLKIN_
TxIN14TxIN15
RxIN2_
TxIN7TxIN8
RxIN1_
TxIN1
TxIN0
RxIN0_
TxIN_ IS DATA FROM THE SERIALIZER.
CYCLE N + 1CYCLE NCYCLE N - 1
TxIN14TxIN15TxIN16TxIN20 TxIN17TxIN18TxIN19
TxIN9TxIN13 TxIN10TxIN11TxIN12
TxIN2TxIN6 TxIN3TxIN4TxIN5
TxIN7TxIN8
TxIN0TxIN1
TxIN14TxIN15TxIN16TxIN20 TxIN17TxIN18TxIN19
TxIN7TxIN8TxIN9TxIN13 TxIN10TxIN11TxIN12
TxIN0TxIN1TxIN2TxIN6 TxIN3TxIN4TxIN5
MAX9242/MAX9244/MAX9246/MAX9254
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
To select the mid level, leave the input open, or if driven,
put the driver output in high impedance. The driver highimpedance leakage current must be less than ±10µA.
Any spread change causes a maximum delay time of
32,800 x RCIP before output data is valid. When the
spread amount is changed from ±2% to ±4% or viceversa, the data outputs go low for one delay time (see
Figure 13). Similarly, when the spread is changed from
no spread to ±2% or ±4%, the data outputs go low for
one delay time (see Figure 14). The data outputs continue to switch but are not valid when the spread amount is
changed from ±2% or ±4% to no spread (see Figure
15). The spread-spectrum function is also available
when the MAX9242/MAX9244/MAX9246/MAX9254 operate in non-DC-balanced mode.
Hot Swap
When the MAX9242/MAX9244/MAX9246/MAX9254 are
connected to an active serializer, they synchronize correctly. The PLL control voltage does not saturate in response to
high-frequency glitches that may occur during a hot swap.
The PWRDWN input on the MAX9242/MAX9244/MAX9246/
MAX9254 does not need to be cycled when these devices
are connected to an active serializer.
PLL Lock Time
The MAX9242/MAX9244/MAX9246/MAX9254 use two
PLLs. The first PLL (PLL1) generates a 7x clock (non-DCbalanced mode) or a 9x clock (DC-balanced mode) from
RxCLKIN_ for deserializing the LVDS inputs. The second
PLL (SSPLL) is used for spread-spectrum modulation.
During initial power-up, the PLL1 locks, and SSPLL locks
immediately after. The PLL lock times are set by an internal counter. The maximum time to lock for each PLL is
32,800 clock periods. Power and clock should be stable
to meet the lock time specification. After initialization, if
the first PLL loses lock, it locks again and then the
Figure 12. Deserializer Serial Input in DC-Balanced Mode
Table 2. Modulation Rate
Table 3. SSG Function
Note: RxOUT_ data outputs are spread because RxCLKOUT
strobes the output of the FIFO.
14 ______________________________________________________________________________________
+
RxCLKIN_
CYCLE N + 1CYCLE NCYCLE N - 1
DCB2DCA2
RxIN2_
TxIN14TxIN15TxIN16TxIN20 TxIN17TxIN18TxIN19
TxIN15
TxIN16TxIN17TxIN18DCA2 TxIN19TxIN20DCB2
TxIN14
DCB1DCA1
RxIN1_
DCA0
DCB0
RxIN0_
TxIN_, DCA_, AND DCB_ ARE DATA FROM THE SERIALIZER.
TxIN9TxIN13 TxIN10TxIN11TxIN12
TxIN2TxIN6 TxIN3TxIN4TxIN5
TxIN7TxIN8
TxIN0TxIN1
f
RxCLKIN_
(MHz) fM (kHz) = f
6 5.91
8 7.87
10 9.84
16 15.75
18 17.72
20 19.68
33 32.48
34 33.46
40 39.37
RxCLKIN_
/ 1016
SSG INPUT LEVEL FUNCTION
High
Mid
Low
RxCLKOUT frequency spread
±4% relative to RxCLKIN_
RxCLKOUT frequency spread
±2% relative to RxCLKIN_
No spread on RxCLKOUT
relative to RxCLKIN_
TxIN8
TxIN1
TxIN7
TxIN0
TxIN9TxIN10TxIN11DCA1 TxIN12TxIN13DCB1
TxIN2TxIN3TxIN4DCA0 TxIN5TxIN6DCB0
MAX9242/MAX9244/MAX9246/MAX9254
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
______________________________________________________________________________________ 15
spread-spectrum PLL locks immediately after (see
Figure 16). If the spread-spectrum PLL loses lock, it
locks again with only one PLL lock delay (see Figure 17).
AC-Coupling Benefits
Bit errors experienced with DC-coupling (Figure 18)
can be eliminated by increasing the receiver commonmode voltage range through AC-coupling. AC-coupling
increases the common-mode voltage range of an LVDS
receiver to nearly the voltage rating of the capacitor. The
typical LVDS driver output is 350mV centered on a 1.25V
offset voltage, making single-ended output voltages of
1.425V and 1.075V. An LVDS receiver accepts signals
from 0V to 2.4V, allowing approximately ±1V commonmode difference between the driver and receiver on a
Figure 13. Output Waveforms when Spread Amount is Changed
Figure 14. Output Waveforms when Spread is Added
Figure 15. Output Waveforms when Spread is Removed
SSG
RxCLKOUT
RxOUT_
NO SPREADSSG
RxCLKOUT
RxOUT_
±2% OR ±4% SPREAD±4% OR ±2% SPREAD
RPLLS2 (32,800 x RCIP)
±2% OR ±4% SPREAD
RPLLS2 (32,800 x RCIP)
LOW
LOW
RPLLS2 (32,800 x RCIP)
RxCLKOUT
RxOUT_
DATA SWITCHING BUT NOT VALID
NO SPREAD±4% OR ±2% SPREADSSG
MAX9242/MAX9244/MAX9246/MAX9254
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
16 ______________________________________________________________________________________
DC-coupled link (2.4V - 1.425V = 0.975V and 1.075V 0V = 1.075V). Common-mode voltage differences may
be due to ground potential variation or common-mode
noise. If there is more than ±1V of difference, the receiver
is not guaranteed to read the input signal correctly and
may cause bit errors. AC-coupling filters low-frequency
ground shifts and common-mode noise and passes
high-frequency data. A common-mode voltage difference up to the voltage rating of the coupling capacitor
(minus half the differential swing) is tolerated. DC-balanced coding of the data is required to maintain the
differential signal amplitude and limit jitter on an
AC-coupled link. A capacitor in series with each output
of the LVDS driver is sufficient for AC-coupling. However,
two capacitors—one at the serializer output and one at
the deserializer input—provide protection in case either
end of the cable is shorted to a high voltage.
Applications Information
Selection of AC-Coupling Capacitors
Voltage droop and the DSV of transmitted symbols
cause signal transitions to start from different voltage
levels. Because the transition time is finite, starting the
signal transition from different voltage levels causes
timing jitter. The time constant for an AC-coupled link
needs to be chosen to reduce droop and jitter to an
acceptable level.
The RC network for an AC-coupled link consists of the
LVDS receiver termination resistor (RT), the LVDS driver
output resistor (RO), and the series AC-coupling capacitors (C). The RC time constant for two equal-value
series capacitors is (C x (RT + RO)) / 2 (Figure 19). The
RC time constant for four equal-value series capacitors
is (C x (RT + RO)) / 4 (Figure 20).
Figure 16. Output Waveforms when PLL1 Loses Lock and Locks Again
Figure 17. Output Waveforms if Spread-Spectrum PLL Loses Lock and Locks Again
RPLLS (65,600 x RCIP)
INTERNAL
PLL1 LOCK
INTERNAL
SSPLL LOCK
RxCLKOUT
RxOUT_
INTERNAL
SSPLL LOCK
RxCLKOUT
RxOUT_
TIMING SHOWN FOR STABLE CLOCK AND DATA INPUTS
LOW
LOW
RPLLS2 (32,800 x RCIP)
LOW
LOW
LOW
MAX9242/MAX9244/MAX9246/MAX9254
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
______________________________________________________________________________________ 17
RTis required to match the transmission line impedance
(usually 100Ω) and ROis determined by the LVDS driver design (the minimum differential output resistance of
78Ω for the MAX9209/MAX9213 serializers is used in
the following example). This condition leaves the capacitor selection to change the system time constant.
In the following example, the capacitor value for a 2%
droop is calculated. Jitter due to this droop is then calculated assuming a 1ns transition time:
C = -(2 x t
B
x DSV) / (ln (1 - D) x (RT+ RO)) (Eq 1)
where:
C = AC-coupling capacitor (F)
tB= bit time (s)
DSV = digital sum variation (integer)
ln = natural log
D = droop (% of signal amplitude)
R
T
= termination resistor (Ω)
R
O
= output resistance (Ω)
Equation 1 is for two series capacitors (Figure 19). The bit
time (t
B
) is the period of the parallel clock divided by 9.
The DSV is 10. See equation 3 for four series capacitors
(Figure 20).
The capacitor for 2% maximum droop at 16MHz parallel
rate clock is:
C = -(2 x t
B
x DSV) / (ln (1 - D) x (RT+ RO))
C = -(2 x 6.95ns x 10) / (ln (1 - 0.02) x (100Ω + 78Ω))
C = 0.038µF
Jitter due to droop is proportional to the droop and
transition time:
t
J
= tTx D (Eq 2)
where:
t
J
= jitter (s)
t
T
= transition time (s) (0 to 100%)
D = droop (% of signal amplitude)
Jitter due to 2% droop and assumed 1ns transition time is:
t
J
= 1ns x 0.02
tJ= 20ps
The transition time in a real system depends on the frequency response of the cable driven by the serializer.
Figure 18. DC-Coupled Link, Non-DC-Balanced Mode
TxIN
PWRDWN
TxCLK IN
MAX9209/MAX9213 MAX9242/MAX9244/MAX9246/MAX9254
TxOUT
R
7
7:1
7
7:1
7
7:1
PLL
21:3 SERIALIZER 3:21 DESERIALIZER
O
TxCLK OUT
TRANSMISSION LINE
100Ω
100Ω
100Ω
100Ω
RxIN__
R
T
RxCLK IN
1:7 FIFO
1:7 FIFO
1:7 FIFO
PLL1 +
SSPLL
7
7
RxOUT_
7
PWRDWN
RxCLK OUT
MAX9242/MAX9244/MAX9246/MAX9254
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
18 ______________________________________________________________________________________
The capacitor value decreases for a higher frequency
parallel clock and for higher levels of droop and jitter.
Use high-frequency, surface-mount ceramic capacitors.
Equation 1 altered for four series capacitors (Figure 20) is:
C = -(4 x t
B
x DSV) / (ln (1 - D) x (RT+ RO)) (Eq 3)
Fail-Safe
The MAX9242/MAX9244/MAX9246/MAX9254 have failsafe LVDS inputs in non-DC-balanced mode (Figure 1).
Fail-safe drives the outputs low when the corresponding
LVDS input is open, undriven and shorted, or undriven
and parallel terminated. The fail-safe on the LVDS clock
input drives all outputs low when power is stable. Failsafe does not operate in DC-balanced mode.
Input Bias and Frequency Detection
In DC-balanced mode, the inverting and noninverting
LVDS inputs are internally connected to +1.2V through
42kΩ (min) to provide biasing for AC-coupling (Figure 1).
To prevent switching due to noise when the clock input
is not driven, bias the clock inputs (RxCLKIN+,
RxCLKIN-) to differential +15mV by connecting a 10kΩ
±1% pullup resistor between the noninverting input and
LVDSVCC, and a 10kΩ ±1% pulldown resistor between
the inverting input and ground. These bias resistors,
along with the 100Ω ±1% tolerant termination resistor,
provide +15mV of differential input. The +15mV bias
causes some small degradation of RSKM proportional to
the slew rate of the clock input. For example, if the clock
transitions 250mV in 500ps, the slew rate of 0.5mV/ps
reduces RSKM by 30ps.
Unused LVDS Data Inputs
In non-DC-balanced mode, leave unused LVDS data
inputs open. In non-DC-balanced mode, the input failsafe circuit drives the corresponding outputs low, and no
pullup or pulldown resistors are needed. In DC-balanced
mode, at each unused LVDS data input, pull the inverting
input up to LVDSVCCusing a 10kΩ resistor, and pull the
noninverting input down to ground using a 10kΩ resistor.
Do not connect a termination resistor. The pullup and
pulldown resistors drive the corresponding outputs low
and prevent switching due to noise.
Figure 19. Two Capacitors per Link, AC-Coupled, DC-Balanced Mode
HIGH-FREQUENCY, CERAMIC
SURFACE-MOUNT CAPACITORS
MAX9209/MAX9213 MAX9242/MAX9244/MAX9246/MAX9254
CAN ALSO BE PLACED AT THE
SERIALIZER INSTEAD OF THE DESERIALIZER.
TxOUT
RxIN__
R
100Ω
100Ω
100Ω
100Ω
RxCLK IN
T
1:(9 - 2)
+ FIFO
1:(9 - 2)
+ FIFO
1:(9 - 2)
+ FIFO
PLL1 +
SSPLL
TxIN
PWRDWN
TxCLK IN
R
7
(7 + 2):1
7
(7 + 2):1
7
(7 + 2):1
PLL
21:3 SERIALIZER 3:21 DESERIALIZER
O
TxCLK OUT
7
7
RxOUT_
7
PWRDWN
RxCLK OUT
MAX9242/MAX9244/MAX9246/MAX9254
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
______________________________________________________________________________________ 19
Link Power-Up Sequence
The recommended link power-up sequence is to power
up the serializer, wait until the serializer PLL locks, and
then power up the deserializer. This sequence prevents
the deserializer from seeing an undriven or unstable
input when powering up.
PWRDWN
Driving PWRDWN low puts the outputs in high impedance, stops the PLL, and reduces supply current to
50µA or less. Driving PWRDWN high drives the outputs
low until the PLL locks. The outputs of two deserializers
can be bused to form a 2:1 mux with the outputs controlled by PWRDWN. Wait 100ns between disabling one
deserializer (driving PWRDWN low) and enabling the
second one (driving PWRDWN high) to avoid contention of the bused outputs.
Power-Supply Bypassing
There are separate on-chip power domains for digital
circuits, outputs, PLL, and LVDS inputs. Bypass each
VCC, V
CCO
, PLLVCC, and LVDSVCCwith high-frequency,
surface-mount ceramic 0.1µF and 0.001µF capacitors in
parallel as close to the device as possible, with the
smallest value capacitor closest to the supply pin.
Cables and Connectors
Interconnect for LVDS typically has a differential impedance of 100Ω. Use cables and connectors that have
matched differential impedance to minimize impedance
discontinuities.
Twisted-pair and shielded twisted-pair cables offer
superior signal quality compared to ribbon cable and
tend to generate less EMI due to magnetic field canceling effects. Balanced cables pick up noise as common
mode, which is rejected by the LVDS receiver.
Board Layout
Keep the LVTTL/LVCMOS outputs and LVDS input signals separated to prevent crosstalk. A four-layer PC
board with separate layers for power, ground, LVDS
inputs, and digital signals is recommended. Layout PC
board traces for 100Ω differential characteristic impedance. The trace dimensions depend on the type of
Figure 20. Four Capacitors per Link, AC-Coupled, DC-Balanced Mode
TxIN
PWRDWN
TxCLK IN
HIGH-FREQUENCY CERAMIC
MAX9209/MAX9213 MAX9242/MAX9244/MAX9246/MAX9254
7
(7 + 2):1
7
(7 + 2):1
7
(7 + 2):1
PLL
21:3 SERIALIZER 3:21 DESERIALIZER
SURFACE-MOUNT CAPACITORS
TxOUT
R
O
TxCLK OUT
RxIN__
R
100Ω
100Ω
100Ω
100Ω
RxCLK IN
T
1:(9 - 2)
+ FIFO
1:(9 - 2)
+ FIFO
1:(9 - 2)
+ FIFO
PLL1 +
SSPLL
7
7
RxOUT_
7
PWRDWN
RxCLK OUT
MAX9242/MAX9244/MAX9246/MAX9254
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
20 ______________________________________________________________________________________
trace used (microstrip or stripline). Note that two 50Ω
PC board traces do not have 100Ω differential impedance when brought close together—the impedance
goes down when the traces are brought closer.
Route the PC board traces for an LVDS channel (there
are two conductors per LVDS channel) in parallel to
maintain the differential characteristic impedance.
Place the termination resistor at the end of the PC
board traces within a 1/4 inch of the LVDS receiver
input. Avoid vias. If vias must be used, use only one
pair per LVDS channel and place the via for each line
at the same point along the length of the PC board
traces. This way, any reflections will occur at the same
time. Do not make vias into test points for ATE. Make
LVDS clock and data pairs the same length on the PC
board to avoid pair-to-pair skew. Make the PC board
traces that make up a differential pair the same length
to avoid skew within the differential pair.
5V-Tolerant Input
PWRDWN is 5V tolerant and is internally pulled down to
GND. SSG and DCB are not 5V tolerant. The input voltage
range for SSG and DCB is nominally ground to VCC.
Skew Margin (RSKM)
Skew margin (RSKM) is the time allowed for degradation of the serial-data sampling setup and hold times by
sources other than the deserializer. The deserializer
sampling uncertainty is accounted for and does not
need to be subtracted from RSKM. The main outside
contributors of jitter and skew that subtract from RSKM
are interconnect intersymbol interference, serializer
pulse position uncertainty, and pair-to-pair path skew.
V
CCO
Output Supply and Power Dissipation
The outputs have a separate supply (V
CCO
) for interfacing
to systems with 1.8V to 5V nominal input logic levels. The
DC Electrical Characteristics
table gives the maximum
supply current for V
CCO
= 3.6V with 8pF load at several
switching frequencies with all outputs switching in the
worst-case switching pattern. The approximate incremental supply current for V
CCO
other than 3.6V with the same
8pF load and worst-case pattern can be calculated using:
II= CTVI0.5fCx 21 (data outputs)
+ CTVIfCx 1 (clock output)
where:
II= incremental supply current
CT= total internal (C
INT
) and external (CL) load capacitance
VI= incremental supply voltage
fC= output clock switching frequency
The incremental current is added to (for V
CCO
> 3.6V)
or subtracted from (for V
CCO
< 3.6V) the
DC Electrical
Characteristics
table maximum supply current. The
internal output buffer capacitance is C
INT
= 6pF. The
worst-case pattern switching frequency of the data outputs is half the switching frequency of the output clock.
In the following example, the incremental supply current
of the MAX9244 in spread and DC-balanced mode is calculated for V
CCO
= 5.5V, fC= 34MHz, and CL= 8pF:
V
I
= 5.5V - 3.6V = 1.9V
CT= C
INT
+ CL= 6pF + 8pF = 14pF
where:
II= CTVI0.5fCx 21 (data outputs) + CTVIfCx 1 (clock
output)
II= (14pF x 1.9V x 0.5 x 34MHz x 21) + (14pF x 1.9V x
34MHz)
II= 9.5mA + 0.9mA = 10.4mA.
The maximum supply current in DC-balanced mode for
V
CC
= V
CCO
= 3.6V at fC= 34MHz is 125mA (from the
DC Electrical Characteristics
table). Add 10.4mA to get
the total approximate maximum supply current at V
CCO
= 5.5V and VCC= 3.6V.
If the output supply voltage is less than V
CCO
= 3.6V,
the reduced supply current can be calculated using the
same formula and method.
At high switching frequency, high supply voltage, and
high capacitive loading, power dissipation can exceed
the package power dissipation rating. Do not exceed
the maximum package power dissipation rating. See
the
Absolute Maximum Ratings
for maximum package
power dissipation capacity and temperature derating.
Rising- or Falling-Edge Output Strobe
The MAX9242 has a rising-edge output strobe, which
latches the parallel output data into the next chip on the
rising edge of RxCLKOUT. The MAX9244/MAX9246/
MAX9254 have a falling-edge output strobe, which
latches the parallel output data into the next chip on the
falling edge of RxCLKOUT. The deserializer output
strobe polarity does not need to match the serializer
input strobe polarity.
Three-Level Logic Inputs
SSG and DCB (DCB mid level is reserved) are threelevel-logic inputs. A logic-high input voltage must be
greater than +2.5V and a logic-low input voltage must
be less than +0.8V. A mid-level logic is recognized by
the MAX9242/MAX9244/MAX9246/MAX9254 when the
input is left open or connected to a driver in a highimpedance state. A weak inverter on the input stage of
MAX9242/MAX9244/MAX9246/MAX9254
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
______________________________________________________________________________________ 21
SSG and DCB provides the proper mid-level voltage
under conditions of low input current. The mid-level
input current must not be greater than ±10µA, and the
mid-level logic state cannot be driven with an external
voltage source.
IEC 61000-4-2 Level 4 and ISO 10605
ESD Protection
The MAX9242/MAX9244/MAX9246/MAX9254 ESD tolerance is rated for Human Body Model, IEC 61000-4-2
and ISO 10605. The ISO 10605 and IEC 61000-4-2
standards specify ESD tolerance for electronic systems. All LVDS inputs on the MAX9242/MAX9244/
MAX9246/MAX9254 meet ISO 10605 ESD protection at
±30kV Air-Gap Discharge and ±6kV Contact Discharge
and IEC 61000-4-2 ESD protection at ±15kV Air-Gap
Discharge and ±8kV Contact Discharge. All other pins
meet the Human Body Model ESD tolerance of ±2.5kV.
The Human Body Model discharge components are C
S
= 100pF and RD= 1.5kΩ (Figure 21). The IEC 61000-42 discharge components are CS= 150pF and RD=
330Ω (see Figure 22). The ISO 10605 discharge components are CS= 330pF and RD= 2kΩ (Figure 23).
Figure 21. Human Body ESD Test Circuit
Figure 22. IEC 61000-4-2 Contact Discharge ESD Test Circuit
Figure 23. ISO 10605 Contact Discharge ESD Test Circuit
Pin Configuration
Chip Information
PROCESS: CMOS
R
D
1.5kΩ
CHARGE-CURRENT-
DC
LIMIT RESISTOR
100pF
HIGH-
VOLTAGE
SOURCE
CHARGE-CURRENT-
LIMIT RESISTOR
HIGH-
VOLTAGE
DC
SOURCE
150pF
DISCHARGE
RESISTANCE
C
S
STORAGE
CAPACITOR
R2
330Ω
DISCHARGE
RESISTANCE
C
S
STORAGE
CAPACITOR
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
R
D
2kΩ
HIGH-
VOLTAGE
DC
SOURCE
CHARGE-CURRENT-
LIMIT RESISTOR
330pF
DISCHARGE
RESISTANCE
C
S
STORAGE
CAPACITOR
TOP VIEW
1
RxOUT17
RxOUT18
GND
RxOUT20
SSG
DCB
RxIN0+
RxIN1+
LVDSV
CC
LVDSGND
RxIN2-
RxIN2+
RxCLKIN-
RxCLKIN+
LVDSGND
PLLGND
PLLVCC
PLLGND
PWRDWN
RxOUT0 24
2
3
4
5
6
7
8
9
10
11
12
MAX9242
13
MAX9244
MAX9246
14
MAX9254
15
16
17
18
19
20
21
22
23RxCLKOUT
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
V
CCO
RxOUT16
RxOUT15
RxOUT14RxOUT19
GND
RxOUT13
V
CC
RxOUT12RxIN0-
RxOUT11
RxOUT10RxIN1-
GND
RxOUT9
V
CCO
RxOUT8
RxOUT7
RxOUT6
GND
RxOUT5
RxOUT4
RxOUT3
V
CCO
RxOUT2
RxOUT1
GND
DEVICE
UNDER
TEST
TSSOP
MAX9242/MAX9244/MAX9246/MAX9254
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
22 ______________________________________________________________________________________
Ordering Information (continued)
+
Denotes a lead(Pb)-free/RoHS-compliant package.
/V denotes an automotive qualified part.
Note: All devices are available in lead(Pb)-free/RoHS-compliant
packaging. Specify lead(Pb)-free/RoHS compliant by adding a
+ symbol at the end of the part number when ordering.
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages
. Note that a “+”, “#”, or “-” in
the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
48 TSSOP U48-1
21-0155
PART TEMP RANGE PIN-PACKAGE
MAX9246EUM -40°C to +85°C 48 TSSOP
MAX9246EUM/V+ -40°C to +85°C 48 TSSOP
MAX9246GUM -40°C to +105°C 48 TSSOP
MAX9246GUM/V+ -40°C to +105°C 48 TSSOP
MAX9254EUM -40°C to +85°C 48 TSSOP
MAX9254EUM/V+ -40°C to +85°C 48 TSSOP
MAX9242/MAX9244/MAX9246/MAX9254
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________
23
© 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
3 2/09
4 7/09 Added automotive qualified parts to Ordering Information table 1
REVISION
DATE
DESCRIPTION
Supply currents measured before the deserializers were fully locked to incoming
serial data. DC Electrical Characteristics updated
PAGES
CHANGED
2, 3
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