Maxim MAX9235 Datasheet

General Description

The MAX9235 serializer transforms 10-bit-wide parallel
LVCMOS/LVTTL data into a serial high-speed, low-volt­age differential signaling (LVDS) data stream. The seri­alizer typically pairs with deserializers like the
MAX9206, which receives the serial output and trans­forms it back to 10-bit-wide parallel data.

The MAX9235 transmits serial data at speeds up to
450Mbps over PCB traces or twisted-pair cables. Since
the clock is recovered from the serial data stream,
clock-to-data and data-to-data skew that would be pre­sent with a parallel bus are eliminated.

The MAX9235 serializer requires no external compo­nents and no control signals and can lock to a 16MHz
to 45MHz system clock. The serializer output is held in
high impedance until the device is fully locked to the
local system clock.

The MAX9235 operates from a single +3.3V supply, is
specified for operation from -40°C to +105°C, and is
available in a 16-pin TQFN (3mm x 3mm) package.

Applications

Features

♦ Stand-Alone Serializer (vs. SERDES) Ideal for

Unidirectional Links

♦ Framing Bits for Deserializer Resync Allow Hot

Insertion Without System Interruption

♦ LVDS Serial Output Rated for Point-to-Point

Applications

♦ Wide Reference Clock Input Range

16MHz to 45MHz

♦ Low 31mA Supply Current

♦ 10-Bit Parallel LVCMOS/LVTTL Interface

♦ Up to 450Mbps Payload Data Rate

♦ Small 16-Pin TQFN (3mm x 3mm) Package

MAX9235

10-Bit LVDS Serializer

________________________________________________________________ Maxim Integrated Products 1

Ordering Information

19-0849; Rev 1; 12/07

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

Pin Configuration and Functional Diagram appear at end of
data sheet.

Typical Application Circuit

Lane Departures
Security Cameras

Rear View Cameras
Production Line Monitoring

+Denotes a lead-free package.

Note: The device is specified over the -40°C to +105°C temper­ature range.
*EP = Exposed pad.

PART

M AX 9235E TE + 16 TQFN-EP* 16 to 45 TI633-5

PIN­ PACKAGE

REF CLOCK

RANGE (MHz)

PKG
CODE

OUT+

IN_

TCLK

10

INPUT LATCH

PARALLEL-TO-SERIAL

TIMING AND

PLL

CONTROL

MAX9235 MAX9206

100Ω 100Ω

OUT-

LVDS

PCB OR

TWISTED PAIR

IN+

10

OUT_

IN-

TIMING AND

PLL

CLOCK

RECOVERY

OUTPUT LATCH

SERIAL-TO-PARALLEL

CONTROL

REFCLK
EN
LOCK

RCLK
RCLK_R/F

MAX9235

10-Bit LVDS Serializer

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

DC ELECTRICAL CHARACTERISTICS

(VCC= +3.0V to +3.6V, RL= 50Ω ±1%, CL= 10pF, TA= -40°C to +105°C. Typical values are at VCC= +3.3V and TA= +25°C,
unless otherwise noted.) (Notes 1, 2, 3)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

VCCto GND.........................................……………-0.3V to +4.0V

IN_, TCLK to GND ......................................-0.3V to (VCC+ 0.3V)

OUT+, OUT- to GND .............................................-0.3V to +4.0V

Output Short-Circuit Duration.....................................Continuous

Continuous Power Dissipation (T

A

= +70°C)

16-Pin TQFN (derate 14.7mW/°C above +70°C) ......1177mW

Storage Temperature Range .............................-65°C to +150°C

Junction Temperature......................................................+150°C

Operating Temperature Range .........................-40°C to +105°C

Lead Temperature (soldering, 10s) .................................+300°C

ESD Protection (Human Body Model, OUT+, OUT-) ...........±8kV

ESD Protection (Human Body Model, IN_, TCLK) ...............±2kV

LVCMOS/LVTLL LOGIC INPUTS (IN0 TO IN9, EN, TCLK)

High-Level Input Voltage V

Low-Level Input Voltage V

Input Current I

LVDS OUTPUTS (OUT+, OUT-)

Differential Output Voltage V

Change in VOD Between
Complementary Output States

Output Offset Voltage V

Change in V
Complementary Output States

Output Short-Circuit Current I

Power-Off Output Current I

POWER SUPPLY

Supply Current I

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

IH

IL

V

= 0 or V

IN_

Figure 1

Figure 1 1 35 mV

Figure 1

Figure 1 3 35 mV

OUT+ or OUT- = GND,
IN0 to IN9 = EN = V

VCC = 0, V

OUT+

Between

OS

ΔV

ΔV

IN

OD

OD

OS

OS

OS

OX

RL = 100Ω or 50Ω

CC

worst-case pattern
(Figures 2, 4)

2.0 V

GND 0.8 V

CC

or V

R

= 100Ω 600 735 950

L

R

= 50Ω 250 370 470

L

R

= 100Ω 1.025 1.265 1.375

L

R

= 50Ω 1.125 1.265 1.375

L

CC

= 0 or 3.6V -10 +10 µA

OUT-

-20 +20 µA

-13 -15 mA

16MHz 22 35

45MHz 31 45

CC

V

mV

V

mA

MAX9235

10-Bit LVDS Serializer

_______________________________________________________________________________________ 3

AC ELECTRICAL CHARACTERISTICS

(VCC= +3.0V to +3.6V, RL= 50Ω ±1%, CL= 5pF, TA= -40°C to +105°C. Typical values are at VCC= +3.3V and TA= +25°C, unless
otherwise noted.) (Notes 2, 4)

Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground

except V

OD

, ΔVOD, and VOS.

Note 2: C

L

includes scope probe and test jig capacitance.

Note 3: Parameters 100% tested at T

A

= +25°C. Limits over operating temperature range guaranteed by design and characterization.

Note 4: AC parameters are guaranteed by design and characterization.

TRANSMIT CLOCK (TCLK) TIMING REQUIREMENTS

TCLK Center Frequency f

TCLK Frequency Variation TCFV -200 +200 ppm

TCLK Period t

TCLK Duty Cycle TCDC 40 60 %

TCLK Input Transition Time t

TCLK Input Jitter t

SWITCHING CHARACTERISTICS

Low-to-High Transition Time t

High-to-Low Transition Time t

IN_ Setup to TCLK t

IN_ Hold from TCLK t

PLL Lock Time t

Bus LVDS Bit Width t

Serializer Delay t

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

TCCF

TCP

CLKT

JIT

LHT

HLT

S

H

PL

BIT

SD

Figure 3 3 6 ns

Figure 4

Figure 4

RL = 100Ω 370 500

R

= 50Ω 350 500

L

RL = 100Ω 370 500

R

= 50Ω 350 500

L

Figure 5 1 ns

Figure 5 3 ns

Figure 6

Figure 7 t

16 45 MHz

22.2 62.5 ns

150

2048 x

t

TCP

/6

TCP

t

TCP

2049 x

t

TCP

/12 ns

( t

/6)

TC P

+ 5

ps

(RMS)

ps

ps

ns

ns

MAX9235

10-Bit LVDS Serializer

4 _______________________________________________________________________________________

Figure 1. Output Voltage Definitions

Figure 2. Worst-Case ICCTest Pattern

Figure 3. Input Clock Transition Time Requirement

Figure 4. Output Load and Transition Times

Figure 5. Data Input Setup and Hold Times

R

OUT+

V

OUT-

L

2

OD

V

R

2

OS

L

TCLK

ODD IN_

EVEN IN_

TCLK

10%

OUT+

OUT-

5pF

R

5pF

V

= (OUT+) - (OUT-)

DIFF

L

90%

t

CLKT

V

DIFF

90%

10%

t

CLKT

80%

20%

t

LHT

t

80%

HLT

3V

0

V

= 0

DIFF

20%

t

TCP

TCLK

IN_

1.5V

1.5V

t

S

t

H

1.5V1.5V

1.5V