For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
General Description
The MAX9217 digital video parallel-to-serial converter
serializes 27 bits of parallel data into a serial data stream.
Eighteen bits of video data and 9 bits of control data are
encoded and multiplexed onto the serial interface, reducing the serial data rate. The data enable input determines
when the video or control data is serialized.
The MAX9217 pairs with the MAX9218 deserializer to
form a complete digital video serial link. Interconnect
can be controlled-impedance PCB traces or twisted-pair
cable. Proprietary data encoding reduces EMI and provides DC balance. DC balance allows AC-coupling,
providing isolation between the transmitting and receiving ends of the interface. The LVDS output is internally
terminated with 100Ω.
ESD tolerance is specified for ISO 10605 with ±10kV
contact discharge and ±30kV air discharge.
The MAX9217 operates from a +3.3V core supply and
features a separate input supply for interfacing to 1.8V
to 3.3V logic levels. This device is available in 48-lead
Thin QFN and LQFP packages and is specified from
-40°C to +85°C.
Applications
Navigation System Display
In-Vehicle Entertainment System
Video Camera
LCD Displays
Features
♦ Proprietary Data Encoding for DC Balance and
Reduced EMI
♦ Control Data Sent During Video Blanking
♦ Five Control Data Inputs Are Single-Bit-Error
Tolerant
♦ Output Common-Mode Filter Reduces EMI
♦ Greater than 10m STP Cable Drive
♦ Wide ±2% Reference Clock Tolerance
♦ ISO 10605 ESD Protection
♦ Separate Input Supply Allows Interface to 1.8V to
= +3.0V to +3.6V, RL= 100Ω ±1%, PWRDWN = high, TA= -40°C to +85°C, unless otherwise noted. Typical values are at
V
CC_
= +3.3V, TA= +25°C.) (Notes 1, 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
V
CC_
to _GND........................................................-0.5V to +4.0V
Any Ground to Any Ground...................................-0.5V to +0.5V
OUT+, OUT- to LVDS GND ...................................-0.5V to +4.0V
1, 13, 37GNDInput Buffer Supply and Digital Supply Ground
2V
3–10,
39–48
11, 12, 15–21CNTL_IN[8:0]
14, 38V
22DE_IN
23PCLK_IN
24, 25I.C.Internally connected to GND. Connect to GND or leave unconnected.
26PLL GNDPLL Supply Ground
27V
28PWRDWNLVTTL/LVCMOS Power-Down Input. Internally pulled down to GND.
29CMF
30, 31LVDS GNDLVDS Supply Ground
32OUT-Inverting LVDS Serial Data Output
33OUT+Noninverting LVDS Serial Data Output
34V
35RNG1
36RNG0
—EPExposed Pad (Thin QFN Package Only). Connect Thin QFN exposed pad to PCB GND.
CCIN
RGB_IN[17:0]
CC
CCPLL
CCLVDS
Input Buffer Supply Voltage. Bypass to GND with 0.1µF and 0.001µF capacitors in parallel as
close to the device as possible, with the smallest value capacitor closest to the supply pin.
LVTTL/LVCMOS Red, Green, and Blue Digital Video Data Inputs. Eighteen data bits are loaded
into the input latch on the rising edge of PCLK_IN when DE_IN is high. Internally pulled down to
GND.
LVTTL/LVCMOS Control Data Inputs. Control data are latched on the rising edge of PCLK_IN
when DE_IN is low. Internally pulled down to GND.
Digital Supply Voltage. Bypass to GND with 0.1µF and 0.001µF capacitors in parallel as close to
the device as possible, with the smallest value capacitor closest to the supply pin.
LVTTL/LVCMOS Data Enable Input. Logic-high selects RGB_IN[17:0] to be latched. Logic-low
selects CNTL_IN[8:0] to be latched. DE_IN must be switching for proper operation. Internally
pulled down to GND.
LVTTL/LVCMOS Parallel Clock Input. Latches data and control inputs and provides the PLL
reference clock. Internally pulled down to GND.
PLL Supply Voltage. Bypass to PLL GND with 0.1µF and 0.001µF capacitors in parallel as close
to the device as possible, with the smallest value capacitor closest to the supply pin.
Common-Mode Filter. Optionally connect a capacitor between CMF and ground to filter
common-mode switching noise.
LVDS Supply Voltage. Bypass to LVDS GND with 0.1µF and 0.001µF capacitors in parallel as
close to the device as possible, with the smallest value capacitor closest to the supply pin.
LVTTL/LVCMOS Frequency Range Select Input. Set to the frequency range that includes the
PCLK_IN frequency as shown in Table 3. Internally pulled down to GND.
LVTTL/LVCMOS Frequency Range Select Input. Set to the frequency range that includes the
PCLK_IN frequency as shown in Table 3. Internally pulled down to GND.
The MAX9217 DC-balanced serializer operates at a
parallel clock frequency of 3MHz to 35MHz, serializing
18 bits of parallel video data RGB_IN[17:0] when the
data enable input DE_IN is high, or 9 bits of parallel
control data CNTL_IN[8:0] when DE_IN is low. The
RGB video input data are encoded using 2 overhead
bits, EN0 and EN1, resulting in a serial word length of
20 bits (Table 1). Control inputs are mapped to 19 bits
and encoded with 1 overhead bit, EN0, also resulting in
a 20-bit serial word. Encoding reduces EMI and main-
tains DC balance across the serial cable. Two transition
words, which contain a unique bit sequence, are inserted at the transition boundaries of video-to-control and
control-to-video phases.
Control data inputs C0 to C4 are mapped to 3 bits each
in the serial control word (Table 2). At the deserializer,
2 or 3 bits at the same state determine the state of the
recovered bit, providing single bit-error tolerance for
C0 to C4. Control data that may be visible if an error
occurs, such as VSYNC and HSYNC, can be connected to these inputs. Control data inputs C5 to C8 are
mapped to 1 bit each.
Figure 8. Peak-to-Peak Output Offset Voltage
Bit 0 is the LSB and is serialized first. EN[1:0] are encoding bits. S[17:0] are encoded symbols.
Table 1. Serial Video Phase Word Format
Bit 0 is the LSB and is serialized first. C[8:0] are the control inputs.
The transition words require interconnect bandwidth
and displace control data. Therefore, control data is not
sampled (see Figure 9):
• Two clock cycles before DE_IN goes high.
• During the video phase.
• Two clock cycles after DE_IN goes low.
The last sampled control data are latched at the deserializer control data outputs during the transition and video
phases. Video data are latched at the deserializer RGB
data outputs during the transition and control phases.
Applications Information
AC-Coupling Benefits
AC-coupling increases the common-mode voltage to
the voltage rating of the capacitor. Two capacitors are
sufficient for isolation, but four capacitors—two at the
serializer output and two at the deserializer input—provide protection if either end of the cable is shorted to a
high voltage. AC-coupling blocks low-frequency
ground shifts and common-mode noise. The MAX9217
serializer can also be DC-coupled to the MAX9218
deserializer.
Figure 10 shows an AC-coupled serializer and deserializer with two capacitors per link, and Figure 11 is the
AC-coupled serializer and deserializer with four capacitors per link.
Selection of AC-Coupling Capacitors
See Figure 12 for calculating the capacitor values for
AC-coupling, depending on the parallel clock frequency. The plot shows capacitor values for two- and fourcapacitor-per-link systems. For applications using less
than 18MHz clock frequency, use 0.1µF capacitors.
Frequency-Range Setting RNG[1:0]
The RNG[1:0] inputs select the operating frequency
range of the MAX9217 serializer. An external clock within this range is required for operation. Table 3 shows
the selectable frequency ranges and corresponding
data rates for the MAX9217.
The MAX9217 has an integrated 100Ω output-termina-
tion resistor. This resistor damps reflections from
induced noise and mismatches between the transmission line impedance and termination resistors at the
deserializer input. With PWRDWN = low or with the supply off, the output termination is switched out and the
LVDS output is high impedance.
Common-Mode Filter
The integrated 100Ω output termination is made up of
two 50Ω resistors in series. The junction of the resistors
is connected to the CMF pin for connecting an optional
common-mode filter capacitor. Connect the filter
capacitor to ground close to the MAX9217 as shown in
Figure 13. The capacitor shunts common-mode switching current to ground to reduce EMI.
Figure 12. AC-Coupling Capacitor Values vs. Clock Frequency
of 18MHz to 35MHz
Driving PWRDWN low stops the PLL, switches out the
integrated 100Ω output termination, and puts the output
in high impedance to ground and differentially. With
PWRDWN ≤ 0.3V and all LVTTL/LVCMOS inputs ≤ 0.3V or
≥ V
CCIN
- 0.3V, supply current is reduced to 50µA or less.
Driving PWRDWN high starts PLL lock to PCLK_IN and
switches in the 100Ω output termination resistor. The
LVDS output is not driven until the PLL locks. The LVDS
output is high impedance to ground and 100Ω differen-
tial. The 100Ω integrated termination pulls OUT+ and
OUT- together while the PLL is locking so that V
OD
= 0V.
If V
CC
= 0, the output resistor is switched out and the LVDS
outputs are high impedance to ground and differentially.
PLL Lock Time
The PLL lock time is set by an internal counter. The lock
time is 16,385 PCLK_IN cycles. Power and clock should
be stable to meet the lock-time specification.
Input Buffer Supply
The single-ended inputs (RGB_IN[17:0], CNTL_IN[8:0],
DE_IN, RNG0, RNG1, PCLK_IN, and PWRDWN) are
powered from V
CCIN
. V
CCIN
can be connected to a
1.71V to 3.6V supply, allowing logic inputs with a nominal swing of V
CCIN
. If no power is applied to V
CCIN
when power is applied to VCC, the inputs are disabled
and PWRDWN is internally driven low, putting the
device in the power-down state.
Power-Supply Circuits and Bypassing
The MAX9217 has isolated on-chip power domains. The
digital core supply (VCC) and single-ended input supply
(V
CCIN
) are isolated but have a common ground (GND).
The PLL has separate power and ground (V
CCPLL
and
V
CCPLL
GND) and the LVDS input also has separate
power and ground (V
CCLVDS
and V
CCLVDS
GND). The
grounds are isolated by diode connections. Bypass each
VCC, V
CCIN
, V
CCPLL
, and V
CCLVDS
pin with high-frequency, surface-mount ceramic 0.1µF and 0.001µF capacitors
in parallel as close to the device as possible, with the
smallest value capacitor closest to the supply pin.
LVDS Output
The LVDS output is a current source. The voltage swing
is proportional to the termination resistance. The output
is rated for a differential load of 100Ω ±1%.
Cables and Connectors
Interconnect for LVDS typically has a differential impedance of 100Ω. Use cables and connectors that have
matched differential impedance to minimize impedance
discontinuities.
Twisted-pair and shielded twisted-pair cables offer
superior signal quality compared to ribbon cable and
tend to generate less EMI due to magnetic field canceling effects. Balanced cables pick up noise as common
mode, which is rejected by the LVDS receiver.
Separate the LVTTL/LVCMOS inputs and LVDS output to
prevent crosstalk. A four-layer PCB with separate layers
for power, ground, and signals is recommended.
ESD Protection
The MAX9217 ESD tolerance is rated for Human Body
Model, Machine Model, and ISO 10605. ISO 10605
specifies ESD tolerance for electronic systems. The
Human Body Model, Machine Model, discharge components are CS= 100pF and RD= 1.5kΩ (Figure 14).
The ISO 10605 discharge components are CS= 330pF
and RD= 2kΩ (Figure 15). The Machine Model discharge components are C
S
= 200pF and RD= 0Ω
(Figure 16).
Chip Information
PROCESS: CMOS
Figure 14. Human Body ESD Test Circuit
Figure 15. ISO 10605 Contact-Discharge ESD Test Circuit
Figure 16. Machine Model ESD Test Circuit
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages
.
PACKAGE TYPEPACKAGE CODEDOCUMENT NO.
48 LQFPC48+5
21-0054
48 TQFNT4866+1
21-0141
R
D
S
1.5kΩ
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
R
D
2kΩ
DEVICE
UNDER
TEST
1MΩ
CHARGE-CURRENT-
DC
LIMIT RESISTOR
C
100pF
HIGH-
VOLTAGE
SOURCE
50Ω TO 100Ω
R
D
0Ω
CHARGE-CURRENT-
DC
LIMIT RESISTOR
200pF
HIGH-
VOLTAGE
SOURCE
C
S
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
DEVICE
UNDER
TEST
HIGH-
VOLTAGE
DC
SOURCE
CHARGE-CURRENT-
LIMIT RESISTOR
330pF
C
S
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
DEVICE
UNDER
TEST
MAX9217
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
Revision History
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________