For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
General Description
The MAX9217 digital video parallel-to-serial converter
serializes 27 bits of parallel data into a serial data stream.
Eighteen bits of video data and 9 bits of control data are
encoded and multiplexed onto the serial interface, reducing the serial data rate. The data enable input determines
when the video or control data is serialized.
The MAX9217 pairs with the MAX9218 deserializer to
form a complete digital video serial link. Interconnect
can be controlled-impedance PCB traces or twisted-pair
cable. Proprietary data encoding reduces EMI and provides DC balance. DC balance allows AC-coupling,
providing isolation between the transmitting and receiving ends of the interface. The LVDS output is internally
terminated with 100Ω.
ESD tolerance is specified for ISO 10605 with ±10kV
contact discharge and ±30kV air discharge.
The MAX9217 operates from a +3.3V core supply and
features a separate input supply for interfacing to 1.8V
to 3.3V logic levels. This device is available in 48-lead
Thin QFN and LQFP packages and is specified from
-40°C to +85°C.
Applications
Navigation System Display
In-Vehicle Entertainment System
Video Camera
LCD Displays
Features
♦ Proprietary Data Encoding for DC Balance and
Reduced EMI
♦ Control Data Sent During Video Blanking
♦ Five Control Data Inputs Are Single-Bit-Error
Tolerant
♦ Output Common-Mode Filter Reduces EMI
♦ Greater than 10m STP Cable Drive
♦ Wide ±2% Reference Clock Tolerance
♦ ISO 10605 ESD Protection
♦ Separate Input Supply Allows Interface to 1.8V to
3.3V Logic
♦ +3.3V Core Supply
♦ Space-Saving Thin QFN and LQFP Packages
♦ -40°C to +85°C Operating Temperature
MAX9217
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
________________________________________________________________
Maxim Integrated Products
1
Pin Configurations
Ordering Information
19-3558; Rev 4; 8/09
EVALUATION KIT
AVAILABLE
+
Denotes a lead(Pb)-free/RoHS-compliant package.
/V denotes an automotive qualified part.
*
EP = Exposed pad.
PART TEMP RANGE
MAX9217ECM+ -40°C to +85°C 48 LQFP
MAX9217ECM/V+ -40°C to +85°C 48 LQFP
MAX9217ETM+ -40°C to +85°C 48 Thin QFN-EP*
PINPACKAGE
TOP VIEW
GND
V
RGB_IN0
RGB_IN1
RGB_IN2
RGB_IN3
RGB_IN4
RGB_IN5
RGB_IN6
RGB_IN7
RGB_IN8
RGB_IN9
37
38
CC
39
40
41
42
43
44
45
46
47
48
CCLVDS
RNG0
RNG1
V
OUT+
OUT-
LVDS GND
LVDS GND
CMF
PWRDWN
3635343332313029282726
MAX9217
+
123456789
CCIN
GND
V
RGB_IN10
RGB_IN11
RGB_IN12
RGB_IN13
RGB_IN14
RGB_IN15
RGB_IN16
LQFP
CCPLL
V
PLL GND
101112
RGB_IN17
CNTL_IN0
I.C.
25
24
23
22
21
20
19
18
17
16
15
14
13
CNTL_IN1
I.C.
PCLK_IN
DE_IN
CNTL_IN8
CNTL_IN7
CNTL_IN6
CNTL_IN5
CNTL_IN4
CNTL_IN3
CNTL_IN2
V
CC
GND
GND
V
RGB_IN0
RGB_IN1
RGB_IN2
RGB_IN3
RGB_IN4
RGB_IN5
RGB_IN6
RGB_IN7
RGB_IN8
RGB_IN9
CCLVDS
OUT+
OUT-
V
RGB_IN10
RGB_IN11
LVDS GND
MAX9217
RGB_IN12
RGB_IN13
RNG0
RNG1
3635343332313029282726
37
38
CC
39
40
41
42
43
44
45
46
47
48
+
123456789
CCIN
GND
V
LVDS GND
CMF
RGB_IN14
RGB_IN15
CCPLL
PWRDWN
V
101112
RGB_IN16
RGB_IN17
PLL GND
I.C.
25
CNTL_IN0
CNTL_IN1
24
23
22
21
20
19
18
17
16
15
14
13
I.C
PCLK_IN
DE_IN
CNTL_IN8
CNTL_IN7
CNTL_IN6
CNTL_IN5
CNTL_IN4
CNTL_IN3
CNTL_IN2
V
CC
GND
THIN QFN-EP
MAX9217
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(V
CC_
= +3.0V to +3.6V, RL= 100Ω ±1%, PWRDWN = high, TA= -40°C to +85°C, unless otherwise noted. Typical values are at
V
CC_
= +3.3V, TA= +25°C.) (Notes 1, 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
V
CC_
to _GND........................................................-0.5V to +4.0V
Any Ground to Any Ground...................................-0.5V to +0.5V
OUT+, OUT- to LVDS GND ...................................-0.5V to +4.0V
OUT+, OUT- Short Circuit to LVDS GND
or V
CCLVDS
.............................................................Continuous
OUT+, OUT- Short Through 0.125µF (or smaller),
25V Series Capacitor..........................................-0.5V to +16V
RGB_IN[17:0], CNTL_IN[8:0], DE_IN,
RNG0, RNG1, PCLK_IN,
PWRDWN, CMF to GND......................-0.5V to (V
CCIN
+ 0.5V)
Continuous Power Dissipation (T
A
= +70°C)
48-Lead LQFP (derate 21.7mW/°C above +70°C) ....1739mW
48-Lead Thin QFN (derate 37mW/°C above +70°C) .2963mW
ESD Protection
Machine Model (R
D
= 0Ω, CS= 200pF)
All Pins to GND ..............................................................±200V
Human Body Model (R
D
= 1.5kΩ, CS= 100pF)
All Pins to GND ................................................................±2kV
ISO 10605 (R
D
= 2kΩ, CS= 330pF)
Contact Discharge (OUT+, OUT-) to GND ....................±10kV
Air Discharge (OUT+, OUT-) to GND ............................±30kV
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
SINGLE-ENDED INPUTS (RGB_IN[17:0], CNTL_IN[8:0], DE_IN, PCLK_IN, PWRDWN, RNG_)
High-Level Input Voltage V
Low-Level Input Voltage V
Input Current I
Input Clamp Voltage V
LVDS OUTPUTS (OUT+, OUT-)
Differential Output Voltage V
Change in VOD Between
Complementary Output States
Common-Mode Voltage V
Change in VOS Between
Complementary Output States
Output Short-Circuit Current I
Magnitude of Differential Output
Short-Circuit Current
Output High-Impedance Current I
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
V
= 1.71V to <3V 0.65V
IH
IL
CCIN
V
= 1.71V to <3V -0.3 0.3V
CCIN
VIN = -0.3V to (V
= 1.71V to 3.6V,
V
IN
CCIN
PWRDWN = high or low
ICL = -18mA -1.5 V
CL
Figure 1 250 335 450 mV
OD
ΔV
ΔV
I
OS
OSD
Figure 1 20 mV
OD
Figure 1 1.125 1.29 1.375 V
OS
Figure 1 20 mV
OS
V
or V
OUT+
V
= 0 5.5 15 mA
OD
PWRDWN = low
OZ
or
V
CC_
= 0
V
CCIN
2V
CCIN
CCIN
+ 0.3
+ 0.3
CCIN
-0.3 +0.8
+ 0.3V),
CCIN
-70 +70 µA
= 0 or 3.6V -15 ±8 +15 mA
OUT-
V
= 0,
OUT+
V
= 3.6V
V
V
OUT-
OUT+
OUT-
= 3.6V,
= 0
-1 +1 µA
V
V
MAX9217
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
_______________________________________________________________________________________ 3
AC ELECTRICAL CHARACTERISTICS
(V
CC_
= +3.0V to +3.6V, RL= 100Ω ±1%, CL= 5pF, PWRDWN = high, TA= -40°C to +85°C, unless otherwise noted. Typical values
are at V
CC_
= +3.3V, TA= +25°C.) (Note 4)
DC ELECTRICAL CHARACTERISTICS (continued)
(V
CC_
= +3.0V to +3.6V, RL= 100Ω ±1%, PWRDWN = high, TA= -40°C to +85°C, unless otherwise noted. Typical values are at
V
CC_
= +3.3V, TA= +25°C.) (Notes 1, 2)
Differential Output Resistance R
Worst-Case Supply Current I
Power-Down Supply Current I
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
O
CCW
CCZ
RL = 100Ω ± 1%,
C
= 5pF,
L
continuous 10
transition words,
modulation off
(Note 3) 50 µA
3MHz 15 25
5MHz 18 25
10MHz 23 28
20MHz 33 39
35MHz 50 70
78 110 147 Ω
PCLK_IN TIMING REQUIREMENTS
Clock Period t
Clock Frequency f
Clock Frequency Difference from
Deserializer Reference Clock
Clock Duty Cycle DC t
Clock Transition Time tR, t
SWITCHING CHARACTERISTICS
Output Rise Time t
Output Fall Time t
Input Setup Time t
Input Hold Time t
Serializer Delay t
PLL Lock Time t
Power-Down Delay t
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Figure 2 28.57 333.00 ns
T
CLK
Δf
CLK
RISE
FALL
SET
HOLD
SD
LOCK
PD
or t
HIGH/tT
Figure 2 2.5 ns
F
20% to 80%, VOD ≥ 250mV,
modulation off, Figure 3
80% to 20%, VOD ≥ 250mV,
modulation off, Figure 3
Figure 4 3 ns
Figure 4 3 ns
Figure 5
Figure 6
Figure 7 1 µs
Figure 2 35 50 65 %
LOW/tT,
3 35 MHz
-2 +2 %
215 350 ps
206 350 ps
3.15 x
t
T
3.2 x
t
T
16385 x
t
T
mA
ns
ns
WORST-CASE PATTERN
SUPPLY CURRENT vs. FREQUENCY
MAX9217 toc01
FREQUENCY (MHz)
SUPPLY CURRENT (mA)
3127231915117
10
20
30
40
50
60
0
335
Typical Operating Characteristics
(TA= +25°C, V
CC_
= +3.3V, RL= 100Ω, modulation off, unless otherwise noted.)
MAX9217
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
4 _______________________________________________________________________________________
AC ELECTRICAL CHARACTERISTICS (continued)
(V
CC_
= +3.0V to +3.6V, RL= 100Ω ±1%, CL= 5pF, PWRDWN = high, TA= -40°C to +85°C, unless otherwise noted. Typical values
are at V
CC_
= +3.3V, TA= +25°C.) (Note 4)
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except V
OD
, ΔVOD, and ΔVOS.
Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production
tested at T
A
= +25°C.
Note 3: All LVTTL/LVCMOS inputs, except PWRDWN at ≤ 0.3V or ≥ V
CCIN
- 0.3V. PWRDWN is ≤ 0.3V.
Note 4: AC parameters are guaranteed by design and characterization and are not production tested. Limits are set at ±6 sigma.
Peak-to-Peak Output Offset
Voltage
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
V
OSp-p
700Mbps data rate,
CMF open, Figure 8
700Mbps data rate,
CMF 0.1µF to ground, Figure 8
22 70
12 50
mV
MAX9217
Pin Description
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
_______________________________________________________________________________________ 5
PIN NAME FUNCTION
1, 13, 37 GND Input Buffer Supply and Digital Supply Ground
2V
3–10,
39–48
11, 12, 15–21 CNTL_IN[8:0]
14, 38 V
22 DE_IN
23 PCLK_IN
24, 25 I.C. Internally connected to GND. Connect to GND or leave unconnected.
26 PLL GND PLL Supply Ground
27 V
28 PWRDWN LVTTL/LVCMOS Power-Down Input. Internally pulled down to GND.
29 CMF
30, 31 LVDS GND LVDS Supply Ground
32 OUT- Inverting LVDS Serial Data Output
33 OUT+ Noninverting LVDS Serial Data Output
34 V
35 RNG1
36 RNG0
— EP Exposed Pad (Thin QFN Package Only). Connect Thin QFN exposed pad to PCB GND.
CCIN
RGB_IN[17:0]
CC
CCPLL
CCLVDS
Input Buffer Supply Voltage. Bypass to GND with 0.1µF and 0.001µF capacitors in parallel as
close to the device as possible, with the smallest value capacitor closest to the supply pin.
LVTTL/LVCMOS Red, Green, and Blue Digital Video Data Inputs. Eighteen data bits are loaded
into the input latch on the rising edge of PCLK_IN when DE_IN is high. Internally pulled down to
GND.
LVTTL/LVCMOS Control Data Inputs. Control data are latched on the rising edge of PCLK_IN
when DE_IN is low. Internally pulled down to GND.
Digital Supply Voltage. Bypass to GND with 0.1µF and 0.001µF capacitors in parallel as close to
the device as possible, with the smallest value capacitor closest to the supply pin.
LVTTL/LVCMOS Data Enable Input. Logic-high selects RGB_IN[17:0] to be latched. Logic-low
selects CNTL_IN[8:0] to be latched. DE_IN must be switching for proper operation. Internally
pulled down to GND.
LVTTL/LVCMOS Parallel Clock Input. Latches data and control inputs and provides the PLL
reference clock. Internally pulled down to GND.
PLL Supply Voltage. Bypass to PLL GND with 0.1µF and 0.001µF capacitors in parallel as close
to the device as possible, with the smallest value capacitor closest to the supply pin.
Common-Mode Filter. Optionally connect a capacitor between CMF and ground to filter
common-mode switching noise.
LVDS Supply Voltage. Bypass to LVDS GND with 0.1µF and 0.001µF capacitors in parallel as
close to the device as possible, with the smallest value capacitor closest to the supply pin.
LVTTL/LVCMOS Frequency Range Select Input. Set to the frequency range that includes the
PCLK_IN frequency as shown in Table 3. Internally pulled down to GND.
LVTTL/LVCMOS Frequency Range Select Input. Set to the frequency range that includes the
PCLK_IN frequency as shown in Table 3. Internally pulled down to GND.
MAX9217
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
6 _______________________________________________________________________________________
Functional Diagram
Figure 1. LVDS DC Output Load and Parameters
OUT-
RGB_IN
CNTL_IN
DE_IN
PCLK_IN
RNG0
RNG1
PWRDWN
(-) VOS(+)
V
OS
1
INPUT LATCH
0
PLL
DC BALANCE/
ENCODE
TIMING AND CONTROL
OUT+
OUT-
PAR-TO-SER
MAX9217
RL / 2
V
/ 2
R
L
((OUT+) + (OUT-)) / 2
OUT+
OUT-
CMF
OD
V
OS
GND
V
(-)
OS
OUT+
= |VOS(+) - VOS(-)|
ΔV
OS
VOD(+)
V
(-)
OD
(OUT+) - (OUT-)
ΔVOD = |VOD(+) - VOD(-)|
= 0V
V
OD
(-)
V
OD
MAX9217
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
_______________________________________________________________________________________ 7
PCLK_IN
Figure 2. Parallel Clock Requirements
Figure 3. Output Rise and Fall Times
Figure 4. Synchronous Input Timing
t
T
V
V
IHmin
ILmax
t
HIGH
t
F
(OUT+) - (OUT-)
80%
t
R
OUT+
OUT-
C
L
t
RISE
t
LOW
R
L
C
L
80%
20%20%
t
FALL
PCLK_IN
RGB_IN[17:0]
CNTL_IN[8:0]
DE_IN
V
V
IHmin
ILmax
V
IHmin
V
ILmax
t
SET
t
HOLD
V
V
IHmin
ILmax
MAX9217
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
8 _______________________________________________________________________________________
Figure 5. Serializer Delay
Figure 6. PLL Lock Time
Figure 7. Power-Down Delay
EXPANDED TIME SCALE
RGB_IN
CNTL_IN
PCLK_IN
OUT_
PWRDWN
(OUT+) - (OUT-)
N
N + 1
HIGH-Z
N + 2
V
ILmax
N - 1
t
SD
t
LOCK
N + 3
N
BIT 0 BIT 19
N + 4
V
OD
= 0V
PCLK_IN
PWRDWN
V
ILmax
t
PD
(OUT+) - (OUT-)
PCLK_IN
HIGH-Z
MAX9217
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
_______________________________________________________________________________________ 9
Detailed Description
The MAX9217 DC-balanced serializer operates at a
parallel clock frequency of 3MHz to 35MHz, serializing
18 bits of parallel video data RGB_IN[17:0] when the
data enable input DE_IN is high, or 9 bits of parallel
control data CNTL_IN[8:0] when DE_IN is low. The
RGB video input data are encoded using 2 overhead
bits, EN0 and EN1, resulting in a serial word length of
20 bits (Table 1). Control inputs are mapped to 19 bits
and encoded with 1 overhead bit, EN0, also resulting in
a 20-bit serial word. Encoding reduces EMI and main-
tains DC balance across the serial cable. Two transition
words, which contain a unique bit sequence, are inserted at the transition boundaries of video-to-control and
control-to-video phases.
Control data inputs C0 to C4 are mapped to 3 bits each
in the serial control word (Table 2). At the deserializer,
2 or 3 bits at the same state determine the state of the
recovered bit, providing single bit-error tolerance for
C0 to C4. Control data that may be visible if an error
occurs, such as VSYNC and HSYNC, can be connected to these inputs. Control data inputs C5 to C8 are
mapped to 1 bit each.
Figure 8. Peak-to-Peak Output Offset Voltage
Bit 0 is the LSB and is serialized first. EN[1:0] are encoding bits. S[17:0] are encoded symbols.
Table 1. Serial Video Phase Word Format
Bit 0 is the LSB and is serialized first. C[8:0] are the control inputs.
Table 2. Serial Control Phase Word Format
OUT-
OUT+
((OUT+) + (OUT-)) / 2
V
OS(P-P)
V
OS(P-P)
012345678910111213141516171819
EN0 EN1 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17
012345678910111213141516171819
E N 0C0C0C0C1C1C1C2C2C2C3C3C3C4C4C4C5C6C7C8
MAX9217
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
10 ______________________________________________________________________________________
Transition Timing
The transition words require interconnect bandwidth
and displace control data. Therefore, control data is not
sampled (see Figure 9):
• Two clock cycles before DE_IN goes high.
• During the video phase.
• Two clock cycles after DE_IN goes low.
The last sampled control data are latched at the deserializer control data outputs during the transition and video
phases. Video data are latched at the deserializer RGB
data outputs during the transition and control phases.
Applications Information
AC-Coupling Benefits
AC-coupling increases the common-mode voltage to
the voltage rating of the capacitor. Two capacitors are
sufficient for isolation, but four capacitors—two at the
serializer output and two at the deserializer input—provide protection if either end of the cable is shorted to a
high voltage. AC-coupling blocks low-frequency
ground shifts and common-mode noise. The MAX9217
serializer can also be DC-coupled to the MAX9218
deserializer.
Figure 10 shows an AC-coupled serializer and deserializer with two capacitors per link, and Figure 11 is the
AC-coupled serializer and deserializer with four capacitors per link.
Selection of AC-Coupling Capacitors
See Figure 12 for calculating the capacitor values for
AC-coupling, depending on the parallel clock frequency. The plot shows capacitor values for two- and fourcapacitor-per-link systems. For applications using less
than 18MHz clock frequency, use 0.1µF capacitors.
Frequency-Range Setting RNG[1:0]
The RNG[1:0] inputs select the operating frequency
range of the MAX9217 serializer. An external clock within this range is required for operation. Table 3 shows
the selectable frequency ranges and corresponding
data rates for the MAX9217.
Figure 9. Transition Timing
CONTROL
PHASE
PCLK_IN
CNTL_IN
DE_IN
RGB_IN
= NOT SAMPLED BY PCLK_IN
TRANSITION
PHASE
TRANSITION
VIDEO PHASE
PHASE
CONTROL
PHASE
MAX9217
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
______________________________________________________________________________________ 11
Figure 10. AC-Coupled Serializer and Deserializer with Two Capacitors per Link
Figure 11. AC-Coupled Serializer and Deserializer with Four Capacitors per Link
V
CC
130Ω
RNG0
RNG1
RGB_IN
CNTL_IN
DE_IN
PCLK_IN
RNG0
RNG1
PWRDWN
130Ω
*
1
0
INPUT LATCH
PLL
ENCODE
DC BALANCE/
TIMING AND
CONTROL
PAR-TO-SER
OUT
CMF
*
82Ω 82Ω
MAX9217
CERAMIC RF SURFACE-MOUNT CAPACITOR
*CAPACITORS CAN BE AT EITHER END.
V
CC
130Ω
RGB_IN
CNTL_IN
DE_IN
130Ω
1
0
INPUT LATCH
ENCODE
DC BALANCE/
PAR-TO-SER
OUT
CMF
82Ω 82Ω
IN
TIMING AND
CONTROL
100Ω DIFFERENTIAL STP CABLE
IN
PLL
DECODE
DC BALANCE/
DC BALANCE/
MAX9218
DECODE
1
0
SER-TO-PAR
SER-TO-PAR
R/F
OUTEN
RGB_OUT
CNTL_OUT
DE_OUT
PCLK_OUT
REF_IN
PWRDWN
LOCK
R/F
1
0
OUTEN
RGB_OUT
CNTL_OUT
DE_OUT
PCLK_IN
RNG0
RNG1
PWRDWN
PLL
TIMING AND
CONTROL
RNG0
RNG1
MAX9217
CERAMIC RF SURFACE-MOUNT CAPACITOR
PLL
TIMING AND
CONTROL
100Ω DIFFERENTIAL STP CABLE
PCLK_OUT
REF_IN
PWRDWN
LOCK
MAX9218
MAX9217
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
12 ______________________________________________________________________________________
Termination
The MAX9217 has an integrated 100Ω output-termina-
tion resistor. This resistor damps reflections from
induced noise and mismatches between the transmission line impedance and termination resistors at the
deserializer input. With PWRDWN = low or with the supply off, the output termination is switched out and the
LVDS output is high impedance.
Common-Mode Filter
The integrated 100Ω output termination is made up of
two 50Ω resistors in series. The junction of the resistors
is connected to the CMF pin for connecting an optional
common-mode filter capacitor. Connect the filter
capacitor to ground close to the MAX9217 as shown in
Figure 13. The capacitor shunts common-mode switching current to ground to reduce EMI.
Figure 12. AC-Coupling Capacitor Values vs. Clock Frequency
of 18MHz to 35MHz
Table 3. Parallel Clock Frequency Range
Select
Figure 13. Common-Mode Filter Capacitor Connection
AC-COUPLING CAPACITOR VALUE
vs. PARALLEL CLOCK FREQUENCY
140
125
110
95
80
65
CAPACITOR VALUE (nF)
50
35
20
18 36
FOUR CAPACITORS PER LINK
TWO CAPACITORS PER LINK
333021 24 27
PARALLEL CLOCK FREQUENCY (MHz)
MAX9217 fig12
RNG1 RNG0
0 0 3 to 5 60 to 100
0 1 5 to10 100 to 200
1 0 10 to 20 200 to 400
1 1 20 to 35 400 to 700
PARALLEL
CLOCK (MHz)
SERIAL DATA RATE
OUT+
/ 2
R
O
CMF
RO / 2
OUT-
(Mbps)
C
CMF
MAX9217
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
______________________________________________________________________________________ 13
Power-Down and Power-Off
Driving PWRDWN low stops the PLL, switches out the
integrated 100Ω output termination, and puts the output
in high impedance to ground and differentially. With
PWRDWN ≤ 0.3V and all LVTTL/LVCMOS inputs ≤ 0.3V or
≥ V
CCIN
- 0.3V, supply current is reduced to 50µA or less.
Driving PWRDWN high starts PLL lock to PCLK_IN and
switches in the 100Ω output termination resistor. The
LVDS output is not driven until the PLL locks. The LVDS
output is high impedance to ground and 100Ω differen-
tial. The 100Ω integrated termination pulls OUT+ and
OUT- together while the PLL is locking so that V
OD
= 0V.
If V
CC
= 0, the output resistor is switched out and the LVDS
outputs are high impedance to ground and differentially.
PLL Lock Time
The PLL lock time is set by an internal counter. The lock
time is 16,385 PCLK_IN cycles. Power and clock should
be stable to meet the lock-time specification.
Input Buffer Supply
The single-ended inputs (RGB_IN[17:0], CNTL_IN[8:0],
DE_IN, RNG0, RNG1, PCLK_IN, and PWRDWN) are
powered from V
CCIN
. V
CCIN
can be connected to a
1.71V to 3.6V supply, allowing logic inputs with a nominal swing of V
CCIN
. If no power is applied to V
CCIN
when power is applied to VCC, the inputs are disabled
and PWRDWN is internally driven low, putting the
device in the power-down state.
Power-Supply Circuits and Bypassing
The MAX9217 has isolated on-chip power domains. The
digital core supply (VCC) and single-ended input supply
(V
CCIN
) are isolated but have a common ground (GND).
The PLL has separate power and ground (V
CCPLL
and
V
CCPLL
GND) and the LVDS input also has separate
power and ground (V
CCLVDS
and V
CCLVDS
GND). The
grounds are isolated by diode connections. Bypass each
VCC, V
CCIN
, V
CCPLL
, and V
CCLVDS
pin with high-frequency, surface-mount ceramic 0.1µF and 0.001µF capacitors
in parallel as close to the device as possible, with the
smallest value capacitor closest to the supply pin.
LVDS Output
The LVDS output is a current source. The voltage swing
is proportional to the termination resistance. The output
is rated for a differential load of 100Ω ±1%.
Cables and Connectors
Interconnect for LVDS typically has a differential impedance of 100Ω. Use cables and connectors that have
matched differential impedance to minimize impedance
discontinuities.
Twisted-pair and shielded twisted-pair cables offer
superior signal quality compared to ribbon cable and
tend to generate less EMI due to magnetic field canceling effects. Balanced cables pick up noise as common
mode, which is rejected by the LVDS receiver.
MAX9217
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
14 ______________________________________________________________________________________
Board Layout
Separate the LVTTL/LVCMOS inputs and LVDS output to
prevent crosstalk. A four-layer PCB with separate layers
for power, ground, and signals is recommended.
ESD Protection
The MAX9217 ESD tolerance is rated for Human Body
Model, Machine Model, and ISO 10605. ISO 10605
specifies ESD tolerance for electronic systems. The
Human Body Model, Machine Model, discharge components are CS= 100pF and RD= 1.5kΩ (Figure 14).
The ISO 10605 discharge components are CS= 330pF
and RD= 2kΩ (Figure 15). The Machine Model discharge components are C
S
= 200pF and RD= 0Ω
(Figure 16).
Chip Information
PROCESS: CMOS
Figure 14. Human Body ESD Test Circuit
Figure 15. ISO 10605 Contact-Discharge ESD Test Circuit
Figure 16. Machine Model ESD Test Circuit
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages
.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
48 LQFP C48+5
21-0054
48 TQFN T4866+1
21-0141
R
D
S
1.5kΩ
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
R
D
2kΩ
DEVICE
UNDER
TEST
1MΩ
CHARGE-CURRENT-
DC
LIMIT RESISTOR
C
100pF
HIGH-
VOLTAGE
SOURCE
50Ω TO 100Ω
R
D
0Ω
CHARGE-CURRENT-
DC
LIMIT RESISTOR
200pF
HIGH-
VOLTAGE
SOURCE
C
S
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
DEVICE
UNDER
TEST
HIGH-
VOLTAGE
DC
SOURCE
CHARGE-CURRENT-
LIMIT RESISTOR
330pF
C
S
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
DEVICE
UNDER
TEST
MAX9217
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
Revision History
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________
15
© 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
REVISION
NUMBER
3 5/08
4 8/09 Added automotive qualified part to Ordering Information 1
REVISION
DATE
DESCRIPTION
Corrected LQFP package, removed MOD function pins, added Machine Model
ESD, and corrected diagrams
PAGES
CHANGED
1, 2, 5, 6, 10–15
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