MAXIM MAX9217 User Manual
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
General Description
The MAX9217 digital video parallel-to-serial converter
serializes 27 bits of parallel data into a serial data stream.
Eighteen bits of video data and 9 bits of control data are
encoded and multiplexed onto the serial interface, reducing the serial data rate. The data enable input determines
when the video or control data is serialized.
The MAX9217 pairs with the MAX9218 deserializer to
form a complete digital video serial link. Interconnect
can be controlled-impedance PCB traces or twisted-pair
cable. Proprietary data encoding reduces EMI and provides DC balance. DC balance allows AC-coupling,
providing isolation between the transmitting and receiving ends of the interface. The LVDS output is internally
terminated with 100Ω.
ESD tolerance is specified for ISO 10605 with ±10kV
contact discharge and ±30kV air discharge.
The MAX9217 operates from a +3.3V core supply and
features a separate input supply for interfacing to 1.8V
to 3.3V logic levels. This device is available in 48-lead
Thin QFN and LQFP packages and is specified from
-40°C to +85°C.
Applications
Navigation System Display
In-Vehicle Entertainment System
Video Camera
LCD Displays
Features
♦ Proprietary Data Encoding for DC Balance and
Reduced EMI
♦ Control Data Sent During Video Blanking
♦ Five Control Data Inputs Are Single-Bit-Error
Tolerant
♦ Output Common-Mode Filter Reduces EMI
♦ Greater than 10m STP Cable Drive
♦ Wide ±2% Reference Clock Tolerance
♦ ISO 10605 ESD Protection
♦ Separate Input Supply Allows Interface to 1.8V to
3.3V Logic
♦ +3.3V Core Supply
♦ Space-Saving Thin QFN and LQFP Packages
♦ -40°C to +85°C Operating Temperature
MAX9217
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
________________________________________________________________
Maxim Integrated Products
1
Pin Configurations
Ordering Information
19-3558; Rev 4; 8/09
EVALUATION KIT
AVAILABLE
+
Denotes a lead(Pb)-free/RoHS-compliant package.
/V denotes an automotive qualified part.
*
EP = Exposed pad.
PART TEMP RANGE
MAX9217ECM+ -40°C to +85°C 48 LQFP
MAX9217ECM/V+ -40°C to +85°C 48 LQFP
MAX9217ETM+ -40°C to +85°C 48 Thin QFN-EP*
PINPACKAGE
TOP VIEW
GND
V
RGB_IN0
RGB_IN1
RGB_IN2
RGB_IN3
RGB_IN4
RGB_IN5
RGB_IN6
RGB_IN7
RGB_IN8
RGB_IN9
37
38
CC
39
40
41
42
43
44
45
46
47
48
CCLVDS
RNG0
RNG1
V
OUT+
OUT-
LVDS GND
LVDS GND
CMF
PWRDWN
3635343332313029282726
MAX9217
+
123456789
CCIN
GND
V
RGB_IN10
RGB_IN11
RGB_IN12
RGB_IN13
RGB_IN14
RGB_IN15
RGB_IN16
LQFP
CCPLL
V
PLL GND
101112
RGB_IN17
CNTL_IN0
I.C.
25
24
23
22
21
20
19
18
17
16
15
14
13
CNTL_IN1
I.C.
PCLK_IN
DE_IN
CNTL_IN8
CNTL_IN7
CNTL_IN6
CNTL_IN5
CNTL_IN4
CNTL_IN3
CNTL_IN2
V
CC
GND
GND
V
RGB_IN0
RGB_IN1
RGB_IN2
RGB_IN3
RGB_IN4
RGB_IN5
RGB_IN6
RGB_IN7
RGB_IN8
RGB_IN9
CCLVDS
OUT+
OUT-
V
RGB_IN10
RGB_IN11
LVDS GND
MAX9217
RGB_IN12
RGB_IN13
RNG0
RNG1
3635343332313029282726
37
38
CC
39
40
41
42
43
44
45
46
47
48
+
123456789
CCIN
GND
V
LVDS GND
CMF
RGB_IN14
RGB_IN15
CCPLL
PWRDWN
V
101112
RGB_IN16
RGB_IN17
PLL GND
I.C.
25
CNTL_IN0
CNTL_IN1
24
23
22
21
20
19
18
17
16
15
14
13
I.C
PCLK_IN
DE_IN
CNTL_IN8
CNTL_IN7
CNTL_IN6
CNTL_IN5
CNTL_IN4
CNTL_IN3
CNTL_IN2
V
CC
GND
THIN QFN-EP
MAX9217
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(V
CC_
= +3.0V to +3.6V, RL= 100Ω ±1%, PWRDWN = high, TA= -40°C to +85°C, unless otherwise noted. Typical values are at
V
CC_
= +3.3V, TA= +25°C.) (Notes 1, 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
V
CC_
to _GND........................................................-0.5V to +4.0V
Any Ground to Any Ground...................................-0.5V to +0.5V
OUT+, OUT- to LVDS GND ...................................-0.5V to +4.0V
OUT+, OUT- Short Circuit to LVDS GND
or V
CCLVDS
.............................................................Continuous
OUT+, OUT- Short Through 0.125µF (or smaller),
25V Series Capacitor..........................................-0.5V to +16V
RGB_IN[17:0], CNTL_IN[8:0], DE_IN,
RNG0, RNG1, PCLK_IN,
PWRDWN, CMF to GND......................-0.5V to (V
CCIN
+ 0.5V)
Continuous Power Dissipation (T
A
= +70°C)
48-Lead LQFP (derate 21.7mW/°C above +70°C) ....1739mW
48-Lead Thin QFN (derate 37mW/°C above +70°C) .2963mW
ESD Protection
Machine Model (R
D
= 0Ω, CS= 200pF)
All Pins to GND ..............................................................±200V
Human Body Model (R
D
= 1.5kΩ, CS= 100pF)
All Pins to GND ................................................................±2kV
ISO 10605 (R
D
= 2kΩ, CS= 330pF)
Contact Discharge (OUT+, OUT-) to GND ....................±10kV
Air Discharge (OUT+, OUT-) to GND ............................±30kV
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
SINGLE-ENDED INPUTS (RGB_IN[17:0], CNTL_IN[8:0], DE_IN, PCLK_IN, PWRDWN, RNG_)
High-Level Input Voltage V
Low-Level Input Voltage V
Input Current I
Input Clamp Voltage V
LVDS OUTPUTS (OUT+, OUT-)
Differential Output Voltage V
Change in VOD Between
Complementary Output States
Common-Mode Voltage V
Change in VOS Between
Complementary Output States
Output Short-Circuit Current I
Magnitude of Differential Output
Short-Circuit Current
Output High-Impedance Current I
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
V
= 1.71V to <3V 0.65V
IH
IL
CCIN
V
= 1.71V to <3V -0.3 0.3V
CCIN
VIN = -0.3V to (V
= 1.71V to 3.6V,
V
IN
CCIN
PWRDWN = high or low
ICL = -18mA -1.5 V
CL
Figure 1 250 335 450 mV
OD
ΔV
ΔV
I
OS
OSD
Figure 1 20 mV
OD
Figure 1 1.125 1.29 1.375 V
OS
Figure 1 20 mV
OS
V
or V
OUT+
V
= 0 5.5 15 mA
OD
PWRDWN = low
OZ
or
V
CC_
= 0
V
CCIN
2V
CCIN
CCIN
+ 0.3
+ 0.3
CCIN
-0.3 +0.8
+ 0.3V),
CCIN
-70 +70 µA
= 0 or 3.6V -15 ±8 +15 mA
OUT-
V
= 0,
OUT+
V
= 3.6V
V
V
OUT-
OUT+
OUT-
= 3.6V,
= 0
-1 +1 µA
V
V
MAX9217
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
_______________________________________________________________________________________ 3
AC ELECTRICAL CHARACTERISTICS
(V
CC_
= +3.0V to +3.6V, RL= 100Ω ±1%, CL= 5pF, PWRDWN = high, TA= -40°C to +85°C, unless otherwise noted. Typical values
are at V
CC_
= +3.3V, TA= +25°C.) (Note 4)
DC ELECTRICAL CHARACTERISTICS (continued)
(V
CC_
= +3.0V to +3.6V, RL= 100Ω ±1%, PWRDWN = high, TA= -40°C to +85°C, unless otherwise noted. Typical values are at
V
CC_
= +3.3V, TA= +25°C.) (Notes 1, 2)
Differential Output Resistance R
Worst-Case Supply Current I
Power-Down Supply Current I
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
O
CCW
CCZ
RL = 100Ω ± 1%,
C
= 5pF,
L
continuous 10
transition words,
modulation off
(Note 3) 50 µA
3MHz 15 25
5MHz 18 25
10MHz 23 28
20MHz 33 39
35MHz 50 70
78 110 147 Ω
PCLK_IN TIMING REQUIREMENTS
Clock Period t
Clock Frequency f
Clock Frequency Difference from
Deserializer Reference Clock
Clock Duty Cycle DC t
Clock Transition Time tR, t
SWITCHING CHARACTERISTICS
Output Rise Time t
Output Fall Time t
Input Setup Time t
Input Hold Time t
Serializer Delay t
PLL Lock Time t
Power-Down Delay t
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Figure 2 28.57 333.00 ns
T
CLK
Δf
CLK
RISE
FALL
SET
HOLD
SD
LOCK
PD
or t
HIGH/tT
Figure 2 2.5 ns
F
20% to 80%, VOD ≥ 250mV,
modulation off, Figure 3
80% to 20%, VOD ≥ 250mV,
modulation off, Figure 3
Figure 4 3 ns
Figure 4 3 ns
Figure 5
Figure 6
Figure 7 1 µs
Figure 2 35 50 65 %
LOW/tT,
3 35 MHz
-2 +2 %
215 350 ps
206 350 ps
3.15 x
t
T
3.2 x
t
T
16385 x
t
T
mA
ns
ns
WORST-CASE PATTERN
SUPPLY CURRENT vs. FREQUENCY
MAX9217 toc01
FREQUENCY (MHz)
SUPPLY CURRENT (mA)
3127231915117
10
20
30
40
50
60
0
335
Typical Operating Characteristics
(TA= +25°C, V
CC_
= +3.3V, RL= 100Ω, modulation off, unless otherwise noted.)
MAX9217
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
4 _______________________________________________________________________________________
AC ELECTRICAL CHARACTERISTICS (continued)
(V
CC_
= +3.0V to +3.6V, RL= 100Ω ±1%, CL= 5pF, PWRDWN = high, TA= -40°C to +85°C, unless otherwise noted. Typical values
are at V
CC_
= +3.3V, TA= +25°C.) (Note 4)
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except V
OD
, ΔVOD, and ΔVOS.
Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production
tested at T
A
= +25°C.
Note 3: All LVTTL/LVCMOS inputs, except PWRDWN at ≤ 0.3V or ≥ V
CCIN
- 0.3V. PWRDWN is ≤ 0.3V.
Note 4: AC parameters are guaranteed by design and characterization and are not production tested. Limits are set at ±6 sigma.
Peak-to-Peak Output Offset
Voltage
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
V
OSp-p
700Mbps data rate,
CMF open, Figure 8
700Mbps data rate,
CMF 0.1µF to ground, Figure 8
22 70
12 50
mV
MAX9217
Pin Description
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
_______________________________________________________________________________________ 5
PIN NAME FUNCTION
1, 13, 37 GND Input Buffer Supply and Digital Supply Ground
2V
3–10,
39–48
11, 12, 15–21 CNTL_IN[8:0]
14, 38 V
22 DE_IN
23 PCLK_IN
24, 25 I.C. Internally connected to GND. Connect to GND or leave unconnected.
26 PLL GND PLL Supply Ground
27 V
28 PWRDWN LVTTL/LVCMOS Power-Down Input. Internally pulled down to GND.
29 CMF
30, 31 LVDS GND LVDS Supply Ground
32 OUT- Inverting LVDS Serial Data Output
33 OUT+ Noninverting LVDS Serial Data Output
34 V
35 RNG1
36 RNG0
— EP Exposed Pad (Thin QFN Package Only). Connect Thin QFN exposed pad to PCB GND.
CCIN
RGB_IN[17:0]
CC
CCPLL
CCLVDS
Input Buffer Supply Voltage. Bypass to GND with 0.1µF and 0.001µF capacitors in parallel as
close to the device as possible, with the smallest value capacitor closest to the supply pin.
LVTTL/LVCMOS Red, Green, and Blue Digital Video Data Inputs. Eighteen data bits are loaded
into the input latch on the rising edge of PCLK_IN when DE_IN is high. Internally pulled down to
GND.
LVTTL/LVCMOS Control Data Inputs. Control data are latched on the rising edge of PCLK_IN
when DE_IN is low. Internally pulled down to GND.
Digital Supply Voltage. Bypass to GND with 0.1µF and 0.001µF capacitors in parallel as close to
the device as possible, with the smallest value capacitor closest to the supply pin.
LVTTL/LVCMOS Data Enable Input. Logic-high selects RGB_IN[17:0] to be latched. Logic-low
selects CNTL_IN[8:0] to be latched. DE_IN must be switching for proper operation. Internally
pulled down to GND.
LVTTL/LVCMOS Parallel Clock Input. Latches data and control inputs and provides the PLL
reference clock. Internally pulled down to GND.
PLL Supply Voltage. Bypass to PLL GND with 0.1µF and 0.001µF capacitors in parallel as close
to the device as possible, with the smallest value capacitor closest to the supply pin.
Common-Mode Filter. Optionally connect a capacitor between CMF and ground to filter
common-mode switching noise.
LVDS Supply Voltage. Bypass to LVDS GND with 0.1µF and 0.001µF capacitors in parallel as
close to the device as possible, with the smallest value capacitor closest to the supply pin.
LVTTL/LVCMOS Frequency Range Select Input. Set to the frequency range that includes the
PCLK_IN frequency as shown in Table 3. Internally pulled down to GND.
LVTTL/LVCMOS Frequency Range Select Input. Set to the frequency range that includes the
PCLK_IN frequency as shown in Table 3. Internally pulled down to GND.
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