The MAX9209/MAX9213 serialize 21 bits of LVTTL/
LVCMOS parallel input data to three LVDS outputs. A
parallel rate clock on a fourth LVDS output provides
timing for deserialization.
The MAX9209/MAX9213 feature programmable DC balance, which allows isolation between the serializer and
deserializer using AC-coupling. The DC balance circuits
on each channel code the data, limiting the imbalance
of transmitted ones and zeros to a defined range. The
companion MAX9210/MAX9214 deserializers decode
the data. When DC balance is not programmed, the
serializers are compatible with non-DC-balanced, 21-bit
serializers such as the DS90CR215 and DS90CR217.
Two frequency ranges and two DC-balance default
conditions are available for maximum replacement flexibility and compatibility with existing non-DC-balanced
serializers.
The MAX9209/MAX9213 are available in TSSOP and
space-saving TQFN packages.
(VCC= +3.0V to +3.6V, RL= 100Ω±1%, PWRDWN = high, DCB/NC = high or low, unless otherwise noted. Typical values are at V
CC
= +3.3V, TA= +25°C.) (Notes 1, 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCCto GND...........................................................-0.5V to +4.0V
LVDS Outputs (TxOUT_, TxCLK OUT_) to GND ...-0.5V to +4.0V
5V Tolerant LVTTL/LVCMOS Inputs
(TxIN_, TxCLK IN, PWRDWN) to GND ..............-0.5V to +6.0V
(DCB/NC) to GND ......................................-0.5V to (V
CC
+ 0.5V)
LVDS Outputs (TxOUT_, TxCLK OUT_)
Short to GND and Differential Short .......................Continuous
(VCC= +3.0V to +3.6V, RL= 100Ω±1%, CL= 5pF, PWRDWN = high, DCB/NC = high or low, unless otherwise noted. Typical values
are at V
CC
= +3.3V, TA= +25°C.) (Notes 4, 5)
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except V
OD
, ∆VOD, and ∆VOS.
Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production
tested at T
A
= +25°C.
Note 3: Guaranteed by design.
Note 4: TCIP is the period of TxCLK IN.
Note 5: AC parameters are guaranteed by design and characterization, and are not production tested. Limits are set at ±6 sigma.
Note 6: Pulse position TPPosN is characterized using 2
The MAX9209 operates at a parallel clock frequency of
8MHz to 34MHz in DC-balanced mode and 10MHz to
40MHz in non-DC-balanced mode. The MAX9213 operates at a parallel clock frequency of 16MHz to 66MHz
in DC-balanced mode and 20MHz to 85MHz in nonDC-balanced mode.
DC-balanced or non-DC-balanced operation is controlled by the DCB/NC pin (see Table 1). In non-DCbalanced mode, each channel serializes 7 bits every
cycle of the parallel clock. In DC-balanced mode, 9 bits
are serialized every clock cycle (7 data bits + 2 DC-balance bits). The highest data rate in DC-balanced mode
for the MAX9213 is 66MHz x 9 = 594Mbps. In non-DCbalanced mode, the maximum data rate is 85MHz x 7 =
595Mbps. A bit time is 1 divided by the data rate, for
example, 1 / 595Mbps = 1.68ns.
DC Balance
Through data coding, the DC-balance circuits limit the
imbalance of ones and zeros transmitted on each channel. If +1 is assigned to each binary one transmitted
and -1 is assigned to each binary zero transmitted, the
variation in the running sum of assigned values is
called the digital sum variation (DSV). The maximum
DSV for the MAX9209/MAX9213 data channels is 10. At
most, 10 more zeros than ones, or 10 more ones than
zeros, are transmitted. The maximum DSV for the clock
channel is 5. Limiting the DSV and choosing the correct
coupling capacitors maintain differential signal amplitude
and reduce jitter due to droop on AC-coupled links.
TxCLK OUT
Figure 5. Non-DC-Balanced Mode LVDS Output Pulse Position Measurement
To obtain DC balance on the data channels, the parallel input data is inverted or not inverted, depending on
the sign of the digital sum at the word boundary. Two
complementary bits are appended to each group of 7
parallel input data bits to indicate to the MAX9210/
MAX9214 deserializers whether the data bits are inverted (Figure 11). The deserializer restores the original
state of the parallel data. The LVDS clock signal alternates duty cycles of 4/9 and 5/9, which maintains DC
balance. Figure 12 shows the non-DC-balanced mode
inputs mapped to LVDS outputs.
Figure 11. DC-Balanced Mode Inputs Mapped to LVDS Outputs
Bit errors experienced with DC-coupling can be eliminated by increasing the receiver common-mode voltage range by AC-coupling. AC-coupling increases the
common-mode voltage range of an LVDS receiver to
nearly the voltage rating of the capacitor. The typical
LVDS driver output is 350mV centered on an offset volt-
age of 1.25V, making single-ended output voltages of
1.425V and 1.075V. An LVDS receiver accepts signals
from 0V to 2.4V, allowing approximately ±1V commonmode difference between the driver and receiver on a
DC-coupled link (2.4V - 1.425V = 0.975V and 1.075V 0V = 1.075V). Figure 13 shows the DC-coupled link,
non-DC-balanced mode.
Figure 12. Non-DC-Balanced Mode Inputs Mapped to LVDS Outputs
Common-mode voltage differences may be due to
ground potential variation or common-mode noise. If
there is more than ±1V of difference, the receiver is not
guaranteed to read the input signal correctly and may
cause bit errors. AC-coupling filters low-frequency
ground shifts and common-mode noise and passes
high-frequency data. A common-mode voltage difference up to the voltage rating of the coupling capacitor
(minus half the differential swing) is tolerated. DC-balanced coding of the data is required to maintain the differential signal amplitude and limit jitter on an
AC-coupled link. A capacitor in series with each output
of the LVDS driver is sufficient for AC-coupling. However,
two capacitors—one at the serializer output and one at
the deserializer input—provide protection in case either
end of the cable is shorted to a high voltage.
5V Tolerant Inputs
All signal and control inputs except DCB/NC are 5V tolerant and are internally pulled down to GND. The
DCB/NC pin has a pullup on the MAX9209/MAX9213.
DCB/NC Pin Default Conditions
The MAX9209/MAX9213 have programmable DC balance/non-DC balance. See Table 1 for DCB/NC default
settings and operating modes.
MAX9209
Figure 14. Two Capacitors per Link, AC-Coupled, DC-Balanced Mode
Voltage droop and the DSV of transmitted symbols
cause signal transitions to start from different voltage
levels. Because the transition time is finite, starting the
signal transition from different voltage levels causes
timing jitter. The time constant for an AC-coupled link
needs to be chosen to reduce droop and jitter to an
acceptable level.
The RC network for an AC-coupled link consists of the
LVDS receiver termination resistor (R
T
), the LVDS driver
output resistor (RO), and the series AC-coupling capacitors (C). The RC time constant for two equal-value
series capacitors is (C x (RT + RO)) / 2 (Figure 14). The
RC time constant for four equal-value series capacitors
is (C x (RT + RO)) / 4 (Figure 15).
RTis required to match the transmission line impedance (usually 100Ω) and ROis determined by the LVDS
driver design, with a minimum value of 78Ω (see the
DC
Electrical Characteristics
table). This leaves the capaci-
tor selection to change the system time constant.
In the following example, the capacitor value for a
droop of 2% is calculated. Jitter due to this droop is
then calculated assuming a 1ns transition time:
C = -(2 x tBx DSV) / (ln (1 - D) x (RT+ RO)) (Eq 1)
where:
C = AC-coupling capacitor (F)
tB= bit time (s)
DSV = digital sum variation (integer)
ln = natural log
D = droop (% of signal amplitude)
RT= termination resistor (Ω)
Figure 15. Four Capacitors per Link, AC-Coupled, DC-Balanced Mode
Equation 1 is for two series capacitors (Figure 14). The
bit time (t
B
) is the period of the parallel clock divided by
9. The DSV is 10. See equation 3 for four series capacitors (Figure 15).
The capacitor for 2% maximum droop at 8MHz parallel
rate clock is:
C = -(2 x tBx DSV) / (ln (1 - D) x (RT+ RO))
C = -(2 x 13.9ns x 10) / (ln (1 - .02) x (100Ω + 78Ω))
C = 0.0773µF
Jitter due to droop is proportional to the droop and
transition time:
tJ= tTx D (Eq 2)
where:
tJ= jitter (s)
tT= transition time (s) (0% to 100%)
D = droop (% of signal amplitude)
Jitter due to 2% droop and assumed 1ns transition time is:
tJ= 1ns x 0.02
tJ= 20ps
The transition time in a real system depends on the frequency response of the cable driven by the serializer.
The capacitor value decreases for a higher frequency
parallel clock and for higher levels of droop and jitter.
Use high-frequency, surface-mount ceramic capacitors.
Equation 1 altered for four series capacitors (Figure 15) is:
C = -(4 x tBx DSV) / (ln (1 - D) x (RT+ RO)) (Eq 3)
Integrated Termination
The MAX9209/MAX9213 have an integrated output termination resistor across each of the four LVDS outputs.
These resistors damp reflections from induced noise and
mismatches between the transmission line impedance
and termination resistor at the deserializer input. In DCbalanced mode, the differential output resistance is part
of the RC time constant. In non-DC-balanced mode, the
output termination is increased to 410Ω (typ) to reduce
power. In power-down mode (PWRDWN = low) or when
the power supply is off, the output resistor is switched
out and the LVDS outputs are high impedance.
PWRDWN
and Power-Off
Driving PWRDWN low stops the PLL, switches out the
integrated output termination resistors, puts the LVDS
outputs in high impedance, and reduces supply current
to 50µA or less. Driving PWRDWN high starts the PLL
lock to the input clock and switches in the output termination resistors. The LVDS outputs are not driven until
the PLL locks. The differential output resistance pulls
the outputs together and the LVDS outputs are high
impedance to ground. If the power supply is turned off,
the output resistors are switched out and the LVDS outputs are high impedance.
PLL Lock Time
The PLL lock time is set by an internal counter. The maximum time to lock is 32,800 clock periods. Power and
clock should be stable to meet the lock-time specification. When the PLL is locking, the LVDS outputs are not
active and have a differential output resistance of RO.
Power-Supply Bypassing
There are separate power domains for LVDS, PLL, and
digital circuits. Bypass each LVDS VCC, PLL VCC, and
VCCpin with high-frequency surface-mount ceramic
0.1µF and 0.001µF capacitors in parallel as close to the
device as possible, with the smallest value capacitor
closest to the supply pin.
LVDS Outputs
The LVDS outputs are current sources. The voltage
swing is proportional to the load impedance. The outputs are rated for a differential load of 100Ω±1%.
Cables and Connectors
Interconnect for LVDS typically has a differential impedance of 100Ω. Use cables and connectors that have
matched differential impedance to minimize impedance
discontinuities.
Twisted-pair and shielded twisted-pair cables offer
superior signal quality compared to ribbon cable and
tend to generate less EMI due to magnetic field canceling effects. Balanced cables pick up noise as common
mode, which is rejected by the LVDS receiver.
Board Layout
Keep the LVTTL/LVCMOS input and LVDS output signals separated to prevent crosstalk. A four-layer PCB
with separate layers for power, ground, LVDS outputs,
and digital signals is recommended.
The MAX9209/MAX9213 ESD tolerance is rated for IEC
61000-4-2, Human Body Model and ISO 10605 standards. IEC 61000-4-2 and ISO 10605 specify ESD tolerance for electronic systems. The IEC 61000-4-2
discharge components are CS= 150pF and RD= 330Ω
(Figure 16). For IEC 61000-4-2, the LVDS outputs are
rated for ±8kV contact and ±15kV air discharge. The
Human Body Model discharge components are C
S
=
100pF and RD= 1.5kΩ (Figure 17). For the Human Body
Model, all pins are rated for ±2kV contact discharge. The
ISO 10605 discharge components are CS= 330pF and
RD= 2kΩ (Figure 18). For ISO 10605, the LVDS outputs
are rated for ±8kV contact and ±25kV air discharge.
Figure 16. IEC 61000-4-2 Contact Discharge ESD Test Circuit
Figure 17. Human Body ESD Test Circuit
Figure 18. ISO 10605 Contact Discharge ESD Test Circuit
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages
. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE NO.
LAND
PATTERN NO.
48 TSSOPA48+1
21-0155
90-0124
48 TQFNT4877+6
21-0144
90-0132
TOP VIEW
TxIN4
V
TxIN5
GND
TxIN7
TxIN8
TxIN9
GND
TxIN11
TxIN12
V
TxIN13
TxIN14
GND
TxIN15
TxIN16
TxIN17
VCC
TxIN18
TxIN19
GND
+
1
2
CC
3
4
5
6
7
8
CC
9
MAX9209
MAX9213
10
11
12
13
14
CC
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
TxIN3
TxIN2
GND
TxIN1TxIN6
TxIN0
DCB/NC
LVDS GND
TxOUT0-V
TxOUT0+
TxOUT1-TxIN10
TxOUT1+
LVDS V
CC
LVDS GND
TxOUT2-
TxOUT2+
TxCLK OUT-
TxCLK OUT+
LVDS GND
PLL GND
PLL V
CC
PLL GND
PWRDWN
TxCLK IN
TxIN20
TxIN8
V
TxIN9
TxIN10
GND
TxIN11
TxIN12
V
TxIN13
TxIN14
GND
TxIN15
TxIN6
CC
V
TxIN5
TxIN18
CC
V
TxIN4
TxIN3
MAX9209
MAX9213
EXPOSED PAD
GND
TxIN19
TxIN20
TxIN2
GND
TxCLK IN
PWRDWN
TxIN1
TxIN0
CC
PLL V
PLL GND
DCB/NC
37
36
35
34
33
32
31
30
29
28
27
26
25
24
PLL GND
LVDS GND
TxOUT0TxOUT0+
TxOUT1TxOUT1+
LVDS V
CC
LVDS GND
TxOUT2-
TxOUT2+
TxCLK OUTTxCLK OUT+
LVDS GND
GND
TxIN7
4847464544434241403938
+
1
2
CC
3
4
5
6
7
8
CC
9
10
11
12
1314151617181920212223
TxIN17
TxIN16
TQFN
TSSOP
MAX9209/MAX9213
Programmable DC-Balanced
21-Bit Serializers
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in
the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
18
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600