MAXIM MAX9206, MAX9208 User Manual

General Description

The MAX9206/MAX9208 deserializers transform a high­speed serial bus low-voltage differential signaling
(BLVDS) data stream into 10-bit-wide parallel LVCMOS/
LVTTL data and clock. The deserializers pair with seri­alizers such as the MAX9205/MAX9207, which gener­ate a serial BLVDS signal from 10-bit-wide parallel
data. The serializer/deserializer combination reduces
interconnect, simplifies PCB layout, and reduces board
size.

The MAX9206/MAX9208 receive serial data at
450Mbps and 600Mbps, respectively, over board
traces or twisted-pair cables. These devices combine
frequency lock, bit lock, and frame lock to produce a
parallel-rate clock and word-aligned 10-bit data.
Serialization eliminates parallel bus clock-to-data and
data-to-data skew.

A power-down mode reduces typical supply current to
less than 600µA. Upon power-up (applying power or
driving PWRDN high), the MAX9206/MAX9208 estab­lish lock after receiving synchronization signals or serial
data from the MAX9205/MAX9207. An output enable
allows the outputs to be disabled, putting the parallel
data outputs and recovered output clock into a high­impedance state without losing lock.

The MAX9206/MAX9208 operate from a single +3.3V
supply and are specified for operation from -40°C to
+85°C. The MAX9206/MAX9208 are available in 28-pin
SSOP packages.

Applications

Features

o Stand-Alone Deserializer (vs. SerDes) Ideal for

Unidirectional Links

o Automatic Clock Recovery

o Allow Hot Insertion and Synchronization Without

System Interruption

o BLVDS Serial Input Rated for Point-to-Point and

Bus Applications

o Fast Pseudorandom Lock

o Wide Reference Clock Input Range

16MHz to 45MHz (MAX9206)

40MHz to 60MHz (MAX9208)

o High 720ps (p-p) Jitter Tolerance (MAX9206)

o Low 30mA Supply Current (MAX9206 at 16MHz)

o 10-Bit Parallel LVCMOS/LVTTL Output

o Up to 600Mbps Throughput (MAX9208)

o Programmable Output Strobe Edge

o Pin Compatible to DS92LV1212A and

DS92LV1224

MAX9206/MAX9208

10-Bit Bus LVDS Deserializers

________________________________________________________________

Maxim Integrated Products

1

19-2130; Rev 2; 11/10

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.

Ordering Information

EVALUATION KIT

AVAILABLE

Pin Configuration appears at end of data sheet.

Typical Operating Circuit

Cellular Phone Base
Stations

Add/Drop Muxes
Digital Cross-Connects

DSLAMs
Network Switches and

Routers
Backplane Interconnect

+

Denotes a lead(Pb)-free/RoHS-compliant package.

/V denotes an automotive qualified part.

PART

MAX9206EAI+ -40°C to +85°C 28 SSOP 16 to 40

MAX9206EAI/V+ -40°C to +85°C 28 SSOP 16 to 40

MAX9208EAI+ -40°C to +85°C 28 SSOP 40 to 66

TEMP

RANGE

PIN­PACKAGE

REF CLOCK

RANGE

(MHz)

BUS

OUT+

10

IN_

TCLK_R/F

TCLK

SYNC 1

SYNC 2

INPUT LATCH

PLL

PARALLEL-TO-SERIAL

TIMING AND

CONTROL

MAX9205
MAX9207

100Ω 100Ω

OUT-

EN
PWRDN

LVDS

PCB OR TWISTED PAIR

RI+

10

ROUT_

RI-

PLL

MAX9206
MAX9208

CLOCK

RECOVERY

OUTPUT LATCH

SERIAL-TO-PARALLEL

TIMING AND

CONTROL

REFCLK
REN
LOCK

RCLK
RCLK_R/F

MAX9206/MAX9208

10-Bit Bus LVDS Deserializers

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

AVCC, DVCC to AGND, DGND................................-0.3V to +4V

RI+, RI- to AGND, DGND .........................................-0.3V to +4V

All Other Pins to DGND..............................-0.3V to DV

CC

+ 0.3V

ROUT_ Short-Circuit Duration (Note 1) ......................Continuous

Continuous Power Dissipation (T

A

= +70°C)

28-Pin SSOP (derate 9.5mW/°C above +70°C) ..........762mW

Operating Temperature Range ...........................-40°C to +85°C

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-65°C to +150°C

ESD Rating (Human Body Model, RI+, RI-) .........................±8kV

Lead Temperature (soldering, 10s) .................................+300°C

Soldering Temperature (reflow) .......................................+260°C

DC ELECTRICAL CHARACTERISTICS

(V

AVCC

= V

DVCC

= +3.0V to +3.6V, differential input voltage |V

ID

| = 0.1V to 1.2V, common-mode voltage V

CM

= |VID/2| to 2.4V

-

|V

ID

/2|, TA= -40°C to +85°C, unless otherwise noted. Typical values are at V

AVCC

= V

DVCC

= +3.3V, VCM= 1.1V, |V

ID

| = 0.2V,

T

A

= +25°C.) (Notes 2, 3)

PARAMETER S YMBOL CONDITIONS MIN TYP MAX UNITS

POWER SUPPLY

CL = 15pF,

Supply Current I

CC

worst-case
pattern,
Figure 1

Power-Down Supply Current I

CCX

PWRDWN = low 1 mA

LVCMOS/LVTTL LOGIC INPUTS (REN, REFCLK, RCLK_R/F, PWRDN)

High-Level Input Voltage VIH 2.0 VCC V

Low-Leve l Input Voltage VIL 0 0.8 V

Input Current I

IN

VIN = 0V, V

AVCC

LVCMOS/LVTTL LOGIC OUTPUTS (ROUT_, RCLK, LOCK)

High-Level Output Voltage VOH IOH = -5mA 2.2 2.9 VCC V

Low-Leve l Output Voltage VOL IOL = 5mA 0 0.33 0.5 V

Output Short-Circuit Current IOS V

Output High-Impedance Current I

OZ

= 0V -15 -38 -85 mA

ROUT_

PWRDN = low, V
= 0V, V

AVCC

, or V

BLVDS S ERIAL INPUT (RI+, RI-)

Differential Input High

Differential Input Low Threshold V

Input Current I

Power-Off Input Current

Input Resistor 1 R

Input Resistor 2 R

9 100 mV

V

TH

-100 -9 mV

TL

0.1V  |VID|  0.45V -64 64

, I

RI+

RI-

0.45V < |VID|  0.6V -82 82

I

RI+OFF

I

RI-OFF

0.1V  |VID|  0.45V, V

,

0.45V < |VID|  0.6V, V

V

IN1

IN2

AVCC

V

AVCC

= V

= V

DVCC

DVCC

MAX9206

MAX9208

, or V

DVCC

= V

ROUT_

DVCC

AVCC

AVCC

-15 15 μA

RCLK

= V

= V

16MHz 30 45

45MHz 57 75

40MHz 55 75

60MHz 80 100

= V

LOCK

= 0V -64 64

DVCC

= 0V -82 82

DVCC

-1 1 μA

= 3.6V or 0V, Figure 2 4 k

= 3.6V or 0V, Figure 2 150 k

mA

μA

μA

MAX9206/MAX9208

10-Bit Bus LVDS Deserializers

_______________________________________________________________________________________ 3

AC ELECTRICAL CHARACTERISTICS

(V

AVCC

= V

DVCC

= +3.0V to +3.6V, CL= 15pF, differential input voltage |V

ID

| = 0.15V to 1.2V, common-mode voltage V

CM

= |VID/2|

to 2.4V - |VID/2|, TA= -40°C to +85°C, unless otherwise noted. Typical values are at V

AVCC

= V

DVCC

= +3.3V, VCM= 1.1V, |V

ID

| =

0.2V, T

A

= +25°C.) (Notes 4, 5)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

REFERENCE CLOCK TIMING REQUIREMENTS (REFCLK)

REFCLK Frequency f

RFF

MAX9206 16 45

MAX9208 40 60

REFCLK Frequency Variation RFFV -200 200 ppm

REFCLK Period t

RFCP

MAX9206 22.222 62.500

MAX9208 16.666 25

REFCLK Duty Cycle RFDC 30 50 70 %

REFCLK Input Transition Time t

3 6 ns

RFTT

SWITCHING CHARACTERISTICS

Recovered Clock (RCLK)
Period (Note 6)

Low-to-High Transition Time t

High-to-Low Transition Time t

t

RCP

CLH

CHL

Deserializer Delay tDD Figure 4

ROUT_ Data Valid Before RCLK t

ROUT_ Data Valid After RCLK t

RCLK Duty Cycle t

OUTPUT High-to-High
Impedance Delay

OUTPUT Low-to-High
Impedance Delay

OUTPUT High-Impedance to
High-State Delay

OUTPUT High-Impedance to
Low-State Delay

ROS

ROH

RDC

t

HZR

t

LZR

t

ZHR

t

ZLR

MAX9206 22.222 62.500

MAX9208 16.666 25

Figure 3 1.5 3 ns

Figure 3 2 3 ns

MAX9206, 45MHz

MAX9208, 60MHz

1.75 x t
+ 2

1.75 x t

+ 1.1

Figure 5 0.4 x t

Figure 5 0.4 x t

RCP

RCP

RCP

RCP

1.75 x t
+ 3.3

1.75 x t
+ 3.3

0.5 x t

0.5 x t

RCP

RCP

RCP

RCP

1.75 x t

RCP

+ 6.5

1.75 x t

RCP

+ 5.6

ns

ns

43 50 57 %

CL = 5pF, Figure 6 8 ns

CL = 5pF, Figure 6 8 ns

CL = 5pF, Figure 6 6 ns

CL = 5pF, Figure 6 6 ns

Sync patterns at input; supply and

PLL Lock Time (from PWRDN
Transition High)

t

DSR1

REFCLK stable; measured from
PWRDN transition high to LOCK

(2048 + 42)

x t

RFCP

transition low; Figure 7

MHz

ns

ns

ns

ns

MAX9206/MAX9208

Note 1: Short one output at a time. Do not exceed the Absolute Maximum continuous power dissipation.
Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. Voltages are referenced to ground

except V

TH

, VTL, and VID, which are differential input voltages.

Note 3: DC parameters are production tested at T

A

= +25°C and guaranteed by design and characterization over operating temper-

ature range.

Note 4: AC parameters guaranteed by design and characterization.
Note 5: C

L

includes scope probe and test jig capacitance.

Note 6: t

RCP

is determined by the period of TCLK, which is the reference clock of the serializer driving the deserializer. The frequen-

cy of TCLK must be within ±400ppm of the REFCLK frequency.

AC ELECTRICAL CHARACTERISTICS (continued)

(V

AVCC

= V

DVCC

= +3.0V to +3.6V, CL= 15pF, differential input voltage |V

ID

| = 0.15V to 1.2V, common-mode voltage V

CM

= |VID/2|

to 2.4V - |VID/2|, TA= -40°C to +85°C, unless otherwise noted. Typical values are at V

AVCC

= V

DVCC

= +3.3V, VCM= 1.1V, |V

ID

| =

0.2V, T

A

= +25°C.) (Notes 4, 5)

10-Bit Bus LVDS Deserializers

4 _______________________________________________________________________________________

PLL Lock Time (from Start of
Sync Patterns)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

PLL locked to stable REFCLK; supply

t

DSR2

stable; static input; measured from
start of sync patterns at input to LOCK
transition low; Figure 8

42 x t

RFCP

ns

LOCK High-Z to High-State
Delay

Input Jitter Tolerance tJT Figure 9

t

ZHLK

Figure 7 30 ns

MAX9206

MAX9208

16MHz 1300

45MHz 720

40MHz 720

60MHz 320

ps