General Description
The MAX9180 is a 400Mbps, low-voltage differential
signaling (LVDS) repeater, which accepts a single
LVDS input and duplicates the signal at a single LVDS
output. Its low-jitter, low-noise performance makes it
ideal for buffering LVDS signals sent over long distances or noisy environments, such as cables and
backplanes.
The MAX9180’s tiny size makes it especially suitable for
minimizing stub lengths in multidrop backplane applications. The SC70 package (half the size of a SOT23)
allows the MAX9180 to be placed close to the connector, thereby minimizing stub lengths and reflections on
the bus. The point-to-point connection between the
MAX9180 output and the destination IC, such as an
FPGA or ASIC, allows the destination IC to be located
at greater distances from the bus connector.
Ultra-low, 23ps
P-P
added deterministic jitter and
0.6ps
RMS
added random jitter ensure reliable communication in high-speed links that are highly sensitive to
timing errors, especially those incorporating clock-anddata recovery, PLLs, serializers, or deserializers. The
MAX9180’s switching performance guarantees a
400Mbps data rate, but minimizes radiated noise by
guaranteeing 0.5ns minimum output transition time.
The MAX9180 has fail-safe circuitry that sets the output
high for undriven open, short, or terminated inputs.
The MAX9180 operates from a single 3.3V supply and
consumes only 10mA over a -40°C to +85°C temperature range. Refer to the MAX9129 data sheet for a quad
bus LVDS (BLVDS) driver, and to the MAX9181 data
sheet for a low-jitter, low-noise 400Mbps LVPECL-toLVDS level translator in an SC70 package.
Applications
Cellular Phone Base Stations
DSLAMs
Digital Cross-Connects
Add/Drop Muxes
Network Switches/Routers
Multidrop Buses
Cable Repeaters
Features
♦ Tiny SC70 Package
♦ Ultra-Low Jitter
23ps
P-P
Added Deterministic Jitter
(2
23
- 1 PRBS)
0.6ps
RMS
Added Random Jitter
♦ 0.5ns (min) Transition Time Minimizes Radiated
Noise
♦ 400Mbps Guaranteed Data Rate
♦ Fail-Safe Circuit Sets Output High for Undriven
Inputs (Open, Terminated, or Shorted)
♦ Low 10mA Supply Current
♦ Low 6mA Supply Current in Fail-Safe
♦ Conforms to ANSI/EIA/TIA-644 LVDS Standard
♦ High-Impedance Inputs and Outputs in
Power-Down Mode
MAX9180
400Mbps, Low-Jitter, Low-Noise LVDS
Repeater in an SC70 Package
________________________________________________________________ Maxim Integrated Products 1
GND
IN+IN-
16OUT+
5V
CC
OUT-
MAX9180
SC70
TOP VIEW
2
34
Pin Configuration
19-2376; Rev 1; 2/04
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Ordering Information
PART
TEMP RANGE
PIN -
TOP
M ARK
MAX9180EXT-T
6 SC70-6
ABH
Typical Operating Circuit appears at end of data sheet.
PA C K A G E
-40°C to +85°C
MAX9180
400Mbps, Low-Jitter, Low-Noise LVDS
Repeater in an SC70 Package
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCCto GND...........................................................-0.3V to +4.0V
IN+, IN- to GND.....................................................-0.3V to +4.0V
OUT+, OUT- to GND .............................................-0.3V to +4.0V
Short-Circuit Duration (OUT+, OUT-).........................Continuous
Continuous Power Dissipation (T
A
= +70°C)
6-Pin SC70 (derate 3.1mW/°C above +70°C)..............245mW
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature......................................................+150°C
Operating Temperature Range ...........................-40°C to +85°C
ESD Protection
Human Body Model, IN+, IN-, OUT+, OUT-....................±8kV
Lead Temperature (soldering, 10s) .................................+300°C
DC ELECTRICAL CHARACTERISTICS
(VCC= 3.0V to 3.6V, RL= 100Ω ±1%, |V
ID
|
= 0.05V to 1.2V, VCM= |VID/ 2|to 2.4V - |VID/ 2|, TA= -40°C to +85°C, unless otherwise
noted. Typical values are at V
CC
= 3.3V, TA= +25°C.) (Notes 1, 2)
PARAMETER
CONDITIONS
U N I T S
LVDS INPUT
Differential Input High Threshold
V
TH
750mV
Differential Input Low Threshold V
TL
-50 -7 mV
0.05V ≤ |V
ID
|
≤ 0.6V -15
Input Current
0.6V < |V
ID
|
≤ 1.2V -20
µA
0.05V ≤ |V
ID
|
≤ 0.6V, V
CC
= 0V -15
Power-Off Input Current
0.6V < |V
ID
|
≤ 1.2V, V
CC
= 0V -20
µA
Input Resistor 1 R
IN1
VCC = 3.6V or 0V, Figure 1 67
kΩ
Input Resistor 2 R
IN2
VCC = 3.6V or 0V, Figure 1 267
kΩ
LVDS OUTPUT
Differential Output Voltage V
OD
Figure 2 250
mV
Change in VOD Between
Complementary Output States
∆V
OD
Figure 2
25 mV
Offset (Common-Mode) Voltage
V
OS
Figure 2
V
Change in VOS for
Complementary Output States
∆V
OS
Figure 2
25 mV
Output High Voltage V
OH
1.6 V
Output Low Voltage V
OL
0.9
V
Fail-Safe Differential Output
Voltage
V
OD+
IN+, IN- shorted, open, or parallel
terminated
mV
-10
Power-Off Output Leakage
Current
O U T- = 3.6V , other outp ut op en -10
µA
Differential Output Resistance
VCC = 3.6V or 0V 100
Ω
VID = 50mV, OUT+ = GND -5 -15
Output Short Current I
SC
VID = -50mV, OUT- = GND -5 -15
mA
POWER SUPPLY
Supply Current I
CC
Output loaded 10 15
mA
Supply Current in Fail-Safe I
CCF
Output loaded, input undriven 6 8
mA
SYMBOL
MIN TYP MAX
I
, I
IN+
IN-
I
, I
IN+
IN-
IO
RO
OFF
VCC = 0V
DIFF
O U T+ = 3.6V , other outp ut op en
1.125 1.25 1.375
+250 +360 +450
-2.5 +15
-3.5 +20
+1.3 +15
+2.6 +20
232
1174
360 450
0.008
0.005
1.44
1.08
+0.02 +10
+0.02 +10
260 400
MAX9180
400Mbps, Low-Jitter, Low-Noise LVDS
Repeater in an SC70 Package
_______________________________________________________________________________________ 3
Note 1: All devices are 100% tested at TA= +25°C. Limits over temperature are guaranteed by design and characterization.
Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except V
TH
, VTL, VOD, and ∆VOD.
Note 3: Guaranteed by design and characterization.
Note 4: Signal generator output (unless otherwise noted): frequency = 200MHz, 50% duty cycle, R
O
= 50Ω, tR= 1.5ns, and tF=
1.5ns (0% to 100%).
Note 5: C
L
includes scope probe and test jig capacitance.
Note 6: Signal generator output for t
DJ
: VOD= 150mV, VOS= 1.2V, tDJincludes pulse (duty-cycle) skew.
Note 7: Signal generator output for t
RJ
: VOD= 150mV, VOS= 1.2V.
Note 8: t
SKPP1
is the magnitude difference of any differential propagation delays between devices operating over rated conditions
at the same supply voltage, input common-mode voltage, and ambient temperature.
Note 9: t
SKPP2
is the magnitude difference of any differential propagation delays between devices operating over rated conditions.
Note 10: Device meets V
OD
DC specification and AC specifications while operating at f
MAX
.
Note 11: Jitter added to the input signal.
AC ELECTRICAL CHARACTERISTICS
(VCC= 3.0V to 3.6V, RL= 100Ω ±1%, CL= 10pF, |V
ID
|
= 0.15V to 1.2V, VCM= |VID/ 2|to 2.4V - |VID/ 2|, TA= -40°C to +85°C, unless
otherwise noted. Typical values are at V
CC
= 3.3V, TA= +25°C.) (Notes 3, 4, 5) (Figures 3, 4)
PARAMETER
CONDITIONS
Differential Propagation Delay High to
Low
1.3 2.0 2.8 ns
Differential Propagation Delay Low to
High
1.3 2.0 2.8 ns
Added Deterministic Jitter t
DJ
400Mbps 223- 1 PRBS data pattern
(Notes 6, 11)
23
Added Random Jitter t
RJ
fIN = 200MHz (Notes 7, 11) 0.6 2.9
(Note 8)
0.6 ns
Differential Part-to-Part Skew
(Note 9) 1.5 ns
Switching Supply Current
18
Rise Time t
TLH
0.5
1.0 ns
Fall Time t
THL
0.5
1.0 ns
Input Frequency f
MAX
(Note 10) 200
SYMBOL
MIN TYP MAX U N I T S
t
PHLD
t
PLHD
t
SKPP1
t
SKPP2
I
CCSW
0.16
12.2
0.67
0.66
100 ps
P-P
ps
RMS
mA
MHz
MAX9180
400Mbps, Low-Jitter, Low-Noise LVDS
Repeater in an SC70 Package
4 _______________________________________________________________________________________
0
6
3
12
9
18
21
15
010050 150 20025 12575 175 225 250
SUPPLY CURRENT
VS. INPUT FREQUENCY
MAX9180 toc01
INPUT FREQUENCY (MHz)
SUPPLY CURRENT (mA)
11.00
11.25
11.50
11.75
12.00
12.25
12.50
12.75
13.00
-40 -15 10 35 60 85
SWITCHING SUPPLY CURRENT
VS. TEMPERATURE
MAX9180 toc02
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
5.05
5.06
5.08
5.07
5.09
5.10
3.0 3.23.1 3.3 3.4 3.5 3.6
OUTPUT SHORT-CIRCUIT CURRENT
VS. SUPPLY VOLTAGE
MAX9180 toc03
SUPPLY VOLTAGE (V)
OUTPUT SHORT-CIRCUIT CURRENT (mA)
5.5
5.7
6.1
5.9
6.3
6.5
3.0 3.23.1 3.3 3.4 3.5 3.6
FAIL-SAFE SUPPLY CURRENT
VS. SUPPLY VOLTAGE
MAX9180 toc04
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
1.05
1.07
1.06
1.09
1.08
1.11
1.10
1.12
3.0 3.2 3.33.1 3.4 3.5 3.6
OUTPUT LOW VOLTAGE
VS. SUPPLY VOLTAGE
MAX9180 toc05
SUPPLY VOLTAGE (V)
OUTPUT LOW VOLTAGE (V)
1.350
1.375
1.400
1.425
1.450
1.475
1.500
1.525
1.550
3.0 3.23.1 3.3 3.4 3.5 3.6
OUTPUT HIGH VOLTAGE
VS. SUPPLY VOLTAGE
MAX9180 toc06
SUPPLY VOLTAGE (V)
OUTPUT HIGH VOLTAGE (V)
2.1
2.0
1.9
1.8
1.7
3.0 3.33.1 3.2 3.4 3.5 3.6
DIFFERENTIAL PROPAGATION DELAY
VS. SUPPLY VOLTAGE
MAX9180 toc07
SUPPLY VOLTAGE (V)
DIFFERENTIAL PROPAGATION DELAY (ns)
t
PHLD
t
PLHD
1.5
1.7
2.1
1.9
2.3
2.5
-40 10-15 35 60 85
DIFFERENTIAL PROPAGATION DELAY
VS. TEMPERATURE
MAX9180 toc08
TEMPERATURE (°C)
DIFFERENTIAL PROPAGATION DELAY (ns)
t
PHLD
t
PLHD
550
575
600
625
650
675
700
725
750
3.0 3.23.1 3.3 3.4 3.5 3.6
TRANSITION TIME
VS. SUPPLY VOLTAGE
MAX9180 toc09
SUPPLY VOLTAGE (V)
TRANSITION TIME (ps)
t
THL
t
TLH
Typical Operating Characteristics
(VCC= 3.3V, RL= 100Ω ±1%, CL= 10pF, |V
ID
|
= 0.2V, VCM= 1.2V, TA= +25°C, unless otherwise noted. Signal generator output:
frequency = 200MHz, 50% duty cycle, R
O
= 50Ω, tR= 1.5ns, and tF= 1.5ns (0% to 100%), unless otherwise noted.)
Detailed Description
The LVDS interface standard is a signaling method
intended for point-to-point communication over a controlled-impedance medium, as defined by the ANSI/
TIA/EIA-644 and IEEE 1596.3 standards. The LVDS
standard uses a lower voltage swing than other common communication standards, achieving higher data
rates with reduced power consumption while reducing
EMI emissions and system susceptibility to noise.
The MAX9180 is a 400Mbps LVDS repeater intended
for high-speed, point-to-point, low-power applications.
The MAX9180 accepts an LVDS input and reproduces
an LVDS signal at the output. This device is capable of
detecting differential signals as low as 50mV and as
high as 1.2V within a 0 to 2.4V input voltage range. The
LVDS standard specifies an input voltage range of 0 to
2.4V referenced to ground.
Fail-Safe
Fail-safe is a feature that puts the output in a known
logic state (differential high) under certain fault conditions. The MAX9180 outputs are differential high when
the inputs are undriven and open, terminated, or shorted
(Table 1).
MAX9180
400Mbps, Low-Jitter, Low-Noise LVDS
Repeater in an SC70 Package
_______________________________________________________________________________________ 5
400
450
500
550
600
650
700
750
800
-40 -15 10 35 60 85
TRANSITION TIME
VS. TEMPERATURE
MAX9180 toc10
TEMPERATURE (°C)
TRANSITION TIME (ps)
t
TLH
, t
THL
0
200
100
400
300
500
600
25 150
DIFFERENTIAL OUTPUT VOLTAGE
VS. LOAD RESISTOR
MAX9180 toc11
LOAD RESISTOR (Ω)
DIFFERENTIAL OUTPUT VOLTAGE (mV)
7550 100 125
Typical Operating Characteristics (continued)
(VCC= 3.3V, RL= 100Ω ±1%, CL= 10pF, |V
ID
|
= 0.2V, VCM= 1.2V, TA= +25°C, unless otherwise noted. Signal generator output:
frequency = 200MHz, 50% duty cycle, R
O
= 50Ω, tR= 1.5ns, and tF= 1.5ns (0% to 100%), unless otherwise noted.)
Pin Description
PIN NAME FUNCTION
1 OUT- Inverting LVDS Output
2 GND Ground
3 IN- Inverting LVDS Input
4 IN+ Noninverting LVDS Input
5V
CC
Power Supply. Bypass VCC to GND
with a 0.01µF ceramic capacitor.
6 OUT+ Noninverting LVDS Output
Note: VID= (IN+ - IN-), VOD= (OUT+ - OUT-)
High = 450mV ≥ V
OD
≥ 250mV
Low = -250mV ≥ V
OD
≥ -450mV
Table 1. Function Table for LVDS Fail-Safe
Input (Figure 2)
INPUT, V
50mV > VID > -50mV Indeterminate
Undriven open, short, or terminated High
ID
> 50mV High
< -50mV Low
OUTPUT, V
OD
MAX9180
Applications Information
Supply Bypassing
Bypass VCCwith a high-frequency surface-mount ceramic 0.01µF capacitor as close to the device as possible.
Differential Traces
Input and output trace characteristics affect the performance of the MAX9180. Use controlled-impedance differential traces. Ensure that noise couples as common
mode by running the traces within a differential pair
close together.
Maintain the distance within a differential pair to avoid
discontinuities in differential impedance. Avoid 90°
turns and minimize the number of vias to further prevent
impedance discontinuities.
Cables and Connectors
The LVDS standards define signal levels for interconnect with a differential characteristic impedance and
termination of 100Ω. Interconnects with a characteristic
impedance and termination of 90Ω to 132Ω impedance
are allowed, but produce different signal levels (see the
Termination section).
Use cables and connectors that have matched differential impedance to minimize impedance discontinuities.
Avoid the use of unbalanced cables, such as ribbon or
coaxial cable. Balanced cables, such as twisted pair,
offer superior signal quality and tend to generate less
EMI due to canceling effects. Balanced cables tend to
pick up noise as common mode, which is rejected by
the LVDS receiver.
Termination
For point-to-point links, the termination resistor should
be located at the LVDS receiver input and match the
differential characteristic impedance of the transmission line.
For a multidrop bus driven at one end, terminate at the
other end of the bus with a resistor that matches the
loaded differential characteristic impedance of the bus.
For a multidrop bus driven from a point other than the
end, terminate each end of the bus with a resistor that
matches the loaded differential characteristic impedance of the bus. When terminating at both ends, or for a
large number of drops, a BLVDS driver is needed to
drive the bus to LVDS signal levels. The MAX9180 is
not intended to drive double-terminated multidrop
buses to LVDS levels.
The differential output voltage level depends upon the
differential characteristic impedance of the interconnect
and the value of the termination resistance. The
MAX9180 is guaranteed to produce LVDS output levels
into 100Ω. With the typical 3.6mA output current, the
MAX9180 produces an output voltage of 360mV when
driving a 100Ω transmission line terminated with a
100Ω termination resistor (3.6mA x 100Ω = 360mV). For
typical output levels with different loads, see the
Differential Output Voltage vs. Load Resistor curve in
the Typical Operating Characteristics.
Chip Information
TRANSISTOR COUNT: 401
PROCESS: CMOS
400Mbps, Low-Jitter, Low-Noise LVDS
Repeater in an SC70 Package
6 _______________________________________________________________________________________
MAX9180
400Mbps, Low-Jitter, Low-Noise LVDS
Repeater in an SC70 Package
_______________________________________________________________________________________ 7
Figure 1. LVDS Fail-Safe Input
OUT+IN+
IN-
V
CC
VCC - 0.3V
R
IN1
/2
R
IN2
R
IN1
/2
OUT-
Figure 2. DC Load Test Circuit
V
OD
1.25V
IN+
IN-
1.20V
1.25V
1.20V
R
L
/2
R
L
/2
OUT-
OUT+
V
OS
Figure 3. Transition Time and Propagation Delay Test Circuit
C
L
PULSE
GENERATOR
IN+
IN-
R
L
50Ω50Ω
OUT-
OUT+
C
L
Test Circuit and Timing Diagrams
MAX9180
400Mbps, Low-Jitter, Low-Noise LVDS
Repeater in an SC70 Package
8 _______________________________________________________________________________________
Test Circuit and Timing Diagrams (continued)
Figure 4. Transition Time and Propagation Delay Timing Diagram
IN-
V
CM
= ((IN+) + (IN-))/2
V
DIFF
= (OUT+) - (OUT-)
IN+
OUT-
OUT+
t
PLHD
t
TLH
t
THL
t
PHLD
OV (DIFFERENTIAL)
OV (DIFFERENTIAL)
OV (DIFFERENTIAL)
80% 80%
20% 20%
OV (DIFFERENTIAL)
OV (DIFFERENTIAL)
OV (DIFFERENTIAL)
V
DIFF
VID
Typical Operating Circuit
1/4
MAX9129
REPEATERS REDUCE ASIC OR FPGA STUB LENGTH ON A MULTIDROP BUS.
1/4
MAX9121
100Ω 100Ω
MAX9180
1/4
MAX9121
MAX9180
WITHOUT
REPEATER
STUB WITH
REPEATER
STUB
MAX9180
400Mbps, Low-Jitter, Low-Noise LVDS
Repeater in an SC70 Package
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9
© 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
SC70, 6L.EPS
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
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