MAXIM MAX9179 User Manual

General Description

The MAX9179 is a quad low-voltage differential
signaling (LVDS) line receiver designed for applications
requiring high data rates, low power dissipation, and
noise immunity. The receiver accepts four LVDS input
signals and translates them to 3.3V LVCMOS output lev­els at speeds up to 400Mbps. The receiver features
built-in hysteresis, which improves noise immunity and
prevents multiple switching on slow transitioning inputs.

The device supports a wide 0.038V to 2.362V common­mode input voltage range, allowing for ground potential
differences and common-mode noise between the driver
and the receiver. A fail-safe circuit sets the output high
when the input is open, undriven and shorted, or undriven
and terminated. Common enable inputs control the high­impedance outputs.

The MAX9179 has a flow-through pinout for easy PC
board layout, and is pin compatible with the MAX9121
and the DS90LV048A with the additional features of
high ESD tolerance and built-in hysteresis.

The MAX9179 operates from a single 3.3V supply, and is
specified for operation from -40°C to +85°C. The device
is offered in 16-pin TSSOP and thin QFN packages.

Applications

Laser Printers

Digital Copiers

Cell-Phone Base Stations

Telecom Switching Equipment

LCD Displays

Network Switches/Routers

Backplane Interconnect

Clock Distribution

Features

♦ Guaranteed 400Mbps Data Rate

♦ 50mV (typ) Hysteresis

♦ Overshoot/Undershoot Protection (-1.0V or V

CC

+

1.0V) on Enables

♦ IEC61000-4-2 Level 4 ESD Tolerance

♦ AC Specifications Guaranteed with |V

ID|=

100mV

♦ Single 3.3V Supply

♦ Fail-Safe Circuit

♦ Flow-Through Pinout

Simplifies PC Board Layout
Reduces Crosstalk

♦ Low-Power CMOS Design

♦ Conforms to ANSI TIA/EIA-644 LVDS Standard

♦ High-Impedance Inputs when Powered Off

♦ Pin Compatible with the MAX9121 and the

DS90LV048A

♦ Small Thin QFN Package Available

MAX9179

Quad LVDS Receiver with Hysteresis

________________________________________________________________ Maxim Integrated Products 1

Ordering Information

19-2752; Rev 0; 2/03

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Pin Configurations

Functional Diagram appears at end of data sheet.

*Future product—contact factory for availability.
**EP = Exposed paddle.

PART TEMP RANGE PIN-PACKAGE

MAX9179EUE -40°C to +85°C 16 TSSOP

MAX9179ETE* -40°C to +85°C 16 Thin QFN-EP**

TOP VIEW

IN1-

IN1+

IN2+

IN2-

IN3-

IN3+

IN4+

IN4-

EN

1

2

3

MAX9179

4

5

6

7

8

TSSOP

16

OUT1

15

OUT2

14

V

13

CC

12

GND

OUT3

11

10

OUT4

EN

9

16 15 14 13

IN2+

1

2

IN2-

IN3-

IN3+

(LEADS UNDER PACKAGE)

MAX9179

3

EXPOSED PAD

4

5678

THIN QFN

OUT1IN1-IN1+ EN

OUT4IN4-IN4+

EN

12

OUT2

11

V

CC

10

GND

9

OUT3

MAX9179

Quad LVDS Receiver with Hysteresis

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

DC ELECTRICAL CHARACTERISTICS

(VCC= 3.0V to 3.6V, differential input voltage |VID| = 0.075V to 1.2V, input common-mode voltage VCM= |VID/2| to 2.4V - |VID/2|,
T

A

= -40°C to +85°C, unless otherwise noted. Typical values are at VCC= 3.3V, |VID| = 0.2V, VCM= 1.2V, TA= +25°C.) (Notes 1, 2)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

VCCto GND...........................................................-0.3V to +4.0V

IN_+, IN_- to GND .................................................-0.3V to +4.0V

EN, EN to GND...........................................-1.4V to (V

CC

+ 1.4V)

OUT_ to GND .............................................-0.3V to (V

CC

+ 0.3V)

Continuous Power Dissipation (T

A

= +70°C)

16-Pin TSSOP (derate 9.4mW/°C above +70°C) .........755mW

16-Pin Thin QFN (derate 16.9mW/°C

above +70°C).............................................................1349mW

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-65°C to +150°C

ESD Protection

Human Body Model (R

D

= 1.5kΩ, CS= 100pF)

(IN_+, IN_-) ................................................................±16kV

IEC61000-4-2 (R

D

= 330Ω, CS= 150pF) (IN_+, IN_-)

Contact Discharge .......................................................±8kV

Air-Gap Discharge .....................................................±15kV

Soldering Temperature (soldering, 10s) ..........................+300°C

INPUTS (IN_+, IN_-)

Differential Input High Threshold V

Differential Input Low Threshold V

Hysteresis V

Input Current I

Power-Off Input Current

Fail-Safe Input Resistor 1 R

Fail-Safe Input Resistor 2 R

OUTPUTS (OUT_)

Output High Voltage V

Output Low Voltage V

Output Short-Circuit Current I

Output High-Impedance Current I

ENABLE INPUTS (EN, EN)

Input High Voltage V

Input Low Voltage V

POWER SUPPLY

Supply Current I

Disabled Supply Current I

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Figure 1 25 75 mV

TH

Figure 1 -75 -25 mV

TL

- VTLFigure 1 50 mV

TH

IN+, IIN-

I

OFF+,

I

OFF-

IN1

IN2

OH

OS

OZ

OL

IH

IL

V

= 0V -20 +20 µA

CC

V

= 3.6V or 0V, Figure 2 40 65 kΩ

CC

V

= 3.6V or 0V, Figure 2 280 455 kΩ

CC

IOH = -4.0mA

IOL = 4.0mA, V

Enabled, V

Disabled, V

ID

OUT

-1.0V ≤ EN, EN ≤ 0V -1800 +10

IN

0V ≤ EN, EN ≤ V

VCC ≤ EN, EN ≤ VCC + 1.0V -10 +1800

CC

CCZ

Enabled, inputs open 10.4 15

Disabled, inputs open 0.6 1.0

-20 +20 µA

Open, undriven short, or
undriven parallel
termination

= +50mV

V

ID

= -50mV 0.1 0.25 V

ID

= +50mV, V

= 0 or V

= 0 (Note 3) -40 -70 -120 mA

OUT

CC

V

-

VCC -

CC

0.2

0.1

-1.0 +1.0 µA

V

2.0

CC

1.0

-1.0 +0.8 V

CC

-20 +20Input Current I

+

V

V

µA

mA

MAX9179

Quad LVDS Receiver with Hysteresis

_______________________________________________________________________________________ 3

Note 1: Maximum and minimum limits over temperature are guaranteed by design and characterization. Parts are production

tested at T

A

= +25°C.

Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground

except V

TH

, VTL, and VID.

Note 3: Short one output at a time.
Note 4: AC parameters are guaranteed by design and characterization. Limits are set at ±6 sigma.
Note 5: C

L

includes scope probe and test jig capacitance.

Note 6: Pulse generator differential output for all tests (unless otherwise noted): t

R

= tF< 1ns (0% to 100%), frequency = 100MHz,

50% duty cycle.

Note 7: t

SKD1

is the magnitude of the difference of the differential propagation delays in a channel. t

SKD1

= | t

PHLD

- t

PLHD

|.

Note 8: t

SKD2

is the magnitude of the difference of the t

PLHD

or t

PHLD

of one channel and the t

PLHD

or t

PHLD

of the other channel

on the same part.

Note 9: t

SKD3

is the magnitude of the difference of any differential propagation delays between parts at the same VCCand within

5°C of each other.

Note 10: t

S

KD4

is the magnitude of the difference of any differential propagation delays between parts operating over the rated

supply and temperature ranges.

Note 11: Pulse generator output for t

PHZ

, t

PLZ

, t

PZH

, and t

PZL

tests: tR= tF= 1.5ns (0.2VCCto 0.8VCC), 50% duty cycle, VOH=

V

CC

+ 1.0V settling to VCC, VOL= -1.0V settling to 0, frequency = 1MHz.

AC ELECTRICAL CHARACTERISTICS

(VCC= 3.0V to 3.6V, CL= 15pF, differential input voltage |VID| = 0.1V to 1.2V, input common-mode voltage VCM= |VID/2| to 2.4V - |VID/2|,
T

A

= -40°C to +85°C, unless otherwise noted. Typical values are at VCC= 3.3V, |VID| = 0.2V, VCM= 1.2V, TA= +25°C.) (Notes 4, 5, 6)

Differential Propagation Delay
High to Low

Differential Propagation Delay
Low to High

Differential Pulse Skew
| t

PHLD

Differential Channel-to-Channel
Skew, Same Part
(Note 8)

Differential Part-to-Part Skew
(Note 9)

Differential Part-to-Part Skew
(Note 10)

Rise Time t

Fall Time t

Disable Time High to Z

Disable Time Low to Z t

Enable Time Z to High t

Enable Time Z to Low t

Maximum Operating Frequency f

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

t

PHLD

t

PLHD

Figures 3, 4 2.0 2.6 4.6 ns

Figures 3, 4 2.0 2.52 4.6 ns

|VID| = 0.1V to 0.15V 700

- t

PLHD

| (Note 7)

t

SKD1

|VID| = 0.15V to 0.2V 400

|VID| = 0.2V to 1.2V 80 300

|VID| = 0.1V to 0.15V 900

t

SKD2

|VID| = 0.15V to 0.2V 600

|VID| = 0.2V to 1.2V 120 400

t

SKD3

t

SKD4

TLH

THL

t

PHZ

PLZ

PZH

PZL

MAX

0.77 1.4 ns

0.74 1.4 ns

RL = 2kΩ, Figures 5, 6 (Note 11) 10.6 14 ns

RL = 2kΩ, Figures 5, 6 (Note 11) 11 14 ns

RL = 2kΩ, Figures 5, 6 (Note 11) 4.8 14 ns

RL = 2kΩ, Figures 5, 6 (Note 11) 4.8 14 ns

All channels switching, CL = 15pF, V
(max) = 0.25V, VOH (min) = VCC - 0.2V,

OL

200 250 MHz

2.0 ns

2.6 ns

44% < duty cycle < 56%

ps

ps

MAX9179

Quad LVDS Receiver with Hysteresis

4 _______________________________________________________________________________________

Test Circuits/Timing Diagrams

Figure 1. Input Thresholds and Hysteresis

Figure 2. Fail-Safe Input Circuit

Figure 3. Propagation Delay and Transition Time Test Circuit

Figure 4. Propagation Delay and Transition Time Waveforms

Figure 5. High-Impedance Delay Test Circuit

Figure 6. High-Impedance Delay Waveforms

IN_-

IN_+

OUT_

(0V DIFFERENTIAL) V

t

PLHD

0.9V

CC

0.5V

CC

0.1V

CC

V

OUT

V

TL

V

TH

V

OH

t

PHLD

VCM = ((V

) + (V

ID

0.9V

CC

0.5V

CC

0.1V

CC

))/2

IN_+

IN_-

-V

ID

HYSTERESIS

V

CC

R

IN2

IN_+

R

IN1

R

IN1

VCC - 0.3V

IN_-

PULSE

GENERATOR

IN_+

IN_-

50Ω50Ω

t

TLH

V

OL

+V

ID

= 0

V

ID

INCLUDES LOAD AND TEST JIG CAPACITANCE.

C

L

= VCC FOR t

S

1

= 0 FOR t

S

1

PZH

PZL

AND t

AND t

MEASUREMENTS.

PLZ

MEASUREMENTS.

PHZ

EN

PULSE

GENERATOR

50Ω

EN

IN_+

IN_-

t

THL

V

CC

DEVICE
UNDER

TEST

S

1

R

L

OUT_

C

L

OUT_

VCC + 1.0V
V

CC

EN WHEN EN = LOW OR OPEN

EN WHEN EN = HIGH

OUT_

C

L

OUT_ WHEN VID = -75mV

OUT_ WHEN V

= +75mV

ID

1.5V 1.5V

1.5V 1.5V

t

PLZ

t

PHZ

0.5V

0.5V

0

-1.0V

V

+ 1.0V

CC

V

CC

0

50%

50%

V

V

V

0

-1.0V

CC

OL

OH

t

PZL

t

PZH