General Description
The MAX9176/MAX9177 are 670MHz, low-jitter, lowskew 2:1 multiplexers ideal for protection switching,
loopback, and clock distribution. The devices feature
ultra-low 68ps peak-to-peak deterministic jitter that
ensures reliable operation in high-speed links that are
highly sensitive to timing errors.
The MAX9176 has fail-safe LVDS inputs and an LVDS
output. The MAX9177 has “anything” differential inputs
(CML/LVDS/LVPECL) and an LVDS output. The output
can be put into high impedance using the power-down
input. The MAX9176 features fail-safe circuits that drive
the output high when a selected input is open, undriven
and shorted, or undriven and terminated. The MAX9177
has bias circuits that force the output high when a
selected input is open. The mux select and powerdown inputs are compatible with standard LVTTL/
LVCMOS logic.
The select and power-down inputs tolerate undershoot
of -1V and overshoot of V
CC
+ 1V. The MAX9176/
MAX9177 are available in 10-pin µMAX and 10-lead
thin QFN packages, and operate from a single 3.3V
supply over the -40°C to +85°C temperature range.
Applications
Protection Switching
Loopback
Clock Distribution
Features
♦ 1.0ps
(RMS)
Jitter (max) at 670MHz
♦ 68ps
(P-P)
Jitter at 800Mbps Data Rate
♦ 3.3V Supply
♦ LVDS Fail-Safe Inputs (MAX9176)
♦ Anything Inputs (MAX9177) Accept
CML/LVDS/LVPECL
♦ Select and Power-Down Inputs Tolerate -1.0V
and V
CC
+ 1.0V
♦ Low-Power CMOS Design
♦ 10-Lead µMAX and QFN Packages
♦ -40°C to +85°C Operating Temperature Range
♦ Conform to ANSI TIA/EIA-644 LVDS Standard
♦ IEC61000-4-2 Level 4 ESD Rating
MAX9176/MAX9177
670MHz LVDS-to-LVDS and
Anything-to-LVDS 2:1 Multiplexers
________________________________________________________________ Maxim Integrated Products 1
Pin Configurations
Ordering Information
19-2757; Rev 0; 1/03
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Functional Diagram appears at end of data sheet.
*Future product—contact factory for availability.
**EP = Exposed paddle.
PART TEMP RANGE PIN-PACKAGE
MAX9176EUB -40°C to +85°C 10 µMAX
MAX9176ETB* -40°C to +85°C 10 Thin QFN-EP**
MAX9177EUB -40°C to +85°C 10 µMAX
MAX9177ETB* -40°C to +85°C 10 Thin QFN-EP**
TOP VIEW
1
1
IN0+
2
INO-
GND
MAX9176
3
4
5
µMAX
10
OUT+
9
OUT-
8
V
CC
7
PDIN1+
SELIN1-
6
IN0+
2
INO-
3
GND
4
5
(LEADS UNDER PACKAGE)
EXPOSED
PAD
QFN
10
OUT+
9
OUT-
8
V
CC
7
PDIN1+
SELIN1-
6
MAX9176/MAX9177
670MHz LVDS-to-LVDS and
Anything-to-LVDS 2:1 Multiplexers
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(VCC= 3.0V to 3.6V, RL= 100Ω, PD = high, SEL = high or low, differential input voltage |VID| = 0.05V to 1.2V, MAX9176 input common-mode voltage V
CM
= |VID/2| to 2.4V - |VID/2|, MAX9177 input common-mode voltage VCM= |VID/2| to VCC- |VID/2|, TA= -40°C to
+85°C, unless otherwise noted. Typical values are at V
CC
= 3.3V, |VID| = 0.2V, V
CM
= 1.25V, TA= +25°C.) (Notes 1, 2, 3)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCCto GND...........................................................-0.3V to +4.0V
IN_+, IN_- to GND .................................................-0.3V to +4.0V
OUT+, OUT- to GND .............................................-0.3V to +4.0V
PD, SEL to GND .........................................-1.4V to (V
CC
+ 1.4V)
Single-Ended and Differential Output
Short-Circuit Duration (OUT+, OUT-) ......................Continuous
Continuous Power Dissipation (T
A
= +70°C)
10-Pin µMAX (derate 5.6mW/°C above +70°C) ............444mW
10-Lead Thin QFN (derate 24.4mW/°C above +70°C)..1951mW
Operating Temperature Range ...........................-40°C to +85°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range .............................-65°C to +150°C
ESD Protection
Human Body Model (R
D
= 1.5kΩ, CS= 100pF)
(IN_+, IN_-, OUT+, OUT-) ...............................................+
16kV
IEC61000-4-2 Level 4 (R
D
= 330Ω, CS= 150pF)
Contact Discharge (IN_+, IN_-, OUT+, OUT-).................+
8 kV
Air-Gap Discharge (IN_+, IN_-, OUT+, OUT-)................+
15kV
Lead Temperature (soldering, 10s) .................................+300°C
DIFFERENTIAL INPUTS (IN_+, IN_-)
Differential Input High Threshold V
Differential Input Low Threshold V
Input Current I
Power-Off Input Current
Fail-Safe Input Resistors
(MAX9176)
Input Resistors
(MAX9177)
Input Capacitance C
LVTTL/LVCMOS INPUTS (SEL, PD)
Input High Voltage V
Input Low Voltage V
LVDS OUTPUT (OUT+, OUT-)
Differential Output Voltage V
Change in Differential Output
Voltage Between Logic States
Offset Voltage V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TH
TL
IN+, IIN-
I
INO+,
I
INO-
R
IN1
R
IN2
R
IN3
IN
IH
IL
IN
OD
∆V
OD
OS
Figure 1 -20 +20 µA
MAX9176
MAX9177
V
Figure 1
V
Figure 1
IN_+ or IN_- to GND (Note 4) 4.5 pF
-1.0V ≤ SEL, PD ≤ 0V -1.5 mA
0V ≤ SEL, PD ≤ V
VCC ≤ SEL, PD ≤ VCC + 1.0V +1.5 mA
Figure 2 250 393 475 mV
Figure 2 1.0 15 mV
Figure 3 1.125 1.25 1.375 V
= 3.6V, 0 or open,
CC
= 3.6V, 0 or open,
CC
+50 mV
-50 mV
V
= 0 or open,
CC
Figure 1
= 3.6V or 0,
V
CC
IN+
V
= 3.6V or 0,
IN-
= 0 or open,
V
CC
Figure 1
-20 +20 µA
60 108
200 394
212 450 kΩ
2.0 VCC + 1.0 V
-1.0 +0.8 V
-20 +20 µAInput Current I
kΩ
MAX9176/MAX9177
670MHz LVDS-to-LVDS and
Anything-to-LVDS 2:1 Multiplexers
_______________________________________________________________________________________ 3
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC= 3.0V to 3.6V, RL= 100Ω, PD = high, SEL = high or low, differential input voltage |VID| = 0.05V to 1.2V, MAX9176 input common-mode voltage V
CM
= |VID/2| to 2.4V - |VID/2|, MAX9177 input common-mode voltage VCM= |VID/2| to VCC- |VID/2|, TA= -40°C to
+85°C, unless otherwise noted. Typical values are at V
CC
= 3.3V, |VID| = 0.2V, V
CM
= 1.25V, TA= +25°C.) (Notes 1, 2, 3)
Change in Offset Voltage
Between Logic States
Fail-Safe Differential Output
Voltage (MAX9176)
Differential Output Resistance R
Power-Down Single-Ended
Output Current
Power-Off Single-Ended Output
Current
Output Short-Circuit Current I
Differential Output Short-Circuit
Current Magnitude
Supply Current I
Power-Down Supply Current I
Output Capacitance C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
∆V
OS
V
OD
DIFF
I
PD
I
OFF
OS
I
OSD
CC
CCPD
O
Figure 3 4 15 mV
Figure 2 250 393 475 mV
VCC = 3.6V or 0 95 123 146 Ω
PD = low
PD, SEL = low,
V
VID = +50mV or -50mV, V
VID = +50mV or -50mV, V
VID = +50mV or -50mV, VOD = 0
(Note 4)
RL = 100Ω, PD = VCC, SEL = VCC or 0 26 40 mA
RL = 100Ω, PD = 0, other inputs open 0.5 20 µA
OUT+ or OUT- to GND (Note 4) 5.2 pF
= 0 or open
CC
V
OUT+ =
V
OUT- =
V
OUT- =
V
OUT+ =
V
OUT+ =
V
OUT- =
V
OUT- =
V
OUT+ =
OUT+
OUT-
open,
3.6V or 0
open,
3.6V or 0
open,
3.6V or 0
open,
3.6V or 0
= 0 or V
= 0 or V
CC
CC
-1.0 ±0.01 +1.0 µA
-1.0 ±0.01 +1.0 µA
-15 +15 mA
15 mA
MAX9176/MAX9177
670MHz LVDS-to-LVDS and
Anything-to-LVDS 2:1 Multiplexers
4 _______________________________________________________________________________________
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except V
TH
, VTL, VID, VOD, and ∆VOD.
Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are 100% tested
at T
A
= +25°C.
Note 3: Tolerance on all external resistors (including figures) is ±1%.
Note 4: Guaranteed by design and characterization.
Note 5: AC parameters are guaranteed by design and characterization and not production tested. Limits are set at ±6 sigma.
Note 6: C
L
includes scope probe and test jig capacitance.
Note 7: Pulse-generator output for differential inputs IN_+, IN_- (unless otherwise noted): f = 670MHz, 50% duty cycle, R
O
=
50Ω,
tR= 500ps, and tF= 500ps (0% to 100%). Pulse-generator output for single-ended inputs PD, SEL: tR = tF= 1.5ns (0.2V
CC
to 0.8VCC), 50% duty cycle, VOH= VCC+ 1.0V settling to VCC, V
OL
= -1.0V settling to zero.
Note 8: Pulse-generator output for t
DJ
: VOD= 0.15V, VOS= 1.25V, bit rate = 800Mbps, 223- 1 PRBS, R
O
=
50Ω, t
R
= 500ps, and t
F
= 500ps (0% to 100%).
Note 9: t
SKPP1
is the magnitude of the difference of any differential propagation delays between devices operating under identical
conditions.
Note 10: t
SKPP2
is the magnitude of the difference of any differential propagation delays between devices operating over rated
conditions.
Note 11: Meets all AC specifications.
Note 12: Input jitter subtracted from output jitter.
AC ELECTRICAL CHARACTERISTICS
(VCC= 3.0V to 3.6V, RL= 100Ω, CL= 5pF, differential input voltage |VID| = 0.15V to 1.2V, MAX9176 input common-mode voltage
V
CM
= |VID/2| to 2.4V - |VID/2|, MAX9177 input common-mode voltage VCM= |VID/2| to VCC- |VID/2|, TA= -40°C to +85°C, unless oth-
erwise noted. Typical values are at V
CC
= 3.3V, |VID| = 0.2V, VCM= 1.25V, TA= +25°C.) (Notes 5, 6, 7)
(
)
(
)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DIFFERENTIAL INPUTS (IN_+, IN_-)
High-to-Low Propagation Delay t
Low-to-High Propagation Delay t
PHL
PLH
Figures 4, 5 1.33 2.46 3.23 ns
Figures 4, 5 1.33 2.49 3.31 ns
Added Deterministic Jitter t
Added Random Jitter t
Pulse Skew t
PLH
- t
t
PHL
Part-to-Part Skew
DJ
RJ
SKP
t
SKPP1
t
SKPP2
Rise Time t
Fall Time t
Select to Out Delay t
Power-Down Time t
Power-Up Time t
PSO
PD
PU
Maximum Data Rate DR
Maximum Switching Frequency f
Switching Supply Current I
PRBS Supply Current I
MAX
CCSW
CCPR
Figures 4, 5 (Notes 8, 12) 68 80 ps
Figures 4, 5 (Note 12) 0.7 1.0 ps
Figures 4, 5 27 142 ps
Figures 4, 5 (Note 9) 0.4 1.3
Figures 4, 5 (Note 10) 2.0
Figures 4, 5 217 320 383 ps
R
Figures 4, 5 157 340 360 ps
F
Figure 6 2.0 2.7 ns
Figures 7, 8 6.0 ns
Figures 7, 8 35 µs
Figures 4, 5, VOD ≥ 250mV (Note 11) 800 Mbps
MAX
Figures 4, 5, VOD ≥ 250mV (Note 11) 670 MHz
fIN = 670MHz 38 58
fIN = 155MHz 26 47
DR = 800Mbps, 223 - 1 PRBS input 27 49 mA
P-P
RMS
ns
mA
MAX9176/MAX9177
670MHz LVDS-to-LVDS and
Anything-to-LVDS 2:1 Multiplexers
_______________________________________________________________________________________ 5
Figure 1. Input Structure
Figure 2. V
OD
Test Circuit
Figure 4. Transition Time and Propagation Delay Test Circuit
Figure 3. VOSTest Circuit
Figure 5. Transition Time and Propagation Delay Timing
R
IN2
IN_+
R
IN1
R
IN1
IN_-
1.25V
1.20V
1.25V
1.20V
IN_+
IN_-
V
CC
COMPARATOR
V
0.3V
CC
LVDS RCVR
MAX9176 FAIL-SAFE INPUT
OUT+
V
OD
OUT-
V
CC
R
IN3
TO MUX
5kΩ
=
V
R
L
TEST
0 TO V
CC
PULSE
GENERATOR
5kΩ
IN_+
IN_-
IN_+
IN_-
R
50Ω50Ω
IN3
MAX9177 INPUT
OUT+
OUT-
C
L
C
TO MUX
R
L
5kΩ
V
=
L
5kΩ
TEST
0 TO V
CC
1.25V
1.20V
1.25V
1.20V
IN_+
IN_-
OUT+
RL/2
RL/2
OUT-
IN_-
IN_+
OUT-
V
OS
OUT+
VOS = ((V
OUT+
(OUT+) - (OUT)-
) + (V
OUT-
20%
))/2
t
PLH
80%
0
t
PHL
V
OD+
t
R
80%
0
V
OD-
20%
t
F
MAX9176/MAX9177
670MHz LVDS-to-LVDS and
Anything-to-LVDS 2:1 Multiplexers
6 _______________________________________________________________________________________
Figure 6. Select-to-Out Delay Timing
Figure 7. Power-Up/Down Delay Test Circuit
Figure 8. Power-Up/Down Delay Waveform
IN0-
V
= -0.2V
V
ID
ID
= +0.2V
0.5 V
CC
t
PSO
INO+
IN1+
IN1-
SEL
OUT-
OUT+
0.5 V
t
PSO
CC
PD
t
PU
50%
50%
t
PU
OUT+ WHEN VID = +50mV
OUT- WHEN V
OUT+ WHEN V
OUT- WHEN V
= -50mV
ID
= -50mV
ID
= +50mV
ID
t
PD
50%
50%
t
PD
V
CC
V
CC
0
-1.0V
1.0V + V
V
CC
0.5V
0V
-1.0V
V
OH
1.25V
1.25V
V
OL
+ 1.0V
CC
V
CC
5pF
5pF
OUT+
50Ω
50Ω
OUT-
1.25V
1.25V
1.20V
1.25V
1.20V
GENERATOR
50Ω
IN_+
IN_-
PD
OUT+
MAX9176
MAX9177
OUT-
GND
CC
MAX9176/MAX9177
670MHz LVDS-to-LVDS and
Anything-to-LVDS 2:1 Multiplexers
_______________________________________________________________________________________ 7
Typical Operating Characteristics
((MAX9176) VCC= 3.3V, |VID| = 0.2V, VCM= 1.25V, RL= 100Ω, CL= 5pf, PD = V
CC,
SEL = 0V, IN1+, IN1- = open, TA= +25°C,
unless otherwise noted.)
SUPPLY CURRENT
vs. TEMPERATURE
45
40
35
30
SUPPLY CURRENT (mA)
25
20
-40 85
TEMPERATURE (°C)
DIFFERENTIAL PROPAGATION DELAY
vs. TEMPERATURE
3.00
2.75
2.50
2.25
2.00
1.75
DIFFERENTIAL PROPAGATION DELAY (ns)
1.50
-40 85
t
PLH
TEMPERATURE (°C)
DC SUPPLY CURRENT
vs. SUPPLY VOLTAGE
28
27
26
25
DC SUPPLY CURRENT (mA)
24
23
3.0 3.23.1 3.3 3.4 3.5 3.6
SUPPLY VOLTAGE (V)
t
PHL
fIN = 155MHz
603510-15
603510-15
MAX9176 toc01
DIFFERENTIAL OUTPUT VOLTAGE (mV)
MAX9176 toc04
SUPPLY CURRENT (mA)
MAX9176 toc07
DIFFERENTIAL OUTPUT VOLTAGE
vs. FREQUENCY
700
600
500
400
300
200
100
0
0 800
FREQUENCY (MHz)
SUPPLY CURRENT
vs. FREQUENCY
50
40
30
20
10
0 800
FREQUENCY (MHz)
OUTPUT RISE/FALL TIME
vs. SUPPLY VOLTAGE
395
375
355
335
315
OUTPUT RISE/FALL TIME (ps)
295
275
3.0 3.2 3.33.1 3.4 3.5 3.6
t
R
SUPPLY VOLTAGE (V)
700600500400300200100
700600500400300200100
fIN = 155MHz
t
F
OUTPUT RISE/FALL TIME
vs. TEMPERATURE
450
MAX9176 toc02
400
t
R
350
300
RISE/FALL TIME (ps)
t
F
250
fIN = 155MHz
200
-40 85
TEMPERATURE (°C)
SUPPLY CURRENT
vs. DATA RATE
50
MAX9176 toc05
40
30
SUPPLY CURRENT (mA)
20
PRBS 2
10
0 800
FREQUENCY (Mbps)
DIFFERENTIAL PROPAGATION DELAY
vs. SUPPLY VOLTAGE
3.0
2.8
MAX9176 toc08
2.5
2.3
2.0
1.8
DIFFERENTIAL PROPAGATION DELAY (ns)
1.5
3.0 3.2 3.33.1 3.4 3.5 3.6
SUPPLY VOLTAGE (V)
t
PLH
t
PHL
f
= 155MHz
IN
MAX9176 toc03
603510-15
MAX9176 toc06
23
- 1
700600500400300200100
MAX9176 toc09
MAX9176/MAX9177
670MHz LVDS-to-LVDS and
Anything-to-LVDS 2:1 Multiplexers
8 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
((MAX9176) VCC= 3.3V, |VID| = 0.2V, VCM= 1.25V, RL= 100Ω, CL= 5pf, PD = V
CC,
SEL = 0V, IN1+, IN1- = open, TA= +25°C,
unless otherwise noted.)
Pin Description
100
200
400
300
500
600
50 9070 110 130 150
DC DIFFERENTIAL OUTPUT VOLTAGE
vs. LOAD RESISTOR
MAX9176 toc10
LOAD RESISTOR (Ω)
DC DIFFERENTIAL OUTPUT VOLTAGE (mV)
PIN
µMAX QFN
NAME FUNCTION
1 1 IN0+ Noninverting Differential Input 0
2 2 IN0- Inverting Differential Input 0
3 3 GND Ground
4 4 IN1+ Noninverting Differential Input 1
5 5 IN1- Inverting Differential Input 1
6 6 SEL
LVTTL/LVCMOS Input Select. SEL = high selects differential input 1. SEL = low selects
differential input 0. Internal pulldown resistor to GND.
77 PD
LVTTL/LVCMOS Input. Device is powered down when PD is low. Internal pulldown resistor
to GND.
88 VCCPower Supply
9 9 OUT- Inverting Differential Output
10 10 OUT+ Noninverting Differential Output
— EP Exposed Pad Exposed Pad. Solder to ground.
2.13
2.25
2.50
2.38
2.75
2.88
2.63
3.00
0.1 0.9 1.30.5 1.7 2.0 2.4 2.8 3.2
DIFFERENTIAL PROPAGATION DELAY
vs. COMMON-MODE VOLTAGE
MAX9176 toc11
COMMON-MODE VOLTAGE (V)
DIFFERENTIAL PROPAGATION DELAY (ns)
t
PLH
, t
PHL
(MAX9177)
t
PHL
(MAX9176)
t
PLH
(MAX9176)
fIN = 155MHz
MAX9176/MAX9177
670MHz LVDS-to-LVDS and
Anything-to-LVDS 2:1 Multiplexers
_______________________________________________________________________________________ 9
Detailed Description
The MAX9176/MAX9177 are 670MHz, low-jitter, lowskew 2:1 multiplexers ideal for protection switching,
loopback, and clock distribution. The devices feature
ultra-low 68ps(
P-P
) deterministic jitter that ensures reliable operation in high-speed links that are highly sensitive to timing error.
The MAX9176 has fail-safe LVDS inputs and an LVDS
output. The MAX9177 has anything differential inputs
(CML/LVDS/LVPECL) and an LVDS output. The output
can be put into high impedance using the power-down
input. The MAX9176 features fail-safe circuits that drive
the output high when a selected input is open, undriven and shorted, or undriven and terminated. The
MAX9177 has bias circuits that force the output high
when a selected input is open. The mux select and
power-down inputs are compatible with standard
LVTTL/LVCMOS logic.
The select and power-down inputs tolerate undershoot
of -1V and overshoot of V
CC
+ 1V. The MAX9176/
MAX9177 are available in 10-pin µMAX and 10-lead
thin QFN packages, and operate from a single 3.3V
supply over the -40°C to +85°C temperature range.
Current-Mode LVDS Output
The LVDS output uses a current-steering configuration.
This approach results in less ground bounce and less
output ringing, enhancing noise margin and system
speed performance.
A differential output voltage is produced by steering
current through the parallel combination of the integrated differential output resistor and transmission line
impedance/termination resistor. When driving a 100Ω
load, a differential voltage of 250mV to 475mV is produced. For loads greater than 100Ω, the output voltage
is larger, and for loads less than 100Ω, the output volt-
age is smaller. See the Differential Output Voltage vs.
Load Resistance curve in Typical Operating
Characteristics for more information. The output is
short-circuit current limited for single-ended and differential shorts.
MAX9176 Input Fail-Safe
The fail-safe feature of the MAX9176 sets the output
high when the differential input is:
• Open
• Undriven and shorted
• Undriven and terminated
Without a fail-safe circuit, when the selected input is
undriven, noise at the input may switch the output and
it may appear to the system that data is being sent.
Open or undriven terminated input conditions can
occur when a cable is disconnected or cut, or when
the driver output is in high impedance. A shorted input
can occur because of a cable failure.
When the selected input is driven with a differential signal of VID= 50mV to 1.2V within a voltage range of 0
to 2.4V, the fail-safe circuit is not activated. If the selected input is open, undriven and shorted, or undriven and
terminated, an internal resistor in the fail-safe circuit
pulls both inputs above VCC- 0.3V, activating the failsafe circuit and forcing the output high (Figure 1).
Overshoot and Undershoot Voltage
Protection
The MAX9176/MAX9177 are designed to protect the
select and power-down inputs (SEL and PD) against
latchup due to transient overshoot and undershoot voltage. If the input voltage goes above V
CC
or below
GND by up to 1V, an internal circuit limits input current
to 1.5mA.
Table 1. Function Table
Table 2. Input Select and Power-Down
Function Table
MAX9177 Open
MAX9176
INPUTS OUTPUT
(IN_+) - (IN_-) (OUT+) - (OUT-)
≥ +50mV H
≤ -50mV L
-50mV < VID < +50mV Indeterminate
Open, undriven
short, or undriven
parallel termination
H
SEL PD OUT+, OUT-
HH
L or open H IN0+, IN0-
High impedance to ground
X L or open
and 123Ω (typ) differential
output resistance
IN1+, IN1-
MAX9176/MAX9177
670MHz LVDS-to-LVDS and
Anything-to-LVDS 2:1 Multiplexers
10 ______________________________________________________________________________________
Figure 9. Human Body Test Model
Figure 10. IEC 61000_4-2 Contact Discharge Test Model
Applications Information
Power-Supply Bypassing
Bypass the VCCpin with high-frequency surface-mount
ceramic 0.1µF and 0.001µF capacitors in parallel as
close to the device as possible, with the smaller valued
capacitor closest to VCC.
Differential Traces
Input and output trace characteristics affect the performance of the MAX9176/MAX9177. Use controlledimpedance differential traces (100Ω typical). To reduce
radiated noise and ensure that noise couples as common mode, route the differential input and output signals within a pair close together. Reduce skew by
matching the electrical length of the two signal paths
that make up the differential pair. Excessive skew can
result in a degradation of magnetic field cancellation.
Maintain a constant distance between the differential
traces to avoid discontinuities in differential impedance.
Minimize the number of vias to further prevent impedance discontinuities.
Cables and Connectors
Interconnect for LVDS typically has a controlled differential impedance of 100Ω. Use cables and connectors
that have matched differential impedance to minimize
impedance discontinuities.
Avoid the use of unbalanced cables such as ribbon or
simple coaxial cable. Balanced cables such as twisted
pair offer superior signal quality and tend to generate
less EMI due to magnetic field canceling effects.
Balanced cables pick up noise as common mode,
which is rejected by the LVDS receiver.
Termination
The MAX9176/MAX9177 require external input and output termination resistors. For LVDS, connect an input
termination resistor across each differential input and at
the far end of the interconnect driven by the LVDS output. Place the input termination resistor as close to the
receiver input as possible. Termination resistors should
match the differential impedance of the transmission
line. Use 1% surface-mount resistors.
The MAX9176/MAX9177 feature an integrated differential output resistor. This resistor reduces jitter by damping reflections produced by any mismatch between the
transmission line and termination resistor at the far end
of the interconnect.
Board Layout
Separate the differential and single-ended signals to
reduce crosstalk. A four-layer printed circuit board with
separate layers for power, ground, differential signals,
and single-ended logic signals is recommended.
Separate the differential signals from the logic signals
with power and ground planes for best results.
IEC 61000-4-2 Level 4 ESD Protection
The IEC 61000-4-2 standard (Figure 10) specifies ESD
tolerance for electronic systems. The IEC61000-4-2
model specifies a 150pF capacitor that is discharged
into the device through a 330Ω resistor. The MAX9176/
MAX9177 differential inputs and outputs are rated for
IEC61000-4-2 level 4 (±8kV Contact Discharge and
±15kV Air-Gap Discharge). The Human Body Model
(HBM, Figure 9) specifies a 100pF capacitor that is discharged into the device through a 1.5kΩ resistor.
IEC 61000-4-2 level 4 discharges higher peak current
and more energy than the HBM due to the lower series
resistance and larger capacitor.
s
R
D
1.5kΩ
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
R
D
330Ω
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
R
C
1MΩ
CHARGE-CURRENT
LIMIT RESISTOR
HIGH-
VOLTAGE
DC
SOURCE
CHARGE-CURRENT
LIMIT RESISTOR
HIGH-
VOLTAGE
DC
SOURCE
C
100pF
R
C
50Ω TO 100Ω
C
150pF
s
MAX9176/MAX9177
670MHz LVDS-to-LVDS and
Anything-to-LVDS 2:1 Multiplexers
______________________________________________________________________________________ 11
Functional Diagram
Chip Information
TRANSISTOR COUNT: 744
PROCESS: CMOS
IN0+
IN0-
IN1+
IN1-
SEL
PD
OUT+
OUT-
MAX9176/MAX9177
670MHz LVDS-to-LVDS and
Anything-to-LVDS 2:1 Multiplexers
12 ______________________________________________________________________________________
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages
.)
e
10
ÿ 0.50±0.1
0.6±0.1
1
0.6±0.1
4X S
H
TOP VIEW
D2
A2
b
D1
A
A1
FRONT VIEW
GAGE PLANE
α
BOTTOM VIEW
SIDE VIEW
10
DIM
1
E2
E1
L
L1
PROPRIETARY INFORMATION
TITLE:
INCHES
MIN
-A
0.002
A1
A2 0.030 0.037 0.75 0.95
0.116
D1
0.114
D2
0.116
E1
0.114
E2
0.187
H
0.0157
L
L1
0.037 REF
0.007
b
e
0.0197 BSC
0.0035
c
0.0196 REF
S
α
0∞ 0∞ 6∞
c
MAX
0.043
0.006
0.120
0.118
0.120
0.118
0.199
0.0275
0.0106
0.0078
6∞
MILLIMETERS
MAX
MIN
1.10
-
0.15
0.05
3.05
2.95
3.00
2.89
3.05
2.95
2.89
3.00
4.75
5.05
0.40
0.70
0.940 REF
0.177
0.270
0.500 BSC
0.090
0.200
0.498 REF
10LUMAX.EPS
PACKAGE OUTLINE, 10L uMAX/uSOP
REV.DOCUMENT CONTROL NO.APPROVAL
21-0061
1
I
1
MAX9176/MAX9177
670MHz LVDS-to-LVDS and
Anything-to-LVDS 2:1 Multiplexers
______________________________________________________________________________________ 13
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages
.)
6, 8, &10L, QFN THIN.EPS
PACKAGE OUTLINE, 6, 8 & 10L,
QFN THIN (DUAL), EXPOSED PAD, 3x3x0.80 mm
21-0137
C
MAX9176/MAX9177
670MHz LVDS-to-LVDS and
Anything-to-LVDS 2:1 Multiplexers
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages
.)
COMMON DIMENSIONS
SYMBOL
A
D
E
A1
L
k
A2 0.20 REF.
MIN. MAX.
0.70 0.80
2.90 3.10
2.90 3.10
0.00 0.05
0.20 0.40
0.25 MIN
PACKAGE VARIATIONS
PKG. CODE
T633-1 1.50±0.10D22.30±0.10
N
6
1.50±0.10
E2
2.30±0.10T833-1 8
JEDEC SPEC
0.95 BSCeMO229 / WEEA
0.65 BSC
MO229 / WEEC
[(N/2)-1] x e
0.40±0.05b1.90 REF
1.95 REF0.30±0.05
0.25±0.05 2.00 REFMO229 / WEED-30.50 BSC1.50±0.10 2.30±0.1010T1033-1
PACKAGE OUTLINE, 6, 8 & 10L,
QFN THIN (DUAL), EXPOSED PAD, 3x3x0.80 mm
21-0137
C
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