For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
General Description
The MAX9173 quad low-voltage differential signaling
(LVDS) line receiver is ideal for applications requiring
high data rates, low power, and low noise. The
MAX9173 is guaranteed to receive data at speeds up
to 500Mbps (250MHz) over controlled-impedance
media of approximately 100Ω. The transmission media
can be printed circuit (PC) board traces or cables.
The MAX9173 accepts four LVDS differential inputs and
translates them to LVCMOS/LVTTL outputs. The
MAX9173 inputs are high impedance and require an
external termination resistor when used in a point-topoint connection.
The device supports a wide common-mode input range
of 0.05V to VCC- 0.05V, allowing for ground potential
differences and common-mode noise between the driver and the receiver. A fail-safe feature sets the output
high when the inputs are open, or when the inputs are
undriven and shorted or undriven and parallel terminated. The EN and EN inputs control the high-impedance
outputs. The enables are common to all four receivers.
Inputs conform to the ANSI TIA/EIA-644 LVDS standard. The flow-through pinout simplifies board layout
and reduces crosstalk by separating the LVDS inputs
and LVCMOS/LVTTL outputs. The MAX9173 operates
from a single 3.3V supply, and is specified for operation from -40°C to +85°C. Refer to the MAX9121/
MAX9122 data sheet for lower jitter quad LVDS
receivers with parallel fail-safe. Refer to the MAX9123
data sheet for a quad LVDS line driver with flowthrough pinout.
The device is available in 16-pin TSSOP, SO, and
space-saving thin QFN packages.
Applications
Digital Copiers
Laser Printers
Cellular Phone Base Stations
Network Switches/Routers
Backplane Interconnect
Clock Distribution
LCD Displays
Telecom Switching Equipment
Features
♦ Accepts LVDS and LVPECL Inputs
♦ Fully Compatible with DS90LV048A
♦ Low 1.0mA (max) Disable Supply Current
♦ In-Path Fail-Safe Circuitry
♦ Flow-Through Pinout
Simplifies PC Board Layout
Reduces Crosstalk
♦ Guaranteed 500Mbps Data Rate
♦ 400ps Pulse Skew (max)
♦ Conforms to ANSI TIA/EIA-644 LVDS Standard
♦ High-Impedance LVDS Inputs when Powered-Off
♦ Available in Tiny 3mm x 3mm QFN Package
Pin Configurations and Functional Diagram appear at end of
data sheet.
Ordering Information
*Future product. Contact factory for availability.
**EP = Exposed pad.
MAX9123
MAX9173
100Ω
100Ω
100Ω
100Ω
Rx
LVDS SIGNALS
100Ω SHIELDED TWISTED CABLE OR MICROSTRIP BOARD TRACES
LVTTL/LVCMOS
DATA INPUTS
LVTTL/LVCMOS
DATA OUTPUTS
Rx
Rx
Rx
Tx
Tx
Tx
Tx
Typical Operating Circuit
PARTTEMP RANGEPIN-PACKAGE
MAX9173EUE-40°C to +85°C16 TSSOP
MAX9173ESE-40°C to +85°C16 SO
MAX9173ETE*-40°C to +85°C16 Thin QFN-EP**
MAX9173
Quad LVDS Line Receiver with Flow-Through
Pinout and “In-Path” Fail-Safe
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCCto GND ..........................................................-0.3V to +4.0V
IN_+, IN_- to GND .................................................-0.3V to +4.0V
OUT_, EN, EN to GND................................-0.3V to (V
Note 1:Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except V
TH
, VTL, and VID.
Note 2:Devices are 100% production tested at T
A
= +25°C and are guaranteed by design for TA= -40°C to +85°C as specified.
Note 3:Short only one output at a time. Do not exceed the absolute maximum junction temperature specification.
Note 4:AC parameters are guaranteed by design and characterization.
Note 5:C
L
includes scope probe and test jig capacitance.
Note 6:Pulse generator output conditions: t
R
= tF< 1ns (0% to 100%), frequency = 250MHz, 50% duty cycle, VOH= 1.3V, VOL=
1.1V. High-impedance delay pulse generator output conditions: t
R
= tF < 3ns (0% to 100%), frequency = 1MHz, 50% duty
cycle, V
OH
= 3V and VOL= 0.
Note 7:Propagation delay and differential pulse skew decrease when |V
ID
| is increased from 200mV to 400mV. Skew specifications
apply for 200mV ≤|V
ID
|≤1.2V over the common-mode range VCM= |VID|/2 to VCC- |VID|/2.
Note 8:t
SKD1
is the magnitude of the difference of differential propagation delays in a channel. t
SKD1
= |t
PHLD
- t
PLHD
|.
Note 9:t
SKD2
is the magnitude of the difference of the t
PLHD
or t
PHLD
of one channel and the t
PLHD
or t
PHLD
of any other channel
on the same part.
Note 10: t
SKD3
is the magnitude of the difference of any differential propagation delays between parts operating over rated conditions
at the same V
CC
and within 5°C of each other.
Note 11: t
SKD4
is the magnitude of the difference of any differential propagation delays between parts operating over rated conditions.
Note 12: 60% to 40% duty cycle, V
OL
= 0.4V (max), VOH= 2.7V (min), load = 15pF.
AC ELECTRICAL CHARACTERISTICS
(VCC= 3.0V to 3.6V, CL= 15pF, |VID| = 0.2V, VCM= 1.2V, and TA= -40°C to +85°C. Typical values are at VCC= 3.3V and TA=
+25°C, unless otherwise noted.) (Notes 4–7)
Differential Propagation Delay
High to Low
Differential Propagation Delay
Low to High
Differential Pulse Skew
|t
PHLD - tPLHD
Differential Channel-to-Channel
Skew
Differential Part-to-Part Skew
Rise Timet
Fall Timet
Disable Time High to Zt
Disable Time Low to Zt
Enable Time Z to Hight
Enable Time Z to Lowt
Maximum Operating Frequencyf
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
t
PHLD
t
PLHD
t
|
SKD1
t
SKD2
t
SKD3
t
SKD4
TLH
THL
PHZ
PLZ
PZH
PZL
MAX
Figures 2 and 31.22.012.7ns
Figures 2 and 31.22.072.7ns
Figures 2 and 3 (Note 8)60400ps
Figures 2 and 3 (Note 9)100500ps
Figures 2 and 3 (Note 10)1
Figures 2 and 3 (Note 11)1.5
ns
Figures 2 and 30.661.0ns
Figures 2 and 30.621.0ns
RL = 2kΩ, Figures 4 and 59.514ns
RL = 2kΩ, Figures 4 and 59.514ns
RL = 2kΩ, Figures 4 and 5314ns
RL = 2kΩ, Figures 4 and 5314ns
All channels switching (Note 12)250MHz
MAX9173
Quad LVDS Line Receiver with Flow-Through
Pinout and “In-Path” Fail-Safe
(VCC= 3.3V, VCM= 1.2V, |VID| = 0.2V, f = 100MHz, input rise and fall time = 1ns (0% to 100%), CL= 15pF, and TA= +25°C, unless
otherwise noted.) (Figures 2 and 3)
(VCC= 3.3V, VCM= 1.2V, |VID| = 0.2V, f = 100MHz, input rise and fall time = 1ns (0% to 100%), CL= 15pF, and TA= +25°C, unless
otherwise noted.) (Figures 2 and 3)
DIFFERENTIAL PROPAGATION DELAY
vs. COMMON-MODE VOLTAGE
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
DIFFERENTIAL PROPAGATION DELAY (ns)
1.9
1.8
t
PHLD
0.13.1
COMMON-MODE VOLTAGE (V)
TRANSITION TIME vs. SUPPLY VOLTAGE
720
680
640
TRANSITION TIME (ps)
600
560
3.03.6
t
TLH
t
THL
SUPPLY VOLTAGE (V)
t
PLHD
DIFFERENTIAL PROPAGATION DELAY
vs. DIFFERENTIAL INPUT VOLTAGE
2.40
MAX9173 toc10
2.62.11.61.10.6
2.35
2.30
2.25
2.20
2.15
2.10
2.05
2.00
DIFFERENTIAL PROPAGATION DELAY (ns)
1.95
1.90
0.1
DIFFERENTIAL INPUT VOLTAGE (V)
t
PHLD
t
PLHD
MAX9173 toc11
1.10.90.30.50.7
TRANSITION TIME vs. TEMPERATURE
800
MAX9173 toc13
3.53.43.33.23.1
750
700
650
600
550
TRANSITION TIME (ps)
500
450
400
-4085
t
TLH
t
TEMPERATURE (°C)
THL
MAX9173 toc14
6035-1510
DIFFERENTIAL PROPAGATION DELAY
vs. LOAD
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
1.9
DIFFERENTIAL PROPAGATION DELAY (ns)
1.8
1.7
1050
t
PLHD
LOAD (pF)
t
PHLD
TRANSITION TIME vs. LOAD
2000
1800
1600
1400
1200
1000
TRANSITION TIME (ps)
800
600
400
1050
LOAD (pF)
t
THL
403020
t
TLH
403020
MAX9173 toc12
MAX9173 toc15
DIFFERENTIAL PULSE SKEW
vs. SUPPLY VOLTAGE
120
110
100
90
80
70
60
50
40
30
DIFFERENTIAL PULSE SKEW (ps)
20
10
0
3.03.6
SUPPLY VOLTAGE (V)
400
MAX9173 toc16
3.53.43.33.23.1
350
300
250
200
150
100
DIFFERENTIAL PULSE SKEW (ps)
DIFFERENTIAL PULSE SKEW
vs. INPUT TRANSITION TIME
f = 50MHz
50
0
1.03.0
INPUT TRANSITION TIME (ns)
2.52.01.5
MAX9173 toc17
MAX9173
Detailed Description
LVDS is a signaling method intended for point-to-point
communication over a controlled-impedance medium
as defined by the ANSI TIA/EIA-644 and IEEE 1596.3
standards. LVDS uses a lower voltage swing than other
common communication standards, achieving higher
data rates with reduced power consumption while
reducing EMI and system susceptibility to noise.
The MAX9173 is a 500Mbps, four-channel LVDS receiver intended for high-speed, point-to-point, low-power
applications. Each channel accepts an LVDS input and
translates it to an LVTTL/LVCMOS output. The receiver
is specified to detect differential signals as low as
100mV and as high as 1.2V within an input voltage
range of 0 to VCC. The 250mV to 400mV differential output of an LVDS driver is nominally centered around a
1.2V offset. This offset, coupled with the receiver’s 0 to
VCCinput voltage range, allows more than ±1V shift in
the signal (as seen by the receiver). This allows for a
difference in ground references of the transmitter and
the receiver, the common-mode effects of coupled
noise, or both.
Quad LVDS Line Receiver with Flow-Through
Pinout and “In-Path” Fail-Safe
115IN1-Inverting Differential Receiver Input for Receiver 1
216IN1+Noninverting Differential Receiver Input for Receiver 1
31IN2+Noninverting Differential Receiver Input for Receiver 2
42IN2-Inverting Differential Receiver Input for Receiver 2
53IN3-Inverting Differential Receiver Input for Receiver 3
64IN3+Noninverting Differential Receiver Input for Receiver 3
75IN4+Noninverting Differential Receiver Input for Receiver 4
86IN4-Inverting Differential Receiver Input for Receiver 4
9, 167, 14EN, EN
108OUT4LVCMOS/LVTTL Receiver Output for Receiver 4
119OUT3LVCMOS/LVTTL Receiver Output for Receiver 3
1210GNDGround
1311V
1412OUT2LVCMOS/LVTTL Receiver Output for Receiver 2
1513OUT1LVCMOS/LVTTL Receiver Output for Receiver 1
—Exposed PadEPExposed Pad. Solder to ground plane for proper heat dissipation.
NAMEFUNCTION
Receiver Enable Inputs. When EN = high and EN = low or open, the outputs are active.
For other combinations of EN and EN, the outputs are disabled and in high
impedance.
CC
Power-Supply Input. Bypass VCC to GND with 0.1µF and 0.001µF ceramic capacitors.
Place the smaller value cap as close to the pin as possible.
ENEN(IN_+) - (IN_-)OUT_
All other combinations of ENABLE pinsDon’t careZ
ENABLESINPUTSOUTPUT
VID ≥ 0H
HL or open
Open, undriven short, or undriven parallel terminationH
VID ≤ -100mVL
Fail-Safe
The MAX9173 fail-safe drives the receiver output high
when the differential input is:
•Open
•Undriven and shorted
•Undriven and terminated
Without fail-safe, differential noise at the input may
switch the receiver and appear as data to the receiving
system. An open input occurs when a cable and termination are disconnected. An undriven, terminated input
occurs when a cable is disconnected with the termination still connected across the receiver inputs or when
the driver of a receiver is in high impedance. An undriven, shorted input can occur due to a shorted cable.
“In-Path” vs. “Parallel” Fail-Safe
The MAX9173 has in-path fail-safe that is compatible
with in-path fail-safe receivers, such as the
DS90LV048A. Refer to the MAX9121/MAX9122 data
sheet for pin-compatible receivers with parallel fail-safe
and lower jitter. Refer to the MAX9130 data sheet for a
single LVDS receiver with parallel fail-safe in an SC70
package.
The MAX9173 with in-path fail-safe is designed with a
+45mV input offset voltage, a 2.5µA current source
between VCCand the noninverting input, and a 5µA
current sink between the inverting input and ground
(Figure 1). If the differential input is open, the 2.5µA
current source pulls the input to approximately VCC-
0.8V and the 5µA current sink pulls the inverting input
to ground, which drives the receiver output high. If the
differential input is shorted or terminated with a typical
value termination resistor, the +45mV offset drives the
receiver output high. If the input is terminated and floating, the receiver output is driven high by the +45mV offset, and the 2:1 current sink to current source ratio
(5µA:2.5µA) pulls the inputs to ground. This can be an
advantage when switching between drivers on a multipoint bus because the change in common-mode voltage from ground to the typical driver offset voltage of
1.2V is not as much as the change from VCCto 1.2V
(parallel fail-safe pulls the bus to VCC).
ESD Protection
ESD-protection structures are incorporated on all pins
to protect against electrostatic discharges encountered
during handling and assembly. The receiver inputs of
the MAX9173 have ±7.0kV of protection against static
electricity (per Human Body Model).
Figure 6a shows the Human Body Model, and Figure
6b shows the current waveform it generates when discharged into a low-impedance load. This model con-
sists of a 100pF capacitor charged to the ESD test voltage, which is then discharged into the test device
through a 1.5kΩ resistor.
Applications Information
Differential Traces
Input trace characteristics affect the performance of the
MAX9173. Use controlled-impedance board traces. For
point-to-point connections, match the receiver input termination resistor to the differential characteristic impedance of the board traces.
Eliminate reflections and ensure that noise couples as
common mode by running the differential traces close
together. Reduce skew by matching the electrical
length of the traces. Excessive skew can result in a
degradation of magnetic field cancellation.
Each channel’s differential signals should be routed
close to each other to cancel their external magnetic
field. Maintain a constant distance between the differential traces to avoid discontinuities in differential
impedance. Minimize the number of vias to further prevent impedance discontinuities.
Cables and Connectors
LVDS transmission media typically have controlled differential impedance of 100Ω. Use cables and connectors that have matched differential impedance to
minimize impedance discontinuities.
Avoid the use of unbalanced cables such as coaxial
cable. Balanced cables such as twisted pair offer
superior signal quality and tend to generate less EMI
due to magnetic field canceling effects. Balanced
cables pick up noise as common mode, which is rejected by the LVDS receiver.
The MAX9173 requires an external termination resistor.
The termination resistor should match the differential
impedance of the transmission line. Termination resistance values may range between 90Ω to 132Ω,
depending on the characteristic impedance of the
transmission medium.
When using the MAX9173, minimize the distance between the input termination resistors and the MAX9173
receiver inputs. Use 1% surface-mount resistors.
Board Layout
In general, separate the LVDS inputs from single-ended
outputs to reduce crosstalk. Take special care when
routing traces with the QFN package. Ideally, the LVDS
inputs should be separated by 180° from the
LVTTL/LVCMOS outputs to reduce crosstalk.
For LVDS applications, a four-layer PC board that provides separate layers of power, ground, LVDS inputs, and
output signals is recommended. When using the QFN
package, solder the exposed pad (EP) to the ground
plane using an array of vias for proper heat dissipation.
Chip Information
TRANSISTOR COUNT: 1462
PROCESS: CMOS
Quad LVDS Line Receiver with Flow-Through
Pinout and “In-Path” Fail-Safe
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
TSSOP4.40mm.EPS
MAX9173
Quad LVDS Line Receiver with Flow-Through
Pinout and “In-Path” Fail-Safe
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
EXPOSED PAD VARIATIONS
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO
JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED
WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.20 mm AND 0.25 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220 REVISION C.
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
12 & 16L, QFN THIN, 3x3x0.8 mm
APPROVAL
DOCUMENT CONTROL NO.
21-0136
REV.
2
C
2
MAX9173
Quad LVDS Line Receiver with Flow-Through
Pinout and “In-Path” Fail-Safe
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
N
1
e
FRONT VIEW
TOP VIEW
D
INCHES
DIM
MIN
0.053A
0.004
A1
0.014
B
0.007
C
e0.050 BSC1.27 BSC
0.150
HE
A
B
A1
C
L
E
H0.2440.2285.806.20
0.016L
VARIATIONS:
INCHES
MINDIM
D
0.1890.197AA5.004.808
0.3370.344AB8.758.5514
D
0-8
MAX
0.069
0.010
0.019
0.010
0.157
0.050
MAX
0.3940.386D
MILLIMETERS
MAX
MIN
1.35
1.75
0.10
0.25
0.35
0.49
0.19
0.25
3.804.00
0.401.27
MILLIMETERS
MAX
MIN
9.8010.00
N MS012
16
AC
SOICN .EPS
SIDE VIEW
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, .150" SOIC
REV.DOCUMENT CONTROL NO.APPROVAL
21-0041
1
B
1
Loading...
+ hidden pages
You need points to download manuals.
1 point = 1 manual.
You can buy points or you can get point for every manual you upload.