MAXIM MAX9160 User Manual

General Description

The MAX9160 125MHz, 14-port LVTTL/LVCMOS clock
driver repeats the selected LVDS or LVTTL/LVCMOS
input on two output banks. Each bank consists of seven
LVTTL/LVCMOS series terminated outputs and a bank
enable. The LVDS input has a fail-safe function. The
MAX9160 has a propagation delay that can be adjusted
using an external resistor to set the bias current for an
internal delay cell. The LVTTL/LVCMOS outputs feature
200ps maximum output-to-output skew and ±100ps maxi­mum added peak-to-peak jitter.

The MAX9160 is designed to operate with a 3.3V sup­ply voltage over the extended temperature range of

-40°C to +85°C. This device is available in 28-pin
exposed- and nonexposed-pad TSSOP and 32-lead
5mm x 5mm QFN packages.

Applications

Features

♦ LVDS or LVTTL/LVCMOS Input Selection

♦ LVDS Input Fail-Safe Sets Outputs High for Open,

Undriven Short, or Undriven Parallel Termination

♦ Two Output Banks with Separate Bank Enables

♦ Integrated Output Series Termination for 60Ω

Lines

♦ 200ps (max) Output-to-Output Skew

♦ ±100ps (max) Peak-to-Peak Added Output Jitter

♦ 42% to 58% Output Duty Cycle at 125MHz

♦ Guaranteed 125MHz Operating Frequency

♦ LVDS Input Is High Impedance with V

CC

= 0V

or Open (Hot Swappable)

♦ 28-Pin Exposed- and Nonexposed-Pad TSSOP

or 32-Lead QFN Packages

♦ -40°C to +85°C Operating Temperature

♦ 3.0V to 3.6V Supply Voltage

MAX9160

LVDS or LVTTL/LVCMOS Input to

14 LVTTL/LVCMOS Output Clock Driver

________________________________________________________________ Maxim Integrated Products 1

Pin Configurations

Ordering Information

Function Table

19-2392; Rev 0; 4/02

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Typical Application Circuit and Functional Diagram appear
at end of data sheet.

VID= V

IN+

- V

IN-

H = high logic level

L = low logic level
X = don’t care

Cellular Base Stations

Servers

Add/Drop Multiplexers

Digital Cross-Connects

DSLAMs

Networking Equipment

*Future product—contact factory for availability.
**Exposed pad.

Pin Configurations continued at end of data sheet.

TOP VIEW

1

OUTA5

2

OUTA6

3

ENA

4

SEL

5

SE_IN

V

CC

GND

IN+

IN-

GND

RSET

ENB

OUTB0

OUTB1

MAX9160

6

7

8

9

10

11

12

13

14

TSSOP

28

OUTA4

27

OUTA3

26

GND

25

OUTA2

24

OUTA1

23

V

CC

22

OUTA0

21

OUTB6

20

GND

19

OUTB5

18

OUTB4

17

V

CC

16

OUTB3

15

OUTB2

PART TEMP RANGE PIN-PACKAGE

MAX9160EUI -40°C to +85°C 28 TSSOP

MAX9160AEUI -40°C to +85°C 28 TSSOP-EP**

MAX9160EGJ* -40°C to +85°C 32 QFN-EP

EN_ SEL SE_IN V

HHH X H

HH

L or

H

open

L or

H

open

L or

H

open

L or

Open

XXXL

ID

L or

open

X ≥ +50mV H

X ≤ -50mV L

X

Op en, und r i ven shor t, or

und r i ven p ar al l el ter m i nati on

XL

OUT_

H

MAX9160

LVDS or LVTTL/LVCMOS Input to
14 LVTTL/LVCMOS Output Clock Driver

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

DC ELECTRICAL CHARACTERISTICS

(VCC= 3.0V to 3.6V, ENA = ENB = high, RSET = 12kΩ±1%, differential input voltage IVIDI = 0.05V to 1.2V, input common-mode volt­age V

CM

= IVID/2 I to 2.4V - IVID/2 I, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC= 3.3V, IVIDI = 0.2V,

V

CM

= 1.2V, TA = +25°C.) (Notes 2, 3)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

V

CC

to GND ..............................................................-0.3V to +4V

IN+, IN- to GND........................................................-0.3V to +4V

SE_IN, EN_, SEL, RSET, OUT_ to GND ........-0.3V to V

CC

+ 0.3V

Output Short-Circuit Duration (OUT_) (Note 1) ..........Continuous

Continuous Power Dissipation (T

A

= +70°C)

28-Pin TSSOP (derate 12.8mW/°C above +70°C) .....1024mW

28-Pin TSSOP-EP (derate 23.8mW/°C above +70°C) ..1904mW

32-Pin QFN (derate 21.2mW/°C above +70°C) .........1704mW

Storage Temperature Range .............................-65°C to +150°C

Junction Temperature......................................................+150°C

Operating Temperature Range ...........................-40°C to +85°C

ESD Protection

Human Body Model (IN+, IN-) .......................................±16kV

Human Body Model (SE_IN) ............................................±8kV

Soldering Temperature (10s) ...........................................+300°C

Note 1: Short one output at a time. Do not exceed the absolute maximum junction temperature.

SINGLE-ENDED INPUTS (SE_IN, ENA, ENB, SEL)

Input High Voltage V

Input Low Voltage V

Input Clamp Voltage V

Input Current I

SE_IN Capacitance (Note 4) C

LVDS INPUT (IN+, IN-)

Differential Input High Threshold V

Differential Input Low Threshold V

Input Current I

Power-Off Input Current

Input Resistor 1 R

Input Resistor 2 R

Input Capacitance (Note 4) C

OUTPUTS (OUT_)

Output Short-Circuit Current
(Note 1)

Output Capacitance (Note 4) C

Output High Voltage V

Fail-Safe Output High Voltage V

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

IH

IL

ICL = -18mA -1.5 -0.85 V

CL

VIN = high or low -20 +20 µA

IN

SE_IN to GND 6.1 pF

IN

TH

TL

0.05V ≤ IVIDI ≤ 0.6V -15 +15

, I

IN+

IN-

0.6V < IVIDI ≤ 1.2V -20 +20

I

IN+(off)

I

IN-(off)

IN1

IN2

I

OS

OH

OHFS

0.05V ≤ IVIDI ≤ 0.6V, VCC = 0V or open -15 +15

0.6V < IVIDI ≤ 1.2V, VCC = 0V or open -20 +20

VCC = 3.6V or 0V, Figure 1 51 100 kΩ

VCC = 3.6V or 0 V, Figure 1 200 341 kΩ

IN+ or IN- to GND 6.0 pF

IN

SEL = high, SE_IN = high, V

SEL = low, VID = 100mV, V

OUT_ to GND 9 pF

O

IOH = -100µA

IOH = -4mA 2.4

IOH = -8mA 2.1

SEL = low, inputs
open, undriven short,
or undriven parallel
terminated

2.0 V

GND 0.8 V

-50 mV

= 0V

OUT

= 0V

OUT

IOH = -100µA

IOH = -4mA 2.4

I

= -8mA 2.1

OH

-115 -30 mA

V

CC

0.2

V

CC

0.2

-

-

CC

50 mV

V

µA

µA

V

V

MAX9160

LVDS or LVTTL/LVCMOS Input to

14 LVTTL/LVCMOS Output Clock Driver

_______________________________________________________________________________________ 3

DC ELECTRICAL CHARACTERISTICS (continued)

(VCC= 3.0V to 3.6V, ENA = ENB = high, RSET = 12kΩ±1%, differential input voltage IVIDI = 0.05V to 1.2V, input common-mode volt­age V

CM

= IVID/2 I to 2.4V - IVID/2 I, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC= 3.3V, IVIDI = 0.2V,

V

CM

= 1.2V, TA = +25°C.) (Notes 2, 3)

AC ELECTRICAL CHARACTERISTICS

(VCC= 3.0V to 3.6V, CL= 20pF, ENA = ENB = high, SEL = high or low, RSET = 12kΩ±1%, differential input voltage IVIDI = 0.15V to

1.2V, input common-mode voltage V

CM

= IVID/2I to 2.4V - IVID/2 I, TA= -40°C to +85°C, unless otherwise noted. Typical values are at

V

CC

= 3.3V, IVIDI = 0.2V, VCM= 1.2V, TA = +25°C.) (Notes 6, 7, 8)

Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground

except V

TH

, VTL, and VID.

Note 3: Parameter limits over temperature are guaranteed by design and characterization. Devices are production tested at

T

A

= +25°C.

Supply Current I

Output Series Resistance
(Note 5)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

IOL = 100µA 0.2

OL

CC

R

IOL = 4mA 0.4Output Low Voltage V

IOL = 8mA 0.8

SEL = high, SE_IN = high or low, no load 15 µA

SEL = low, V

Output switched high, V

S

Output switched low, V

= -100mV or 100mV, no load 7.0 10 mA

ID

= 1.65V 72

OUT

= 1.65V 61

OUT

V

Ω

Rise Time t

Fall Time t

Low-to-High Propagation Delay
IN+, IN- to OUT_

High-to-Low Propagation Delay
IN+, IN- to OUT_

Low-to-High Propagation Delay
SE_IN to OUT_

High-to-Low Propagation Delay
SE_IN to OUT_

Added Peak-to-Peak Output Jitter t

Output Duty Cycle ODC

Outp ut- to- Outp ut S kew ( N ote 9) t

Part-to-Part Skew (Note 10) t

Part-to-Part Skew (Note 11) t

Maximum Switching Frequency
(Note 12)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

R

F

t

PLH1

t

PHL1

t

PLH2

t

PHL2

J

SKOO

SKPP1

SKPP2

f

MAX

Figures 2 and 3

SEL = low

SEL = low

SEL = high 2.2 2.9 3.8 ns

SEL = high 2.2 3.1 3.8 ns

100mV peak-to-peak supply noise at
200kHz, 3.3V supply

f

= 125MHz 42 58

IN

f

= 35MHz 48.75 51.25

IN

SE_IN to OUT_, SEL = high 0.9

IN+, IN- to OUT_, SEL = low 2.2

SE_IN to OUT_, SEL = high 1.6

IN+, IN- to OUT_, SEL = low 2.7

RSET = 12kΩ 5.3 6.5 8.0

RSET = open 4.9 9.0

RSET = 12kΩ 5.3 6.4 8.0

RSET = open 4.9 9.0

1.4 2.95 ns

1.4 2.95 ns

100 ps

200 ps

125 MHz

ns

ns

%

ns

ns

Typical Operating Characteristics

(MAX9160 with RSET = 12kΩ±1%, VCC= 3.3V, CL= 20pF, ENA = ENB = high, IVIDI = 0.2, V

CM

= 1.2V, f

IN

= 125MHz, TA= +25°C,

unless otherwise noted.)

MAX9160

LVDS or LVTTL/LVCMOS Input to
14 LVTTL/LVCMOS Output Clock Driver

4 _______________________________________________________________________________________

AC ELECTRICAL CHARACTERISTICS (continued)

(VCC= 3.0V to 3.6V, CL= 20pF, ENA = ENB = high, SEL = high or low, RSET = 12kΩ±1%, differential input voltage IVIDI = 0.15V to

1.2V, input common-mode voltage V

CM

= IVID/2I to 2.4V - IVID/2 I, TA= -40°C to +85°C, unless otherwise noted. Typical values are at

V

CC

= 3.3V, IVIDI = 0.2V, VCM= 1.2V, TA = +25°C.) (Notes 6, 7, 8)

Note 4: Guaranteed by design and characterization.
Note 5: Total of driver output resistance and integrated series resistor.
Note 6: AC parameters are guaranteed by design and characterization and are not production tested. Limits are set at ±6 sigma.
Note 7: C

L

includes scope probe and test jig capacitance.

Note 8: Pulse generator conditions for SE_IN input: frequency = 125MHz, 50% duty cycle, Z

O

= 50Ω, tR= 1.2ns, and tF= 1.2ns (20%

to 80%), V

OH

= V

CC, VOL

= 0V. Pulse generator conditions for IN+, IN- input: frequency = 125MHz, 50% duty cycle, ZO=

50Ω, t

R

= 1ns, and tF= 1ns (20% to 80%). VID, VCMas specified in AC Electrical Characteristics general

conditions.

Note 9: Measured between outputs with identical loads at V

CC

/2 for a same-edge transition.

Note 10: t

SKPP1

is the greatest difference in propagation delay between different parts operating under identical conditions within

rated conditions.

Note 11: t

SKPP2

is the greatest difference in propagation delay between different parts operating within rated conditions.

Note 12: All AC specifications met at f

MAX

.

DIFFERENTIAL PROPAGATION DELAY

vs. SUPPLY VOLTAGE

MAX9160 toc03

SUPPLY VOLTAGE (V)

DIFFERENTIAL PROPAGATION DELAY (ns)

3.53.43.33.23.1

5.7

6.2

6.7

7.2

7.7

8.2

5.2

3.0 3.6

t

PLH

t

PHL

SINGLE-ENDED PROPAGATION DELAY

vs. TEMPERATURE

MAX9160 toc02

TEMPERATURE (°C)

SINGLE-ENDED PROPAGATION DELAY (ns)

80706050403020100-10-20-30

2.5

3.0

3.5

4.0

2.0

-40 90

t

PHL

t

PLH

DIFFERENTIAL PROPAGATION DELAY

vs. TEMPERATURE

MAX9160 toc01

TEMPERATURE (°C)

DIFFERENTIAL PROPAGATION DEALY (ns)

80706050403020100-10-20-30

4.7

5.2

5.7

6.2

6.7

7.2

4.2

-40 90

t

PLH

t

PHL