General Description
The MAX9152 2 x 2 crosspoint switch is designed for
applications requiring high speed, low power, and lownoise signal distribution. This device includes two
LVDS/LVPECL inputs, two LVDS outputs, and two logic
inputs that set the internal connections between differential inputs and outputs.
The MAX9152 can be programmed to connect any
input to either or both outputs, allowing it to be used in
the following configurations: 2 ✕2 crosspoint switch, 2:1
mux, 1:2 demux, 1:2 splitter, or dual repeater. This flexibility makes the MAX9152 ideal for protection switching
in fault-tolerant systems, loopback switching for diagnostics, fanout buffering for clock/data distribution, and
signal regeneration for communication over extended
distances.
Ultra-low 120ps
PK-PK
(max) PRBS jitter ensures reliable
communications in high-speed links that are highly sensitive to timing error, especially those incorporating
clock-and-data recovery, or serializers and deserializers. The high-speed switching performance guarantees
an 800Mbps data rate and less than 50ps (max) skew
between channels.
LVDS inputs and outputs are compatible with the
TIA/EIA-644 LVDS standard. The LVDS inputs are
designed to also accept LVPECL signals directly, and
PECL signals with an attenuation network. The LVDS
outputs are designed to drive 75Ω or 100Ω loads, and
feature a selectable differential output resistance to
minimize reflections.
The MAX9152 is available in 16-pin TSSOP and SO
packages, and consumes only 109mW while operating
from a single +3.3V supply over the -40°C to +85°C
temperature range.
Applications
Cell Phone Base Stations
Add/Drop Muxes
Digital Crossconnects
DSLAMs
Network Switches/Routers
Protection Switching
Loopback Diagnostics
Clock/Data Distribution
Cable Repeaters
Features
♦ Pin-Programmable Configuration
2 x 2 Crosspoint Switch
2:1 Mux
1:2 Demux
1:2 Splitter
Dual Repeater
♦ Ultra-Low 120ps
PK-PK
(max) Jitter with 800Mbps,
PRBS = 2
23
-1 Data Pattern
♦ Low 50ps (max) Channel-to-Channel Skew
♦ 109mW Power Dissipation
♦ Compatible with ANSI TIA/EIA-644 LVDS Standard
♦ Inputs Accept LVDS/LVPECL Signals
♦ LVDS Output Rated for 75Ω and 100Ω Loads
♦ Pin-Programmable Differential Output Resistance
♦ Pin-Compatible Upgrade to DS90CP22
(SO Package)
♦ Available in 16-Pin TSSOP Package
(Half the Size of SO)
MAX9152
800Mbps LVDS/LVPECL-to-LVDS 2 x 2
Crosspoint Switch
________________________________________________________________ Maxim Integrated Products 1
19-2003; Rev 0; 4/01
EN0
SEL0
IN0+
IN0-
IN1+
IN1-
MAX9152
01 01
EN1
SEL1
OUT1-OUT1+OUT0-OUT0+
Ordering Information
Pin Configuration appears at end of data sheet.
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
PART TEMP. RANGE PIN-PACKAGE
MAX9152ESE -40°C to +85°C 16 SO
MAX9152EUE -40°C to +85°C 16 TSSOP
MAX9152
800Mbps LVDS/LVPECL-to-LVDS 2 x 2
Crosspoint Switch
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(VCC= +3.0V to +3.6V, NC/RSEL = open for RL= 75Ω ±1%, NC/RSEL = high for RL= 100Ω ±1%, differential input voltage |VID| =
0.1V to V
CC
, input voltage (V
IN+
, V
IN-
) = 0 to VCC, EN_ = high, SEL0 = low, SEL1 = high, and TA= -40°C to +85°C. Typical values at
V
CC
= +3.3V, |VID| = 0.2V, input common-mode voltage VCM= 1.2V, TA= +25°C, unless otherwise noted.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCCto GND...........................................................-0.3V to +4.0V
IN_+, IN_-, OUT_+, OUT_- to GND .......................-0.3V to +4.0V
EN_, SEL_, NC/RSEL to GND.....................-0.3V to (VCC+ 0.3V)
Short-Circuit Duration (OUT_+, OUT_-) .....................Continuous
Continuous Power Dissipation (T
A
= +70°C)
16-Pin SO (derate 8.7mW/°C above +70°C)................696mW
16-Pin TSSOP (derate 9.4mW/°C above +70°C) .........755mW
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature......................................................+150°C
Operating Temperature Range ...........................-40°C to +85°C
Lead Temperature (soldering, 10s) .................................+300°C
ESD Protection
Human Body Model, IN_+, IN_-, OUT_+, OUT_-........... ±7kV
LVCMOS/LVTTL INPUTS (EN_, SEL_)
Input High Voltage V
Input Low Voltage V
Input High Current I
Input Low Current I
NC/RSEL INPUT
Input High Voltage V
Input Low Voltage V
Input High Current I
Input Low Current I
DIFFERENTIAL INPUTS (IN_+, IN_-)
Differential Input High Threshold V
Differential Input Low Threshold V
Input Current I
LVDS OUTPUTS (OUT_+, OUT_-)
Differential Output Impedance
(Note 2)
Differential Output Voltage V
Change in Magnitude of V
Between Complementary Output
States
Offset Common-Mode Voltage V
Change in Magnitude of V
Between Complementary Output
States
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
OD
OS
IH
IL
VIN = VCC or 2.0V 0 20 µA
VIN = 0 or 0.8V -10 10 µA
VIN = VCC or 2.0V 0 20 µA
VIN = 0 or 0.8V -10 10 µA
V
= VCC or 0, V
IN+
I
IN-
V
= 3. 6 V o r 0 , V
I N +
= 0
V
C C
NC/RSEL = low or open 60 90 118
NC/RSEL = high 85 122 155
RL = 75Ω, NC/RSEL = open, Figure 1
RL = 100Ω, NC/RSEL = high, Figure 1
IN+
R
IH
IL
IH
IL
IH
IL
TH
TL
DIFF
OD
RL = 75Ω, NC/RSEL = open, Figure 1
∆V
OD
RL = 100Ω, NC/RSEL = high, Figure 1
OS
RL = 75Ω, NC/RSEL = open, Figure 1
RL = 100Ω, NC/RSEL = high, Figure 1
RL = 75Ω, NC/RSEL = open, Figure 1
∆V
OS
RL = 100Ω, NC/RSEL = high, Figure 1
2.0 V
CC
GND 0.8 V
2.0 V
CC
GND 0.8 V
100 mV
-100 mV
= V
IN-
I N -
or 0 -1 1
CC
= 3 . 6 V or 0 ,
-1 1
280 382 470 mV
25 mV
1.150 1.430 V
25 mV
V
V
µA
Ω
MAX9152
800Mbps LVDS/LVPECL-to-LVDS 2 x 2
Crosspoint Switch
_______________________________________________________________________________________ 3
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC= +3.0V to +3.6V, NC/RSEL = open for RL= 75Ω ±1%, NC/RSEL = high for RL= 100Ω ±1%, differential input voltage |VID| =
0.1V to V
CC
, input voltage (V
IN+
, V
IN-
) = 0 to VCC, EN_ = high, SEL0 = low, SEL1 = high, and TA= -40°C to +85°C. Typical values at
V
CC
= +3.3V, |VID| = 0.2V, input common-mode voltage VCM= 1.2V, TA= +25°C, unless otherwise noted.) (Note 1)
AC ELECTRICAL CHARACTERISTICS
(VCC= +3.0V to +3.6V, NC/RSEL = open for RL= 75Ω ±1%, NC/RSEL = high for RL= 100Ω ±1%, CL= 5pF, differential input voltage
|V
ID
| = 0.15V to VCC, EN_ = high, SEL0 = low, SEL1 = high, differential input transition time = 0.6ns (20% to 80%), input voltage
(V
IN+
, V
IN-
) = 0 to VCC, LVCMOS/LVTTL inputs = 0 to 3V with 2ns (10% to 90%) transition times, TA= -40°C to +85°C. Typical values
at V
CC
= +3.3V, |VID| = 0.2V, VCM= 1.2V, TA= +25°C, unless otherwise noted.) (Notes 3, 4)
Output Short-Circuit Current I
Both Output Short-Circuit Current I
Output High-Z Current I
Power-Off Output Current I
SUPPLY CURRENT
Supply Current I
High-Z Supply Current I
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
OS
VID = +100mV, V
open
VID = -100mV, V
= 0, other output
OUT_+
= 0,
OUT_-
-12 -20 mA
other output open
OSB
, I
OZ+
OZ-
OFF+, IOFF-
CC
CCZ
VID = +100mV, V
VID = -100mV, V
Disabled, V
V
OUT_-
V
CC
V
OUT_-
= VCC or 0
= 0, V
= 3.6V or 0
OUT_+
OUT_+
RL = 75Ω, CL = 5pF, enabled, quiescent,
Figure 5
RL = 100Ω, CL = 5pF, enabled, quiescent,
Figure 5
RL = 75Ω, CL = 5pF, enabled, switching
at 400MHz (800Mbps), Figure 5 (Note 2)
RL = 100Ω, CL = 5pF, enabled, switching
at 400MHz (800Mbps), Figure 5 (Note 2)
Disabled 15 25 mA
= 0, V
OUT_+
= 0, V
OUT_+
= VCC or 0,
= 3.6V or 0,
OUT_-
OUT_-
= 0
= 0
-12 -20 mA
-1 1 µA
-1 1 µA
38 55
33 50
58 70
52 65
mA
Input to SEL Setup Time (Note 5) t
Input to SEL Hold Time (Note 5) t
SEL to Switched Output t
Disable Time High to Z t
Disable Time Low to Z t
Enable Time Z to High t
Enable Time Z to Low t
Propagation Low-to-High Delay t
Propagation High-to-Low Delay t
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SET
HOLD
SWITCH
PHZ
PLZ
PZH
PZL
PLHD
PHLD
Figures 2, 3 0.4 ns
Figures 2, 3 0.6 ns
Figures 2, 3 1.8 2.5 3.5 ns
Figure 4 3.8 ns
Figure 4 3.8 ns
Figure 4 3.2 ns
Figure 4 3.2 ns
Figures 5, 6 1.7 2.3 3.4
V
= +3.3V, TA = +25°C; Figures 5, 6 2.0 2.3 2.9
CC
Figures 5, 6 1.7 2.3 3.4
VCC = +3.3V, TA = +25°C; Figures 5, 6 2.0 2.3 2.9
ns
ns
DIFFERENTIAL OUTPUT EYE PATTERN
IN 1:2 SPLITTER MODE AT 800Mbps
CONDITIONS: 3.3V, PRBS = 223 -1 DATA PATTERN,
|V
ID
| = 200mV, VCM = +1.2V
HORIZONTAL SCALE = 200ps/div
VERTICAL SCALE = 100mV/div
MAX9152 toc01
150
250
350
450
550
650
50 10075 125 150 175 200
DIFFERENTIAL
OUTPUT VOLTAGE vs. LOAD
MAX9152 toc02
LOAD RESISTOR (Ω)
DIFFERENTIAL OUTPUT VOLTAGE (mV)
NC/RSEL = LOW OR OPEN
NC/RSEL = HIGH
30
32
36
34
38
40
100 300200 400 500 600 700 800
SUPPLY CURRENT vs. DATA RATE
MAX9152 toc03
DATA RATE (Mbps)
SUPPLY CURRENT (mA)
Typical Operating Characteristics
(VCC= +3.3V, RL= 100Ω, NC/RSEL = high, CL= 5pF, input transition time = 600ps (20% to 80%), VID= 200mV, PRBS = 223- 1 data
pattern, VCM= +1.2V, TA= +25°C, unless otherwise noted.)
MAX9152
800Mbps LVDS/LVPECL-to-LVDS 2 x 2
Crosspoint Switch
4 _______________________________________________________________________________________
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC= +3.0V to +3.6V, NC/RSEL = open for RL= 75Ω ±1%, NC/RSEL = high for RL= 100Ω ±1%, CL= 5pF, differential input voltage
|V
ID
| = 0.15V to VCC, EN_ = high, SEL0 = low, SEL1 = high, differential input transition time = 0.6ns (20% to 80%), input voltage
(V
IN+
, V
IN-
) = 0 to VCC, LVCMOS/LVTTL inputs = 0 to 3V with 2ns (10% to 90%) transition times, TA= -40°C to +85°C. Typical values
at V
CC
= +3.3V, |VID| = 0.2V, VCM= 1.2V, TA= +25°C, unless otherwise noted.) (Notes 3, 4)
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except V
TH
, VTL, VID, VOD, and ∆VOD.
Note 2: Guaranteed by design and characterization, not production tested.
Note 3: AC parameters are guaranteed by design and characterization.
Note 4: C
L
includes scope probe and test jig capacitance.
Note 5: t
SET
and t
HOLD
time specify that data must be in a stable state before and after the SEL transition.
Note 6: t
SKEW
is the magnitude difference of differential propagation delay over rated conditions; t
SKEW
= |t
PHLD
- t
PLHD
|.
Note 7: Specification includes test equipment jitter.
Pulse Skew |t
Output Channel-to-Channel Skew t
Output Low-to-High Transition
Time (20% to 80%)
Output High-to-Low Transition
Time (20% to 80%)
LVDS Data Path Peak-to-Peak
Jitter (Note 7)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
-t
PLHD
| (Note 6) t
PHLD
SKEW
CCS
t
LHT
t
HLT
Figures 5, 6 25 90 ps
Figures 5, 7 20 50 ps
Figures 5, 6 160 270 480 ps
Figures 5, 6 160 270 480 ps
VID = 200mV, VCM = 1.2V, 50% duty
cycle, 800Mbps, input transition time =
t
JIT
600ps (20% to 80%)
V
= 200mV, VCM = 1.2V, PRBS = 2
ID
23
- 1
data pattern, 800Mbps, input transition
10 30
65 120
time = 600ps (20% to 80%)
ps