General Description
The MAX9125/MAX9126 quad low-voltage differential
signaling (LVDS) line receivers are ideal for applications requiring high data rates, low power, and reduced
noise. The MAX9125/MAX9126 are guaranteed to
receive data at speeds up to 500Mbps (250MHz) over
controlled-impedance media of approximately 100Ω.
The transmission media may be printed circuit (PC)
board traces or cables.
The MAX9125/MAX9126 accept four LVDS differential
inputs and translate them to 3.3V CMOS outputs. The
MAX9126 features integrated parallel termination resistors (nominally 115Ω), which eliminate the requirement
for four discrete termination resistors and reduce stub
length. The MAX9125 inputs are high impedance and
require an external termination resistor when used in a
point-to-point connection.
The devices support a wide common-mode input range
of 0.05V to 2.35V, allowing for ground potential differences and common-mode noise between the driver
and the receiver. A fail-safe feature sets the output high
when the inputs are open, or when the inputs are
undriven and shorted or parallel terminated. The EN
and EN inputs control the high-impedance output and
are common to all four receivers. Inputs conform to the
ANSI TIA/EIA-644 LVDS standard. The MAX9125/
MAX9126 operate from a single +3.3V supply, are
specified for operation from -40°C to +85°C, and are
available in 16-pin TSSOP and SO packages. Refer to
the MAX9124 data sheet for a quad LVDS line driver.
Applications
Digital Copiers
Laser Printers
Cellular Phone Base Stations
Add/Drop Muxes
Digital Cross-Connects
DSLAMs
Network Switches/Routers
Backplane Interconnect
Clock Distribution
Features
♦ Integrated Termination Eliminates Four External
Resistors (MAX9126)
♦ Pin Compatible with DS90LV032A
♦ Guaranteed 500Mbps Data Rate
♦ 300ps Pulse Skew (max)
♦ Conform to ANSI TIA/EIA-644 LVDS Standard
♦ Single +3.3V Supply
♦ Low 70µA Shutdown Supply Current
♦ Fail-Safe Circuit
MAX9125/MAX9126
Quad LVDS Line Receivers with
Integrated Termination
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
115Ω
MAX9124
MAX9126
115Ω
115Ω
115Ω
R
X
LVDS SIGNALS
100Ω SHIELDED TWISTED CABLE OR MICROSTRIP PC BOARD TRACES
LVTTL/LVCMOS
DATA INPUT
LVTTL/LVCMOS
DATA OUTPUT
R
X
R
X
R
X
T
X
T
X
T
X
T
X
Typical Application Circuit
19-1908; Rev 0; 5/01
EVALUATION KIT
AVAILABLE
Pin Configuration appears at end of data sheet.
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
PART TEMP. RANGE PIN-PACKAGE
MAX9125EUE -40°C to +85°C 16 TSSOP
MAX9125ESE -40°C to +85°C 16 SO
MAX9126EUE -40°C to +85°C 16 TSSOP
MAX9126ESE -40°C to +85°C 16 SO
MAX9125/MAX9126
Quad LVDS Line Receivers with
Integrated Termination
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(VCC= +3.0V to +3.6V, differential input voltage |
V
ID
| = 0.1V to 1.0V, common-mode voltage V
CM
= |
V
ID
/2|
to 2.4V - |V
ID
/2|
, T
A
=
-40°C to +85°C. Typical values are at V
CC
= +3.3V, TA= +25°C, unless otherwise noted.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCCto GND...........................................................-0.3V to +4.0V
IN_+, IN_- to GND .................................................-0.3V to +4.0V
EN, EN to GND...........................................-0.3V to (V
CC
+ 0.3V)
OUT_ to GND .............................................-0.3V to (V
CC
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
16-Pin TSSOP (derate 9.4mW/°C above +70°C) .........755mW
16-Pin SO (derate 8.7mW/°C above +70°C)................696mW
Storage Temperature Range .............................-65°C to +150°C
Maximum Junction Temperature .....................................+150°C
Operating Temperature Range ...........................-40°C to +85°C
Lead Temperature (soldering, 10s) .................................+300°C
ESD Protection (Human Body Model) IN_+, IN_-, OUT_............±7.5kV
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LVDS INPUTS (IN_+, IN_-)
V
TH
mV
V
TL
mV
0.1V ≤VID≤ 0.6V, -20 20
Input Current (MAX9125)
I
IN
_+,
I
IN
_-
0.6V <V
ID
≤ 1.0V -25 25
µA
0.1V ≤VID≤ 0.6V, V
CC
= 0 -20 20
Power-Off Input Current
(MAX9125)
IIN_+,
I
IN
_-
0.6V <V
ID
≤ 1.0V, V
CC
= 0 -25 25
µA
Input Resistor 1 R
IN1
V
CC
= +3.6V or 0, Figure 1 35 kΩ
Input Resistor 2 R
IN2
V
CC
= +3.6V or 0, Figure 1 132 kΩ
Differential Input Resistance
(MAX9126)
R
DIFF
V
CC
= +3.6V or 0, Figure 1 90
Ω
LVCMOS/LVTTL OUTPUTS (OUT_)
Open, undriven short, or
undriven 100Ω parallel
termination
2.7 3.2
IOH =
-4.0mA
V
ID
= +100mV 2.7 3.2
Open or undriven short 2.7 3.2
Output High Voltage V
OH
IOH =
-4.0mA
V
ID
= +100mV 2.7 3.2
V
Output Low Voltage V
OL
IOL = +4.0mA, VID = -100mV 0.1
V
Output Short-Circuit Current I
OS
-15
mA
I
OZ
Disabled, V
OUT
_ = 0 or V
CC
-10
µA
Differential Input High Threshold
Differential Input Low Threshold
Output High-Impedance Current
-100
(MAX9125)
(MAX9126)
Enabled, VID = +100mV, V
_ = 0 (Note 2)
OUT
100
115 132
0.25
-120
+10
MAX9125/MAX9126
Quad LVDS Line Receivers with
Integrated Termination
_______________________________________________________________________________________ 3
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC= +3.0V to +3.6V, differential input voltage |
V
ID
| = 0.1V to 1.0V, common-mode voltage V
CM
= |
V
ID
/2|
to 2.4V - |V
ID
/2|
, T
A
=
-40°C to +85°C. Typical values are at V
CC
= +3.3V, TA= +25°C, unless otherwise noted.) (Note 1)
AC ELECTRICAL CHARACTERISTICS
(VCC= +3.0V to +3.6V, CL= 10pF, differential input voltage |V
ID
| = 0.2V to 1.0V, common-mode voltage V
CM
= |VID/2| to 2.4V
-
|V
ID
/2|, input rise and fall time = 1ns (20% to 80%), input frequency = 100MHz, TA= -40°C to +85°C. Typical values are at VCC=
+3.3V, V
CM
= 1.2V, |V
ID
| = 0.2V, T
A
= +25°C, unless otherwise noted.) (Notes 3, 4)
LOGIC INPUTS (EN, EN)
Input High Voltage V
Input Low Voltage V
Input Current I
SUPPLY
Supply Current I
Disabled Supply Current I
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
IH
IL
IN
CC
CCZ
VIN = VCC or 0 -15 15 µA
Enabled, inputs open 9 15 mA
Disabled, inputs open 70 500 µA
CC
2.0 V
0 0.8 V
Differential Propagation Delay
High to Low
Differential Propagation Delay
Low to High
Differential Pulse Skew
[t
PHLD
Differential Channel-to-Channel
Skew (Note 6)
Differential Part-to-Part Skew
(Note 7)
Differential Part-to-Part Skew
(Note 8)
Rise Time t
Fall Time t
Disable Time High to Z t
Disable Time Low to Z t
Enable Time Z to High t
Enable Time Z to Low t
Maximum Operating Frequency
(Note 9)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
t
] (Note 5)
PLHD
-
t
PHLD
t
PLHD
t
SKD1
t
SKD2
t
SKD3
t
SKD4
TLH
THL
PHZ
PLZ
PZH
PZL
f
MAX
Figures 2 and 3 1.8 2.4 3.3 ns
Figures 2 and 3 1.8 2.3 3.3 ns
Figures 2 and 3 100 300 ps
Figures 2 and 3 400 ps
Figures 2 and 3 0.8 ns
Figures 2 and 3 1.5 ns
Figures 2 and 3 0.34 1.2 ns
Figures 2 and 3 0.32 1.2 ns
RL = 2kΩ, Figures 4 and 5 12 ns
RL = 2kΩ, Figures 4 and 5 12 ns
RL = 2kΩ, Figures 4 and 5 17 ns
RL = 2kΩ, Figures 4 and 5 17 ns
All channels switching 250 300 MHz
V
2.2
2.4
2.3
2.6
2.5
2.7
2.8
100 900 1300500 1700 2100 2500
DIFFERENTIAL PROPAGATION DELAY
vs. DIFFERENTIAL INPUT VOLTAGE
MAX9125/6 toc03
DIFFERENTIAL INPUT VOLTAGE (mV)
DIFFERENTIAL PROPAGATION DELAY (ns)
t
PHLD
t
PLHD
Typical Operating Characteristics
(VCC= +3.3V, |V
ID
| = 200mV, V
CM
= +1.2V, CL= 10pF, frequency = 10MHz, TA= +25°C, unless otherwise noted.) (Figures 2 and 3)
MAX9125/MAX9126
Quad LVDS Line Receivers with
Integrated Termination
4 _______________________________________________________________________________________
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except V
TH
, VTL, and VID.
Note 2: Short only one output at a time. Do not exceed the absolute maximum junction temperature specification.
Note 3: AC parameters are guaranteed by design and characterization.
Note 4: C
L
includes scope probe and test jig capacitance.
Note 5: t
SKD1
is the magnitude difference of differential propagation delays in a channel; t
SKD1
= |t
PHLD
- t
PLHD
|.
Note 6: t
SKD2
is the magnitude difference of the t
PLHD
or t
PHLD
of one channel and the t
PLHD
or t
PHLD
of any other channel on the
same part.
Note 7: t
SKD3
is the magnitude difference of any differential propagation delays between parts operating over rated conditions at
the same V
CC
and within 5°C of each other.
Note 8: t
SKD4
is the magnitude difference of any differential propagation delays between parts operating over rated conditions.
Note 9: f
MAX
generator output conditions: tR= tF< 1ns (0% to 100%), 50% duty cycle, VOL= 1.1V, VOH= 1.3V. Receiver output
criteria: 60% to 40% duty cycle, V
OL
= 0.4V (max), VOH= 2.7V (min), load = 10pF.
100
0
0.01 0.1 1 10 100 1000
SUPPLY CURRENT vs. SWITCHING
FREQUENCY, FOUR CHANNELS SWITCHING
20
MAX9125/6 toc01
SWITCHING FREQUENCY (MHz)
SUPPLY CURRENT (mA)
40
60
80
10
30
50
70
90
VCC = +3.6V
VCC = +3.3V
VCC = +3V
2.8
2.6
2.4
2.2
2.0
-40 10-15 35 60 85
DIFFERENTIAL PROPAGATION DELAY
vs. TEMPERATURE
MAX9125/6 toc02
TEMPERATURE (°C)
DIFFERENTIAL PROPAGATION DELAY (ns)
t
PHLD
t
PLHD
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC= +3.0V to +3.6V, CL = 10pF, differential input voltage |
V
ID
| = 0.2V to 1.0V, common-mode voltage V
CM
= |
V
ID
/2|
to 2.4V
-
|V
ID
/2
|, input rise and fall time = 1ns (20% to 80%), input frequency = 100MHz, T
A
= -40°C to +85°C. Typical values are at VCC=
+3.3V, V
CM
= 1.2V, |V
ID
| = 0.2V, T
A
= +25°C, unless otherwise noted.) (Notes 3, 4)
MAX9125/MAX9126
Quad LVDS Line Receivers with
Integrated Termination
_______________________________________________________________________________________ 5
Typical Operating Characteristics (continued)
(VCC= +3.3V, |V
ID
| = 200mV, V
CM
= +1.2V, CL= 10pF, frequency = 10MHz, TA= +25°C, unless otherwise noted (Figures 2 and 3).)
Pin Description
2.6
2.5
2.4
2.3
2.2
0 1.00.5 1.5 2.0 2.5
DIFFERENTIAL PROPAGATION DELAY
vs. COMMON-MODE VOLTAGE
MAX9125/6 toc04
COMMON-MODE VOLTAGE (V)
DIFFERENTIAL PROPAGATION DELAY (ns)
t
PHLD
t
PLHD
50
100
75
150
125
175
200
-40 10 35-15 60 85
PULSE SKEW vs. TEMPERATURE
MAX9125/6 toc07
TEMPERATURE (°C)
SKEW (ps)
0
900
400
200
500
1000
51510 20 25
TRANSITION TIME vs. CAPACITIVE LOAD
MAX9125/6 toc08
CAPACITIVE LOAD (pF)
TRANSITION TIME (ps)
t
TLH
t
THL
800
700
600
300
100
2.2
2.3
2.5
2.4
2.6
3.0 3.2 3.33.1 3.4 3.5 3.6
DIFFERENTIAL PROPAGATION DELAY
vs. SUPPLY VOLTAGE
MAX9125/6 toc05
SUPPLY VOLTAGE (V)
DIFFERENTIAL PROPAGATION DELAY (ns)
t
PHLD
t
PLHD
50
100
75
150
125
175
200
3.0 3.2 3.33.1 3.4 3.5 3.6
PULSE SKEW vs. SUPPLY VOLTAGE
MAX9125/6 toc06
SUPPLY VOLTAGE (V)
SKEW (ps)
PIN NAME FUNCTION
1, 7, 9, 15 IN_- Inverting Differential Receiver Inputs
2, 6, 10, 14 IN_+ Noninverting Differential Receiver Inputs
3, 5, 11, 13 OUT_ LVCMOS/LVTTL Receiver Outputs
4, 12 EN, EN
8 GND Ground
16 V
Receiver Enable Inputs. When EN = low and EN = high, the outputs are disabled and in high
impedance. For other combinations of EN and EN, the outputs are active.
CC
Power Supply Input. Bypass VCC to GND with 0.1µF and 0.001µF ceramic capacitors.
MAX9125/MAX9126
Detailed Description
The LVDS interface standard is a signaling method
intended for point-to-point communication over a controlled-impedance medium as defined by the ANSI
TIA/EIA-644 and IEEE 1596.3 standards. The LVDS
standard uses a lower voltage swing than other common communication standards, achieving higher data
rates with reduced power consumption while reducing
EMI emissions and system susceptibility to noise.
The MAX9125/MAX9126 are 500Mbps, four-channel
LVDS receivers intended for high-speed, point-to-point,
low-power applications. Each channel accepts an
LVDS input and translates it to an LVTTL/LVCMOS output. The receiver is capable of detecting differential
signals as low as 100mV and as high as 1V within an
input voltage range of 0 to 2.4V. The 250mV to 400mV
differential output of an LVDS driver is nominally centered around a +1.2V offset. This offset, coupled with
the receiver’s 0 to 2.4V input voltage range, allows an
approximate ±1V shift in the signal (as seen by the
receiver). This allows for a difference in ground references of the transmitter and the receiver, the commonmode effects of coupled noise, or both. The LVDS
standards specify an input voltage range of 0 to 2.4V
referenced to receiver ground.
The MAX9126 has an integrated termination resistor
internally connected across each receiver input. The
internal termination saves board space, eases layout,
and reduces “stub length” compared to an external termination resistor. In other words, the transmission line
is terminated on the IC.
Quad LVDS Line Receivers with
Integrated Termination
6 _______________________________________________________________________________________
Table 1. Input/Output Function Table
Figure 1. Inputs with Internal Fail-Safe Circuitry
EN EN (IN_+) - (IN_-) OUT_
LH X Z
All other combinations of ENABLE inputs
ENABLES INPUTS OUTPUT
V
CC
R
IN2
- 0.3V
V
CC
IN_+
R
IN1
R
IN1
VID ≥ +100mV H
VID ≤ -100mV L
Open, undriven short, or
MAX9125
MAX9126 Open or undriven short
IN_+
R
OUT_
R
DIFF
R
undriven 100Ω parallel
termination
V
CC
R
IN2
- 0.3V
V
CC
IN1
IN1
OUT_
H
IN_-
MAX9125 MAX9126
IN_-
MAX9125/MAX9126
Quad LVDS Line Receivers with
Integrated Termination
_______________________________________________________________________________________ 7
Figure 2. Transition Time and Propagation Delay Test Circuit
Figure 3. Transition Time and Propagation Delay Timing Diagram
Figure 4. High-Z Delay Test Circuit
PULSE**
GENERATOR
50Ω*50Ω*
*50Ω REQUIRED FOR PULSE GENERATOR.
**WHEN TESTING MAX9126, ADJUST THE PULSE GENERATOR OUTPUT
TO ACCOUNT FOR INTERNAL TERMINATION RESISTOR.
IN_-
O (DIFFERENTIAL)
IN_+
t
PLHD
80% 80%
50%
NOTE: V
CM =
(V
- + VIN_+)
IN_
2
IN_+
IN_-
V
ID
OUT_
C
L
RECEIVER ENABLED
1/4 MAX9125/MAX9126
O (DIFFERENTIAL)
t
PHLD
50%
V
OH
OUT_
t
TLH
GENERATOR
INCLUDES LOAD AND TEST JIG CAPACITANCE.
C
L
= VCC FOR t
S
1
= GND FOR t
S
1
PZL
PZH
AND t
AND t
50Ω
EN
EN
1/4 MAX9125/MAX9126
MEASUREMENTS.
PLZ
MEASUREMENTS.
PHZ
IN_+
IN_-
V
CC
DEVICE
UNDER
TEST
20%20%
V
t
THL
S
1
R
L
OUT_
C
L
OL
MAX9125/MAX9126
Fail-Safe
The fail-safe feature of the MAX9125/MAX9126 sets the
output high when:
• Inputs are open.
• Inputs are undriven and shorted.
• Inputs are undriven and terminated.
A fail-safe circuit is important because under these
conditions, noise at the inputs may switch the receiver
and it may appear to the system that data is being
received. Open or undriven terminated input conditions
can occur when a cable is disconnected or cut, or
when the LVDS driver outputs are high impedance. A
short condition can occur because of a cable failure.
The fail-safe input network (Figure 1) samples the input
common-mode voltage and compares it to VCC- 0.3V
(nominal). When the input is driven to levels specified in
the LVDS standards, the input common-mode voltage
is less than VCC- 0.3V and the fail-safe circuit is not
activated. If the inputs are open or if the inputs are
undriven and shorted or undriven and parallel terminated, there is no input current. In this case, a pullup resistor in the fail-safe circuit pulls both inputs above VCC-
0.3V, activating the fail-safe circuit and forcing the output high.
Applications Information
Power-Supply Bypassing
Bypass the VCCpin with high-frequency surface-mount
ceramic 0.1µF and 0.001µF capacitors in parallel, as
close to the device as possible, with the smaller valued
capacitor closest to VCC.
Differential Traces
Input trace characteristics affect the performance of the
MAX9125/MAX9126. Use controlled-impedance PC
board traces to match the cable characteristic impedance. The termination resistor is also matched to this
characteristic impedance.
Eliminate reflections and ensure that noise couples as
common mode by running the differential traces close
together. Reduce skew by matching the electrical
length of the traces. Excessive skew can result in a
degradation of magnetic field cancellation.
Each channel’s differential signals should be routed
close to each other to cancel their external magnetic
field. Maintain a constant distance between the differential traces to avoid discontinuities in differential
impedance. Avoid 90° turns and vias to further prevent
impedance discontinuities.
Cables and Connectors
Transmission media typically have a controlled differential impedance of 100Ω. Use cables and connectors
Quad LVDS Line Receivers with
Integrated Termination
8 _______________________________________________________________________________________
Figure 5. High-Z Delay Waveforms
EN WHEN EN = V
EN WHEN EN = GND
OUTPUT WHEN
OUTPUT WHEN
= -100mV
V
ID
= +100mV
V
ID
CC
1.5V
1.5V
t
PLZ
0.5V
t
PHZ
0.5V
3V
1.5V
0
3V
1.5V
0
t
PZL
50%
t
PZH
50%
V
V
V
GND
CC
OL
OH
that have matched differential impedance to minimize
impedance discontinuities.
Avoid the use of unbalanced cables such as ribbon or
simple coaxial cable. Balanced cables such as twisted
pair offer superior signal quality and tend to generate
less EMI due to canceling effects. Balanced cables
pick up noise as common mode, which is rejected by
the LVDS receiver.
Termination
The MAX9126 has an integrated termination resistor
connected across the inputs of each receiver. The
value of the integrated resistor is specified in the DC
characteristics.
The MAX9125 requires an external termination resistor.
The termination resistor should match the differential
impedance of the transmission line. Termination resistance values range between 90Ω and 132Ω, depending on the characteristic impedance of the transmission
medium.
When using the MAX9125, minimize the distance
between the input termination resistors and the MAX9125
receiver inputs. Use 1% surface-mount resistors.
Board Layout
Keep the LVDS and any other digital signals separated
from each other to reduce crosstalk.
For LVDS applications, use a four-layer PC board that
provides separate power, ground, LVDS signals, and
output signals. Isolate the input LVDS signals from the
output LVCMOS/LVTTL signals to prevent coupling.
Separate the input LVDS signal plane from the LVCMOS/LVTTL output signal plane with the power and
ground planes for best results.
Chip Information
TRANSISTOR COUNT: 940
PROCESS: CMOS
MAX9125/MAX9126
Quad LVDS Line Receivers with
Integrated Termination
_______________________________________________________________________________________ 9
MAX9125/MAX9126
Quad LVDS Line Receivers with
Integrated Termination
10 ______________________________________________________________________________________
Functional Diagram
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
IN1- V
CC
IN4-
IN4+
OUT4
OUT3
IN3+
TOP VIEW
MAX9125
MAX9126
TSSOP/SO
IN3-
EN
IN1+
OUT1
IN2+
EN
OUT2
IN2-
GND
Pin Configuration
V
CC
V
CC
IN1+
I
N1-
IN2+
I
N2-
IN3+
I
IN4+
I
N3-
N4-
EN
EN
MAX9125
I
N1+
Rx
Rx
Rx
Rx
OUT1
OUT2
OUT3
OUT4
GND GND
R
DIFF
I
N1-
I
N2+
R
DIFF
I
N2-
I
N3+
R
DIFF
I
N3-
I
N4+
R
DIFF
I
N4-
EN
EN
MAX9126
Rx
Rx
Rx
Rx
OUT1
OUT2
OUT3
OUT4
MAX9125/MAX9126
Quad LVDS Line Receivers with
Integrated Termination
______________________________________________________________________________________ 11
Package Information
TSSOP,NO PADS.EPS
MAX9125/MAX9126
Quad LVDS Line Receivers with
Integrated Termination
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Package Information (continued)
SOICN.EPS
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