General Description
The MAX9124 quad low-voltage differential signaling
(LVDS) line driver is ideal for applications requiring high
data rates, low power, and low noise. The MAX9124 is
guaranteed to transmit data at speeds up to 800Mbps
(400MHz) over controlled impedance media of approximately 100Ω. The transmission media may be printed
circuit (PC) board traces, backplanes, or cables.
The MAX9124 accepts four LVTTL/LVCMOS input levels
and translates them to LVDS output signals. Moreover,
the MAX9124 is capable of setting all four outputs to a
high-impedance state through two enable inputs, EN and
EN, thus dropping the device to an ultra-low-power state
of 16mW (typ) during high impedance. The enables are
common to all four transmitters. Outputs conform to the
ANSI TIA/EIA-644 LVDS standard.
The MAX9124 operates from a single +3.3V supply and is
specified for operation from -40°C to +85°C. It is available
in 16-pin TSSOP and SO packages. Refer to the MAX9125/
MAX9126 data sheet for quad LVDS line receivers.
Applications
Features
♦ Pin Compatible with DS90LV031A
♦ Guaranteed 800Mbps Data Rate
♦ 250ps Maximum Pulse Skew
♦ Conforms to TIA/EIA-644 LVDS Standard
♦ Single +3.3V Supply
♦ 16-Pin TSSOP and SO Packages
MAX9124
Quad LVDS Line Driver
________________________________________________________________ Maxim Integrated Products 1
Pin Configuration
Ordering Information
115Ω
MAX9124
MAX9126
115Ω
115Ω
115Ω
R
X
LVDS SIGNALS
100Ω SHIELDED TWISTED CABLE OR MICROSTRIP PC BOARD TRACES
LVTTL/LVCMOS
DATA INPUT
LVTTL/LVCMOS
DATA OUTPUT
R
X
R
X
R
X
T
X
T
X
T
X
T
X
Typical Applications Circuit
19-1991; Rev 0; 4/01
EVALUATION KIT
AVAILABLE
* Future product—contact factory for availability.
Digital Copiers
Laser Printers
Cell Phone Base
Stations
Add/Drop Muxes
Digital Cross-Connects
DSLAMs
Network
Switches/Routers
Backplane
Interconnect
Clock Distribution
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
PART TEMP. RANGE PIN-PACKAGE
MAX9124EUE -40°C to +85°C 16 TSSOP
MAX9124ESE -40°C to +85°C 16 SO
TOP VIEW
1
IN1 V
OUT1+
2
OUT1-
OUT2-
OUT2+
GND
EN
IN2
3
4
5
6
7
8
MAX9124
TSSOP/SO
16
CC
IN4
15
OUT4+
14
OUT4-
13
EN
12
OUT3-
11
OUT3+
10
IN3
9
MAX9124
Quad LVDS Line Driver
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(VCC= +3.0V to +3.6V, RL= 100Ω ±1%, TA= -40°C to +85°C. Typical values are at VCC= +3.3V, TA= +25°C, unless otherwise
noted.) (Notes 1, 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCCto GND...........................................................-0.3V to +4.0V
IN_, EN, EN to GND....................................-0.3V to (V
CC
+ 0.3V)
OUT_+, OUT_- to GND..........................................-0.3V to +3.9V
Short-Circuit Duration (OUT_+, OUT_-) .....................Continuous
Continuous Power Dissipation (T
A
= +70°C)
16-Pin TSSOP (derate 9.4mW/°C above +70°C) .........755mW
16-Pin SO (derate 8.7mW/°C above +70°C)................696mW
Storage Temperature Range .............................-65°C to +150°C
Maximum Junction Temperature .....................................+150°C
Operating Temperature Range ...........................-40°C to +85°C
Lead Temperature (soldering, 10s) .................................+300°C
ESD Protection
Human Body Model, OUT_+, OUT_- ..............................±6kV
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LVDS OUTPUT (OUT_+, OUT_-)
Differential Output Voltage V
OD
Figure 1
368 450 mV
Change in Magnitude of V
OD
Between Complementary Output
States
∆V
OD
Figure 1 1 25 mV
Offset Voltage V
OS
Figure 1
V
Change in Magnitude of V
OS
Between Complementary Output
States
∆V
OS
Figure 1 4 25 mV
Output High Voltage V
OH
1.6 V
Output Low Voltage V
OL
V
Differential Output Short-Circuit
Current (Note 3)
I
OSD
Enabled, VOD = 0 -9 mA
Output Short-Circuit Current I
OS
OUT_+ = 0 at IN_ = VCC or OUT_- = 0 at IN_
= 0, enabled
-9 mA
Output High-Impedance Current
I
OZ
OUT_- = 0 or VCC , RL = ∞
-10 10 µA
Power-Off Output Current I
OFF
VCC = 0 or open, OUT_+ = 0 or 3.6V, OUT_= 0 or 3.6V, R
L
= ∞
-10 10 µA
INPUTS (IN_, EN, EN)
High-Level Input Voltage V
IH
2.0
V
Low-Level Input Voltage V
IL
0.8 V
Input Current I
IN
IN_, EN, EN = 0 or V
CC
-20 20 µA
SUPPLY CURRENT
No-Load Supply Current I
CC
RL = ∞, IN_ = VCC or 0 for all channels 9.2 11 mA
Loaded Supply Current I
CCL
RL = 100Ω, IN_ = VCC or 0 for all channels
30 mA
Disabled Supply Current I
CCZ
D i sab l ed , IN _ = V
C C
or 0 for all channel s,
E N = 0, EN = V
CC
4.9 6 mA
250
1.125 1.25 1.375
0.90
-3.8
EN = low and EN = high, OUT_+ = 0 or VCC,
GND
22.7
V
CC
MAX9124
Quad LVDS Line Driver
_______________________________________________________________________________________ 3
SWITCHING CHARACTERISTICS
(VCC= +3.0V to +3.6V, RL= 100Ω ±1%, CL= 10pF, TA= -40°C to +85°C. Typical values are at VCC= +3.3V, TA= +25°C, unless
otherwise noted.) (Notes 4, 5, 6)
Note 1: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are 100% tested
at T
A
= +25°C.
Note 2: Currents into the device are positive, and current out of the device is negative. All voltages are referenced to ground except
V
OD
.
Note 3: Guaranteed by correlation data.
Note 4: AC parameters are guaranteed by design and characterization.
Note 5: C
L
includes probe and jig capacitance.
Note 6: Signal generator conditions for dynamic tests: V
OL
= 0, VOH= 3V, f = 100MHz, 50% duty cycle, RO= 50Ω, tR≤ 1ns, tF≤
1ns (0% to 100%).
Note 7: t
SKD1
is the magnitude difference of differential propagation delay. t
SKD1
= |t
PHLD
- t
PLHD
|.
Note 8: t
SKD2
is the magnitude difference of t
PHLD
or t
PLHD
of one channel to the t
PHLD
or t
PLHD
of another channel on the same
device.
Note 9: t
SKD3
is the magnitude difference of any differential propagation delays between devices at the same VCCand within 5°C
of each other.
Note 10: t
SKD4
is the magnitude difference of any differential propagation delays between devices operating over the rated supply
and temperature ranges.
Note 11: f
MAX
signal generator conditions: VOL= 0, VOH= 3V, f = 400MHz, 50% duty cycle, RO= 50Ω, tR≤ 1ns, tF≤ 1ns (0% to
100%). Transmitter output criteria: duty cycle = 45% to 55%, V
OD
≥ 250mV.
Differential Propagation Delay
High to Low
Differential Propagation Delay
Low to High
Differential Pulse Skew (Note 7) t
Differential Channel-to-Channel
Skew (Note 8)
Differential Part-to-Part Skew
(Note 9)
Differential Part-to-Part Skew
(Note 10)
Rise Time t
Fall Time t
Disable Time High to Z t
Disable Time Low to Z t
Enable Time Z to High t
Enable Time Z to Low t
Maximum Operating Frequency
(Note 11)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
t
PHLD
t
PLHD
SKD1
t
SKD2
t
SKD3
t
SKD4
TLH
THL
PHZ
PLZ
PZH
PZL
f
MAX
Figures 2 and 3 0.8 1.42 2.0 ns
Figures 2 and 3 0.8 1.44 2.0 ns
Figures 2 and 3 0.02 0.25 ns
Figures 2 and 3 0.35 ns
Figures 2 and 3 0.8 ns
Figures 2 and 3
1.2 ns
Figures 2 and 3 0.1 0.35 0.7 ns
Figures 2 and 3 0.1 0.35 0.7 ns
Figures 4 and 5 5 ns
Figures 4 and 5 5 ns
Figures 4 and 5 5 ns
Figures 4 and 5 5 ns
400 MHz
Pin Description
MAX9124
Quad LVDS Line Driver
4 _______________________________________________________________________________________
Typical Operating Characteristics
(TA= +25°C)
0.30
0.70
0.50
1.30
1.10
0.90
1.90
1.70
1.50
2.10
50 150 200100 250 300 350 400
SINGLE-ENDED OUTPUT VOLTAGE
vs. LOAD RESISTANCE
(R
L
= 50Ω TO 400Ω)
MAX9124 toc01
RL (Ω)
SINGLE-ENDED OUTPUT VOLTAGE (V)
VCC = +3.6V
_V
CC
= +3.0V
OUT_+
OUT_-
0
0.40
0.20
0.60
0.80
1.00
1.20
1.40
1.60
1.80
2.00
2.20
2.40
0 1000 2000 5000 6000 7000
SINGLE-ENDED OUTPUT VOLTAGE vs.
LOAD RESISTANCE
(R
L
= 0 TO 7kΩ)
MAX9124 toc02
RL (Ω)
SINGLE-ENDED OUTPUT VOLTAGE (V)
3000 4000
VCC = +3.6V
_V
CC
= +3.0V
D
OUT
+
D
OUT
-
PIN NAME FUNCTION
1, 7, 9, 15 IN_ LVTTL/LVCMOS Driver Inputs
2, 6, 10, 14 OUT_+ Noninverting LVDS Driver Outputs
3, 5, 11, 13 OUT_- Inverting LVDS Driver Outputs
4, 12 EN, EN
8 GND Ground
16 V
Driver Enable Inputs. The driver is disabled and in high impedance when EN is low and EN is high.
For other combinations of EN and EN, the outputs are active.
CC
Power-Supply Input. Bypass VCC to GND with 0.1µF and 0.001µF ceramic capacitors.
MAX9124
Quad LVDS Line Driver
_______________________________________________________________________________________ 5
Detailed Description
The LVDS interface standard is a signaling method
intended for point-to-point communication over a controlled-impedance medium as defined by the
ANSI/TIA/EIA-644 and IEEE 1596.3 standards. The
LVDS standard uses a lower voltage swing than other
common communication standards, achieving higher
data rates with reduced power consumption while
reducing EMI emissions and system susceptibility to
noise.
The MAX9124 is an 800Mbps quad differential LVDS
driver that is designed for high-speed, point-to-point,
and low-power applications. This device accepts
LVTTL/LVCMOS input levels and translates them to
LVDS output signals.
The MAX9124 generates a 2.5mA to 4.0mA output current using a current-steering configuration. This currentsteering approach induces less ground bounce and no
shoot-through current, enhancing noise margin and system speed performance. The driver outputs are shortcircuit current limited and enter a high-impedance state
when the device is not powered or is disabled.
The current-steering architecture of the MAX9124
requires a resistive load to terminate the signal and
complete the transmission loop. Because the device
switches current and not voltage, the actual output voltage swing is determined by the value of the termination
resistor at the input of an LVDS receiver. Logic states
are determined by the direction of current flow through
the termination resistor. With a typical 3.7mA output
current, the MAX9124 produces an output voltage of
370mV when driving a 100Ω load.
Termination
Because the MAX9124 is a current-steering device, no
output voltage will be generated without a termination
resistor. The termination resistors should match the differential impedance of the transmission line. Output
voltage levels depend upon the value of the termination
resistor. The MAX9124 is optimized for point-to-point
interface with 100Ω termination resistors at the receiver
inputs. Termination resistance values may range
between 90Ω and 132Ω, depending on the characteristic impedance of the transmission medium.
Applications Information
Power-Supply Bypassing
Bypass VCCwith high-frequency, surface-mount
ceramic 0.1µF and 0.001µF capacitors in parallel as
close to the device as possible, with the smaller valued
capacitor closest to V
CC
.
Differential Traces
Output trace characteristics affect the performance of
the MAX9124. Use controlled-impedance traces to
match trace impedance to the transmission medium.
Eliminate reflections and ensure that noise couples as
common mode by running the differential trace pairs
close together. Reduce skew by matching the electrical
length of the traces. Excessive skew can result in a
degradation of magnetic field cancellation.
Maintain the distance between the differential traces to
avoid discontinuities in differential impedance. Avoid
90° turns and minimize the number of vias to further
prevent impedance discontinuities.
Cables and Connectors
Transmission media should have a nominal differential
impedance of 100Ω. To minimize impedance discontinuities, use cables and connectors that have matched
differential impedance.
Avoid the use of unbalanced cables such as ribbon or
simple coaxial cable. Balanced cables, such as twisted
pair, offer superior signal quality and tend to generate
less EMI due to canceling effects. Balanced cables
tend to pick up noise as common mode, which is
rejected by the LVDS receiver.
Board Layout
For LVDS applications, a four-layer PC board that provides separate power, ground, LVDS signals, and input
signals is recommended. Isolate the LVTTL/LVCMOS
and LVDS signals from each other to prevent coupling.
Chip Information
TRANSISTOR COUNT: 2007
PROCESS: CMOS
Table 1. Input/Output Function Table
ENABLES INPUTS OUTPUTS
EN EN IN_ OUT_+ OUT_ -
LHXZZ
All other combinations
of ENABLE inputs
LLH
HHL
MAX9124
Quad LVDS Line Driver
6 _______________________________________________________________________________________
Figure 4. Driver High-Impedance Delay Test Circuit
Figure 1. Driver VODand VOSTest Circuit
Figure 2. Driver Propagation Delay and Transition Time Test
Circuit
Figure 3. Driver Propagation Delay and Transition Time Waveforms
OUT_+
C
L
V
CC
IN_
GND
IN_
OUT_
OUT_+
V
DIFF
R
OUT_ +
L
OUT_ -
RL/2
R
L
50Ω
IN_
C
L
OS
V
V
V
OS
OD
GENERATOR
/2
OUT_-
3V
OUT_
80%
-)
1.5V
t
PHLD
0
V
OH
0
V
OL
0
20%
t
THL
1.5V
t
-
PLHD
0 DIFFERENTIAL
80%
V
= (V
50%
0
DIFF
OUT_
+) - (V
20%
t
TLH
C
L
OUT_+
V
GENERATOR
CC
GND
EN
EN
50Ω
IN_
1/4 MAX9124
R
L/2
+1.2V
R
L/2
OUT_-
C
L
MAX9124
Quad LVDS Line Driver
_______________________________________________________________________________________ 7
Figure 5. Driver High-Impedance Delay Waveform
Functional Diagram
EN WHEN EN = V
EN WHEN EN = 0
OUT_+ WHEN IN_ = V
OUT_- WHEN IN_ = 0
OUT_+ WHEN IN_ = 0
OUT_- WHEN IN_ = V
CC
CC
CC
OUT1+
IN1
OUT1-
t
t
1.5V
1.5V
PHZ
PLZ
1.5V
1.5V
3V
0
3V
t
PZH
50%50%
50%50%
t
PZL
0
V
1.2V
1.2V
V
OH
OL
OUT2+
IN2
OUT2-
OUT3+
IN3
OUT3-
OUT4+
IN4
OUT4-
EN
EN
MAX9124
Quad LVDS Line Driver
8 _______________________________________________________________________________________
Package Information
TSSOP,NO PADS.EPS
MAX9124
Quad LVDS Line Driver
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9
© 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Package Information (continued)
SOICN.EPS
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