General Description
The MAX9115 is a single low-voltage differential signaling (LVDS) line receiver ideal for applications requiring
high data rates, low power, and low noise. The device
is guaranteed to receive data at speeds up to 200Mbps
(100MHz).
The MAX9115 accepts an LVDS differential input and
translates it to an LVTTL/LVCMOS output. The fail-safe
feature sets the output high when the inputs are undriven and open, terminated, or shorted. The device supports a wide common-mode input range, allowing a
ground potential difference and common-mode noise
between the driver and the receiver. The MAX9115
conforms to the ANSI TIA/EIA-644 LVDS standard.
The MAX9115 operates from a single +3.3V supply,
and is specified for operation from -40°C to +85°C. It is
available in a space-saving 5-pin SC70 package. Refer
to the MAX9110/MAX9112 data sheet for single/dual
LVDS line drivers.
Applications
Clock Distribution
Cellular Phone Base Stations
Digital Cross-Connects
Network Switches/Routers
DSLAMs
Laser Printers
Features
♦ Space-Saving SC70 Package (50% Smaller than
SOT23)
♦ Guaranteed 200Mbps Data Rate
♦ Low 350ps (max) Pulse Skew
♦ High-Impedance LVDS Inputs When Powered Off
Allow Hot Swapping
♦ Conforms to ANSI TIA/EIA-644 LVDS Standard
♦ Single +3.3V Supply
♦ Fail-Safe Circuit Sets Output High for Undriven
Inputs (Open, Terminated, or Shorted)
♦ Low 150µA (typ) Supply Current in Fail-Safe Mode
MAX9115
Single LVDS Line Receiver in SC70
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
19-1995; Rev 0; 4/01
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Typical Application Circuit
GND
IN+IN-
15OUTVCC
MAX9115
SC70
TOP VIEW
2
34
Rx
Pin Configuration
PART
MAX9115EXK-T -40°C to +85°C 5 SC70-5 ACI
TEMP.
RANGE
PINPACKAGE
TOP
MARK
CLOCK
INPUT
MAX9115
Rx
CLOCK
SOURCE
REFERENCE CLOCK DISTRIBUTION
USING MAX9115 IN A MULTIDROP CONFIGURATION
Tx
MAX9115
Rx
CLOCK
INPUT
LVDS SIGNALS
MAX9115
Rx
CLOCK
INPUT
100Ω
TERMINATION
MAX9115
Single LVDS Line Receiver in SC70
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(VCC= +3.0V to +3.6V, differential input voltage |VID| = 0.05V to 1.0V, input common voltage VCM= |VID/2| to 2.4V - |VID/2|,
T
A
= -40°C to +85°C, unless otherwise noted. Typical values at VCC= +3.3V, TA= +25°C.) (Notes 2, 3)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Note 1: Package leads soldered to a PC board having copper ground and VCCplanes. Do not exceed Maximum Junction Temperature.
V
CC
to GND...........................................................-0.3V to +4.0V
IN+, IN- to GND.....................................................-0.3V to +4.0V
OUT to GND ...............................................-0.3V to (V
CC
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
5-Pin SC70 (derate 3.1mW/°C above +70°C).............247 mW
Output Short to GND (OUT) (Note 1)........................................1s
Storage Temperature Range .............................-65°C to +150°C
Maximum Junction Temperature .....................................+150°C
Operating Temperature Range ...........................-40°C to +85°C
Lead Temperature (soldering, 10s) .................................+300°C
ESD Protection
Human Body Model (IN+, IN-) .........................................±6kV
LVDS INPUTS (IN+, IN-)
Differential Input High Threshold V
Differential Input Low Threshold V
Input Current I
Power-Off Input Current I
Input Resistance
LVTTL/LVCMOS OUTPUT (OUT)
Output High Voltage V
Output Low Voltage V
Output Short-Circuit Current I
SUPPLY CURRENT
Supply Current I
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TH
TL
0.05V ≤VID≤ 0.6V -20 20
, I
IN+
IN-
0.6V <VID≤ 1.0V -25 25
INO
R
R
OS
CC
0.05V ≤VID≤ 0.6V, V
0.6V <VID≤ 1.0V, V
VCC = +3.6V or 0, Figure 1 35
IN1
VCC = +3.6V or 0, Figure 1 132
IN2
OHIOH
OL
= - 8.0m A
IOL = +8.0mA, VID = -50mV 0.25 V
VID = +50mV, V
No load, inputs undriven (fail-safe) 150 300 µA
No load, inputs driven 7 mA
50 mV
-50 mV
= 0 -20 20
CC
= 0 -25 25
CC
Inp uts op en or und r i ven shor t
or und r i ven 100Ω ter m i nati on
= +50mV VCC - 0.3
V
ID
= 0 -125 mA
OUT
- 0.3
V
CC
µA
µA
kΩ
V
MAX9115
Single LVDS Line Receiver in SC70
_______________________________________________________________________________________ 3
AC ELECTRICAL CHARACTERISTICS
(VCC= +3.0V to +3.6V, CL= 15pF, differential input voltage |VID| = 0.15V to 1.0V, input common voltage VCM= |VID/2| to 2.4V - |V
ID
/2|, input rise and fall time = 1ns (20% to 80%), input frequency = 100MHz, TA= -40°C to +85°C, unless otherwise noted. Typical values at V
CC
= +3.3V, |VID| = 0.2V, VCM= 1.2V, TA= +25°C.) (Figures 2 and 3) (Notes 4 and 5)
Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production
tested at T
A
= +25°C.
Note 3: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except V
TH
, VTL, and VID.
Note 4: AC parameters are guaranteed by design and characterization.
Note 5: CL includes scope probe and test jig capacitance.
Note 6: t
SKD1
is the magnitude difference of differential propagation delays. t
SKD1
= |t
PHLD
- t
PLHD
|.
Note 7: t
SKD2
is the magnitude difference of any differential propagation delays between parts operating over rated conditions at
the same V
CC
and within 5°C of each other.
Note 8: t
SKD3
is the magnitude difference of any differential propagation delays between parts operating over rated conditions.
Note 9: f
MAX
pulse generator output conditions: rise-time = fall-time = 1ns (0% to 100%), 50% duty cycle, VOH= +1.3V, VOL=
+1.1V. MAX9115 output criteria: 60% to 40% duty cycle, V
OL
= 0.25V max, VOH= 2.7V min, load = 15pF.
Differential Propagation Delay
High to Low
Differential Propagation Delay
Low to High
Differential Pulse Skew
|t
PHLD
Differential Part-to-Part Skew
(Note 7)
Differential Part-to-Part Skew
(Note 8)
Rise-Time t
Fall-Time t
Maximum Operating Frequency
(Note 9)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
t
PHLD
t
PLHD
t
t
| (Note 6)
PLHD
-
SKD1
t
SKD2
t
SKD3
TLH
THL
f
MAX
1.2 1.9 3 ns
1.2 1.9 3 ns
350 ps
1.3 ns
1.8 ns
0.5 0.8 ns
0.5 0.8 ns
100 MHz
MAX9115
Single LVDS Line Receiver in SC70
4 _______________________________________________________________________________________
Typical Operating Characteristics
(VCC= +3.3V, CL= 15pF, |VID| = 0.2V, VCM= 1.2V, input rise and fall time = 1ns (20% to 80%), input frequency = 100MHz, 50%
duty cycle, T
A
= +25°C, unless otherwise noted.)
0
10
30
40
1 10 100 1000
SUPPLY CURRENT
vs. FREQUENCY
MAX9115 toc01
FREQUENCY (MHz)
SUPPLY CURRENT (mA)
20
6.00
5.50
5.00
4.50
4.00
-40 10-15 35 60 85
SUPPLY CURRENT vs. TEMPERATURE
MAX9115 toc02
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
-60
-65
-75
-70
-80
-85
3.0 3.3 3.6
OUTPUT SHORT-CIRCUIT CURRENT
vs. SUPPLY VOLTAGE
MAX9115 toc03
SUPPLY VOLTAGE (V)
OUTPUT SHORT-CIRCUIT CURRENT (mA)
3.60
3.40
3.20
3.00
2.80
3.0 3.3 3.6
OUTPUT HIGH VOLTAGE
vs. SUPPLY VOLTAGE
MAX9115 toc04
SUPPLY VOLTAGE (V)
OUTPUT HIGH VOLTAGE (V)
84.0
84.5
85.0
85.5
86.0
86.5
87.0
87.5
88.0
3.0 3.3 3.6
OUTPUT LOW VOLTAGE
vs. SUPPLY VOLTAGE
MAX9115 toc05
SUPPLY VOLTAGE (V)
OUTPUT LOW VOLTAGE (mV)
1.6
1.8
2.0
2.2
3.0 3.3 3.6
DIFFERENTIAL PROPAGATION DELAY
vs. SUPPLY VOLTAGE
MAX9115 toc06
SUPPLY VOLTAGE (V)
DIFFERENTIAL PROPAGATION DELAY (ns)
t
PHLD
t
PLHD
1.73
1.90
1.86
2.15
2.03
2.40
2.28
2.53
-40 10-15 35 60 85
DIFFERENTIAL PROPAGATION DELAY
vs. TEMPERATURE
MAX9115 toc07
TEMPERATURE (°C)
DIFFERENTIAL PROPAGATION DELAY (ns)
t
PHLD
t
PLHD
MAX9115
Single LVDS Line Receiver in SC70
_______________________________________________________________________________________ 5
Typical Operating Characteristics (continued)
(VCC= +3.3V, CL= 15pF, |VID| = 0.2V, VCM= 1.2V, input rise and fall time = 1ns (20% to 80%), input frequency = 100MHz, 50%
duty cycle, T
A
= +25°C, unless otherwise noted.)
60
50
40
30
20
DIFFERENTIAL SKEW (ps)
10
0
3.0 3.3 3.6
DIFFERENTIAL SKEW
vs. SUPPLY VOLTAGE
MAX9115 toc08
SUPPLY VOLTAGE (V)
DIFFERENTIAL PROPAGATION DELAY
vs. DIFFERENTIAL INPUT VOLTAGE
2.1
2.0
1.9
DIFFERENTIAL PROPAGATION DELAY (ns)
1.8
0.1 0.30.2 0.4 0.5 0.6
DIFFERENTIAL INPUT VOLTAGE (V)
TRANSITION TIME
vs. LOAD CAPACITANCE
2.1
DIFFERENTIAL SKEW
vs. TEMPERATURE
150
100
DIFFERENTIAL SKEW (ps)
50
0
-40 10-15 35 60 85
TEMPERATURE (°C)
60.0
57.5
55.0
52.5
50.0
47.5
45.0
CYCLE-TO-CYCLE JITTER (psp-p)
42.5
40.0
580
t
PHLD
t
MAX9115 toc11
PLHD
DIFFERENTIAL PROPAGATION DELAY
vs. COMMON-MODE VOLTAGE
2.4
2.3
MAX9115 toc09
2.2
t
2.1
2.0
1.9
DIFFERENTIAL PROPAGATION DELAY (ns)
1.8
0.1 1.10.6 1.6 2.1
PLHD
t
PHLD
COMMON-MODE VOLTAGE (V)
CYCLE-TO-CYCLE JITTER
vs. DIFFERENTIAL INPUT VOLTAGE
FALLING EDGE
RISING EDGE
0.1 0.2 0.3 0.4 0.5 0.6
DIFFERENTIAL INPUT VOLTAGE (V)
TRANSITION TIME
vs. SUPPLY VOLTAGE
MAX9115 toc12
MAX9115 toc10
1.8
1.5
1.2
0.9
TRANSITION TIME (ns)
0.6
0.3
52515 35 45 55
LOAD CAPACITANCE (pF)
t
TLH
MAX9115 toc13
540
t
THL
500
TRANSITION TIME (ps)
460
3.0 3.3 3.6
t
THL
t
TLH
SUPPLY VOLTAGE (V)
MAX9115 toc14
MAX9115
Detailed Description
LVDS is intended for point-to-point communication over
a controlled-impedance medium as defined by the
ANSI TIA/EIA-644 and IEEE 1596.3 standards. LVDS
uses a lower voltage swing than other common communication standards, achieving higher data rates with
reduced power consumption while reducing EMI emissions and system susceptibility to noise.
The MAX9115 is a single LVDS line receiver ideal for
applications requiring high data rates, low power, and
low noise. The device accepts an LVDS input and
translates it to an LVTTL/LVCMOS output. The receiver
detects differential signals as low as 50mV and as high
as 1V within an input voltage range of 0 to +2.4V.
The 250mV to 450mV differential output of an LVDS driver is nominally centered around a +1.25V offset. This
offset, coupled with the receiver’s 0 to +2.4V input voltage range, allows an approximate ±1V shift in the signal (as seen by the receiver). This allows for a
difference in ground references of the driver and the
receiver, the common-mode effects of coupled noise,
or both. The LVDS standards specify an input voltage
range of 0 to +2.4V referenced to receiver ground.
Fail-Safe
The fail-safe feature of the MAX9115 sets the output
high and reduces supply current when:
• inputs are open
• inputs are undriven and shorted
• inputs are undriven and terminated
A fail-safe circuit is important because under these
conditions, noise at the input may switch the receiver
and it may appear to the system that data is being
received. Open or undriven terminated input conditions
can occur when a cable is disconnected or cut, or
when an LVDS driver output is in high impedance. A
short condition can occur because of a cable failure.
The fail-safe input network (Figure 1) samples the input
common-mode voltage and compares it to V
CC
- 0.3V
(nominal). When the input is driven to levels specified in
the LVDS standards, the input common-mode voltage
is less than VCC- 0.3V and the fail-safe circuit is not
activated. If the inputs are open or if the inputs are
undriven and shorted or undriven and parallel terminated, there is no input current. In this case, a pullup resistor in the fail-safe circuit pulls both inputs above VCC-
0.3V, activating the fail-safe circuit and forcing the output high.
Applications Information
Power-Supply Bypassing
Bypass VCCwith a high-frequency surface-mount
ceramic 0.01µF capacitor in parallel as close to the
device as possible.
Single LVDS Line Receiver in SC70
6 _______________________________________________________________________________________
Pin Description
Figure 1. Input Fail-Safe Network
Figure 2. Propagation Delay and Transition Time Test Circuit
PIN NAME FUNCTION
1V
2 GND Ground
3 IN- Inverting LVDS Differential Input
4 IN+ Noninverting LVDS Differential Input
5 OUT LVTTL/LVCMOS Output
Power-Supply Input. Bypass VCC to
CC
GND with a 0.01µF ceramic capacitor.
IN+
R
V
CC
R
IN2
VCC - 0.3V
IN1
OUT
R
IN1
GND
IN+
IN-
MAX9115
Rx
MAX9115
OUT
C
L
IN-
PULSE
GENERATOR
*50Ω *50Ω
*50Ω REQUIRED FOR PULSE GENERATOR.
Differential Traces
Input trace characteristics affect the performance of the
MAX9115. Use controlled-impedance PC board traces,
typically 100Ω. Match the termination resistor to this
characteristic impedance.
Eliminate reflections and ensure that noise couples as
common mode by running the differential traces close
together. Reduce skew by matching the electrical
length of the traces. Excessive skew can result in a
degradation of magnetic field cancellation.
Input differential signals should be routed close to each
other to cancel their external magnetic field. Maintain a
constant distance between the differential traces to
avoid discontinuities in differential impedance. Minimize
the number of vias to further prevent impedance discontinuities.
Cables and Connectors
Transmission media should typically have a controlled
differential impedance of 100Ω. Use cables and connectors that have matched differential impedance to
minimize impedance discontinuities.
Avoid the use of unbalanced cables such as ribbon or
simple coaxial cable. Balanced cables such as twisted
pair offer superior signal quality and tend to generate
less EMI due to canceling effects. Balanced cables
tend to pick up noise as common mode, which is
rejected by the LVDS receiver.
Termination
The MAX9115 requires an external termination resistor.
The termination resistor should match the differential
impedance of the transmission line. Termination resistance is typically 100Ω but may range between 90Ω to
132Ω, depending on the characteristic impedance of
the transmission medium.
When using the MAX9115, minimize the distance
between the input termination resistor and the MAX9115
receiver inputs. Use 1% surface-mount resistors.
Board Layout
For LVDS applications, a four-layer PC board that provides separate layers, power, ground, and input/output
signals is recommended. Keep the LVDS input signals
away from the output LVCMOS/LVTTL signal to prevent
coupling (Figure 4). To minimize crosstalk, do not run
the output in parallel with the inputs. Extend the ground
pin trace under the package to the other side between
IN+ and OUT to provide isolation between IN+ and
OUT.
Chip Information
TRANSISTOR COUNT: 201
PROCESS: CMOS
MAX9115
Single LVDS Line Receiver in SC70
_______________________________________________________________________________________ 7
Figure 3. Propagation Delay and Transition-Time Waveforms
Figure 4. Board Layout
V
IN-
V
IN+
V
OUT
COMMON-MODE VOLTAGE: V
DIFFERENTIAL INPUT VOLTAGE: V
VID = 0
t
PLHD
50%
20% 20%
t
TLH
V
ID
80%
= (V
+ V
CM
) / 2
IN+
IN-
= (V
) - (V
ID
)
IN+
IN-
80%
t
PHLD
= 0
V
ID
50%
t
THL
(LVTTL/LVCMOS OUTPUT)
C1
0.01µF
U1: MAX9115
R1, C1 ARE 0402 TYPE
V
CC
GND
IN-
R1
U1
OUT
IN+
(LVDS INPUTS)
V
OH
V
OL
MAX9115
Single LVDS Line Receiver in SC70
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Package Information
SC70, 5L.EPS
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