The MAX8819_ is a complete power solution for MP3
players and other handheld applications. The IC
includes a battery charger, step-down converters, and
WLED power. It features an input current-limit switch to
power the IC from an AC-to-DC adapter or USB port, a
1-cell lithium ion (Li+) or lithium polymer (Li-Poly) charger, three step-down converters, and a step-up converter
with serial step dimming for powering two to six white
LEDs. All power switches for charging and switching the
system load between battery and external power are
included on-chip. No external MOSFETs are required.
The MAX8819C/MAX8819D offer a sequenced powerup/power-down of OUT1, OUT2, and then OUT3.
Maxim’s Smart Power Selector™ makes the best use of
AC-to-DC adapter power or limited USB power. Battery
charge current and input current limit are independently set. Input power not used by the system charges the
battery. Charge current is resistor programmable and
the input current limit can be selected as 100mA,
500mA, or 1A. Automatic input selection switches the
system load from battery to external power. In addition,
on-chip thermal limiting reduces the battery charge rate
to prevent charger overheating.
Applications
MP3 Players
Portable GPS Devices
Low-Power Handheld Products
Cellular Telephones
Digital Cameras
Handheld Instrumentation
PDAs
Features
♦ Smart Power Selector
♦ Operates with No Battery Present
♦ USB/AC Adapter One-Cell Li+ Charger
♦ Three 2MHz Step-Down Converters
= -40°C to +85°C, capacitors as shown in Figure 1, R
CISET
= 3kΩ, unless otherwise noted.) (Note 3)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS
DC, SYS, BAT, CISET, DLIM1, DLIM2, EN123
CEN, EN4, CHG, RST1, FB1, FB2, FB3 to GND....-0.3V to +6V
PV2 to GND...............................................-0.3V to (V
SYS
+ 0.3V)
PV13 to SYS...........................................................-0.3V to +0.3V
PG1, PG2, PG3, PG4 to GND................................-0.3V to +0.3V
COMP4, FB4 to GND ................................-0.3V to (V
SYS
+ 0.3V)
LX4 to PG4 .............................................................-0.3V to +33V
OVP4 to GND .........................................................-0.3V to +33V
LX1, LX2, LX3 Continuous Current (Note 1) .........................1.5A
LX4 Current ................................................................750mA
= -40°C to +85°C, capacitors as shown in Figure 1, R
CISET
= 3kΩ, unless otherwise noted.) (Note 3)
Note 3: Limits are 100% production tested at TA= +25°C. Limits over the operating temperature range are guaranteed through cor-
relation using statistical quality control (SQC) methods.
Note 4: The charger transitions from done to fast-charge mode at this BAT recharge threshold.
Note 5: The charger transitions from fast-charge to top-off mode at this top-off threshold (Figure 2).
Note 6: The maximum output current is guaranteed by correlation to the p-channel current-limit threshold, p-channel on-resistance,
n-channel on-resistance, oscillator frequency, input voltage range, and output voltage range. The parameter is stated for
a 4.7μH inductor with 0.13Ω series resistance. See the
Step-Down Converter Maximum Output Current
section for more
information.
Note 7: The step-down output voltages are 1% high with no load due to the load-line architecture.
Note 8: The skip-mode current threshold is the transition point between fixed-frequency PWM operation and skip-mode operation.
The specification is given in terms of output load current for inductor values shown in the typical application circuit (Figure 1).
Note 9: Line regulation for the step-down converters is measured as ΔV
OUT
/ΔD, where D is the duty cycle (approximately
V
OUT/VIN
).
Note 10: REG2 is disabled by connecting PV2 to ground, decreasing the quiescent current.
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
LED DIMMING CONTROL (EN4)
EN4 Low Shutdown Delayt
EN4 High Enable Delay (Figure 8)t
EN4 Low Timet
EN4 High Timet
RESET (RST)
Reset Trip ThresholdV
Reset Deassert Delay Timet
Reset Glitch Filtert
LOGIC (DLIM1, DLIM2, EN123, EN4, CHG, RST1)
Logic Input-Voltage LowVDC = 4.1V to 5.5V, V
Logic Input-Voltage HighVDC = 4.1V to 5.5V, V
Logic Input Pulldown ResistanceV
Logic Leakage CurrentV
Logic Output Voltage LowI
Logic Output-High Leakage
Current
SHDN
H_INIT
THRST
DRST
GLRST
LO
HI
Voltage from FB1 to GND, V
50mV hysteresis
= 0.4V to 5.5V, CEN, EN123, EN44007601200kΩ
LOGIC
= 0 to 5.5V, DLIM1, DLIM2-1.0+0.001+1.0μA
LOGIC
= 1mA715mV
SINK
V
= 5.5V-1.0+0.001+1.0μA
LOGIC
falling,
FB1
= 2.6V to 5.5V0.4V
SYS
= 2.6V to 5.5V1.2V
SYS
100μs
0.5500μs
0.5μs
0.7650.8580.945V
180200220ms
23.2ms
50μs
MAX8819A–MAX8819D
PMIC with Integrated Chargers and Smart
Power Selector in a 4mm x 4mm TQFN
7EN4REG4 Enable Input and Dimming Control Digital Input
8RST1
9BAT
10SYS
11DC
12CENBattery Charger Enable Input
13FB1
Active-Low, Open-Drain Reset Output. RST1 pulls low to indicate that FB1 is below its regulation
threshold. RST1 goes high 200ms after FB1 reaches its regulation threshold. RST1 is high-impedance
when EN123 is low, and DC is unconnected.
Positive Battery Terminal Connection. Connect BAT to the positive terminal of a single-cell Li+/Li-Poly
battery. Bypass BAT to GND with a 4.7μF ceramic capacitor.
System Supply Output. Bypass SYS to GND with a 10μF ceramic capacitor. When a valid voltage is
present at DC and DLIM[1:2] ≠ 11, V
(MAX8819B/MAX8819D). When the system load (I
75mV (V
BSREG
) below V
, allowing both the external power source and the battery to service SYS.
BAT
SYS is connected to BAT through an internal 70mΩ system load switch when a valid source is not
present at DC.
DC Power Input. DC is capable of delivering 1A to SYS. DC supports both AC adapters and USB
inputs. As shown in Table 1, the DC current limit is controlled by DLIM1 and DLIM2.
Feedback Input for REG1. Connect FB1 to the center of a resistor voltage-divider from the REG1
output capacitors to GND to set the output voltage from 1V to V
is limited to 4.35V (MAX8819A/MAX8819C) or 5.3V
SYS
) exceeds the input current limit, V
SYS
.
SYS
SYS
drops
MAX8819A–MAX8819D
PMIC with Integrated Chargers and Smart
Power Selector in a 4mm x 4mm TQFN
25PV2Power Input for REG2. Connect PV2 to SYS. Bypass PV2 to PG2 with a 4.7μF ceramic capacitor.
26LX2
27PG2REG2 Power Ground
28DLIM2
—EPExposed Pad
Charge Rate Select Input. Connect a resistor from CISET to GND (R
current limit, prequalification-charge current limit, and top-off threshold.
Active-Low, Open-Drain Charge Status Output. CHG pulls low to indicate that the battery is charging.
See Figure 3 for more information.
Inductor Switching Node for REG1. When enabled, LX1 switches between PV13 and PG1 to regulate
the FB1 voltage to 1.0V. When disabled, LX1 is pulled to PG1 by 1kΩ in shutdown.
Power Input for the REG1 and REG3 Converters. Connect PV13 to SYS. Bypass PV13 to PG1 with a
4.7μF ceramic capacitor.
Inductor Switching Node for REG3. When enabled, LX3 switches between PV13 and PG3 to regulate
the FB3 voltage to 1.0V. When disabled, LX3 is pulled to PG3 by a 1kΩ internal resistor.
Input Current-Limit Selection Digital Input 1. Drive high or low according to Table 1 to set the DC input
current limit.
Feedback Input for REG2. Connect FB2 to the center of a resistor voltage-divider from the REG2
output capacitors to GND to set the output voltage from 1V to V
Feedback Input for REG3. Connect FB3 to the center of a resistor voltage-divider from the REG3
output capacitors to GND to set the output voltage from 1V to V
RE G1, RE G2, and RE G3 E nab l e Inp ut. D r i ve E N 123 hi g h to enab l e RE G1, RE G 2, and RE G3. D r i ve E N 123
l ow to d i sab l e RE G 1, RE G2, and RE G 3. The enab l e/d i sab l e seq uenci ng i s show n i n Fi g ur es 6 and 7.
Inductor Switching Node for REG2. When enabled, LX2 switches between PV2 and PG2 to regulate
the FB2 voltage to 1.0V. When disabled, LX2 is pulled to PG2 by a 1kΩ internal resistor.
Input Current-Limit Selection Digital Input 2. Drive high or low according to Table 1 to set the DC input
current limit.
The MAX8819_ is a complete power solution that
includes a battery charger, step-down converters, and
WLED power. As shown in Figure 1, the IC integrates a
DC power input, Li+/Li-Poly battery charger, three stepdown converters, and one step-up converter for powering
white LEDs. All three step-down converters feature
adjustable output voltages set with external resistors.
The MAX8819_ has one external power input that connects to either an AC-to-DC adapter or USB port. Logic
inputs DLIM1 and DLIM2 select the desired input current limit.
In addition to charging the battery, the IC supplies
power to the system through the SYS output. The
charging current is provided from SYS so that the set
input current limit controls the total SYS current, this is
the sum of the system load current and the batterycharging current.
In some instances, there may not be enough DC input
current to supply peak system loads. The Smart Power
Selector circuitry offers flexible power distribution from
an AC-to-DC adapter or USB source to the battery and
system load. The battery is charged with any available
power not used by the system load. If a system load
peak exceeds the input current limit, supplemental current is taken from the battery. Thermal limiting prevents
overheating by reducing power drawn from the input
source. In the past, it might have been necessary to
reduce system functionality to limit current drain when a
USB source is connected. However, with the
MAX8819_, this is no longer the case. When the DC or
USB source hits its limit, the battery supplies supplemental current to maintain the load.
The IC features overvoltage protection. Part of this protection is a 4.35V (MAX8819A/MAX8819C) or 5.3V
(MAX8819B/MAX8819D) voltage limiter at SYS. If DC
exceeds the overvoltage threshold of 5.88V (V
OVLO_DC
),
the input limiter disconnects SYS from DC, but batterypowered operation of all regulators is still allowed.
Input Limiter
The Smart Power Selector seamlessly distributes power
between the current-limited external input (DC), the battery (BAT), and the system load (SYS). The basic functions performed are:
With both an external power supply (DC) and battery
(BAT) connected:
• When the system load requirements are less than
the input current limit, the battery is charged with
residual power from the input.
• When the system load requirements exceed the
input current limit, the battery supplies supplemental current to the load through the internal system load switch.
• When the battery is connected and there is no
external power input, the system (SYS) is powered
from the battery.
• When an external power input is connected and
there is no battery, the system (SYS) is powered
from the external power input.
A thermal-limiting circuit reduces the battery charge
rate and external power source current to prevent the
MAX8819_ from overheating.
System Load Switch
An internal 70mΩ MOSFET connects SYS to BAT when
no voltage source is available at DC. When an external
source is detected at DC, this switch opens and SYS is
powered from the valid input source through the Smart
Power Selector.
When the system load requirements exceed the input
current limit, the battery supplies supplemental current
to the load through the internal system load switch. If
the system load continuously exceeds the input current
limit, the battery does not charge, even though external
power is connected. This is not expected to occur in
most cases because high loads usually occur only in
short peaks. During these peaks, battery energy is
used, but at all other times the battery charges.
DC Power Input (DC, DLIM1, DLIM2)
DC is a current-limited power input that supplies the
system (SYS) up to 1A. The DC to SYS switch is a linear
regulator designed to operate in dropout. This linear
regulator prevents the SYS voltage from exceeding
5.3V for the MAX8819B/MAX8819D or 4.35V for the
MAX8819A/MAX8819C. As shown in Table 1, DC supports four different current limits that are set with the
DLIM1 and DLIM2 digital inputs. These current limits
are ideally suited for use with AC-to-DC wall adapters
and USB power. The operating voltage range for DC is
4.1V to 5.5V, but it can tolerate up to 6V without damage. When the DC input voltage is below the undervoltage threshold (4V), it is considered invalid. When the
DC voltage is below the battery voltage it is considered
invalid. The DC power input is disconnected when the
DC voltage is invalid. Bypass DC to ground with at least
a 4.7μF capacitor.
Four current settings are provided based upon the settings of DLIM1 and DLIM2, see Table 1. DLIM1 and
DLIM2 are deglitched. This deglitching prevents the
problem of major carry transitions momentarily entering
the suspend state.
Figure 2 shows the typical Li+/Li-Poly charge profile for
the MAX8819_, and Figure 3 shows the battery charger
state diagram.
With a valid DC input that is not suspended, the battery
charger initiates a charge cycle once CEN is driven
high. It first detects the battery voltage. If the battery
voltage is less than the prequalification threshold
(3.0V), the charger enters prequalification mode and
charges the battery at 10% of the maximum fast-charge
current while deeply discharged. Once the battery voltage rises to 3.0V, the charger transitions to fast-charge
mode and applies the maximum charge current. As
charging continues, the battery voltage rises until it
Figure 2. Li+/Li-Poly Charge Profile
BATTERY VOLTAGEBATTERY CHARGE CURRENTCHG
V
BATREG
V
BATPRQ
I
CHGMAX
PREQUALIFICATION
I
PQ
FAST-CHARGE
(CONSTANT CURRENT)
FAST-CHARGE
(CONSTANT VOLTAGE)
TOP-OFF
DONE
I
TO
0
HIGH
IMPEDANCE
LOW
MAX8819A–MAX8819D
PMIC with Integrated Chargers and Smart
Power Selector in a 4mm x 4mm TQFN
approaches the battery regulation voltage (4.2V typ)
where charge current starts tapering down. When
charge current decreases to 10% of the maximum fastcharge current, the charger enters a 33min top-off state
and then charging stops. If the battery voltage subsequently drops 100mV below the battery regulation voltage, charging restarts and the timers reset.
The battery charge rate is set by several factors:
• The battery charger is enabled by the processor driving the CEN input high. A valid input must be available at DC. The battery charger is disabled without
a valid input at DC or by driving CEN low.
• The system current has priority over the battery
charger; the battery charger automatically reduces
its charge current to maintain the input current limit
while still providing the system current (I
SYS
).
• The input current limit is tapered down from full current to zero current when the die temperature transitions from +100°C to +120°C. Since I
SYS
has priority
over the battery charge current, the battery charge
current tapers down before I
SYS
. The overall result is
self-regulation of die temperature (see the
Thermal
Limiting and Overload Protection
section for more
information).
• The battery charger stops charging in done mode
as shown in Figures 2 and 3.
Charge Status Output (CHG)
CHG is an open-drain, active-low output that indicates
charger status. As shown in Figures 2 and 3, CHG is
low when the charger is in its prequalification or fastcharge states. When a timer count is exceeded in
either state, CHG indicates the fault by blinking at a
2Hz rate and remains in that state until the charger is
reset by CEN going low, removal of DC or setting
DLIM[1:2] = 11.
When the MAX8819_ is used with a microprocessor
(μP), connect a pullup resistor between CHG and the
system logic voltage to indicate charge status to the
μP. Alternatively, CHG sinks up to 20mA for an LED
charge indicator.
If the charge status output feature is not required, connect CHG to ground or leave unconnected.
Charge Timer
As shown in Figure 3, a fault timer prevents the battery
from charging indefinitely. In prequalification mode, the
charge time is internally fixed to 33min.
t
PREQUAL
= 33min
In fast-charge mode, the charge timer is internally fixed
to 660min.
t
FSTCHG
= 660min
When the charger exits fast-charge mode, a fixed
33min top-off mode is entered:
t
TOP-OFF
= 33min
While in the constant-current fast-charge mode (Figure
2), if the MAX8819_ reduces the battery charge current
due to its internal die temperature or large system
loads, it slows down the charge timer. This feature eliminates nuisance charge timer faults. When the battery
charge current is between 100% and 50% of its programmed fast-charge level, the fast-charge timer runs
at full speed. When the battery charge current is
between 50% and 20% programmed fast-charge level,
the fast-charge timer is slowed by 2x. Similarly, when
the battery charge current is below 20% of the programmed fast-charge level, the fast-charge timer is
Figure 4. Calculated Charge Currents vs. R
CISET
Table 2. Calculated Charge Currents vs.
R
CISET
FAST-CHARGE, PREQUALIFICATION, AND TOP-OFF
CURRENT vs. CHARGE-SETTING RESISTOR
10,000
I
1000
100
CURRENT (mA)
10
1
05101520
CHGMAX
I
PREQUAL, ITOP-OFF
R
CISET
(kΩ)
I
R
(kΩ)
CISET
3.011000100100
4.027467575
4.996016060
6.044975050
6.984304343
8.063723737
9.093303333
103003030
112732727
12.12482525
132312323
142142121
152002020
CHGMAX
(mA)
I
(mA)I
PQ
TO
(mA)
MAX8819A–MAX8819D
PMIC with Integrated Chargers and Smart
Power Selector in a 4mm x 4mm TQFN
paused. The fast-charge timer is not slowed or paused
when the charger is in the constant voltage portion of
its fast-charge mode (Figure 2) where the charge current reduces normally.
Charge Current (CISET)
As shown in Table 2 and Figure 4, a resistor from CISET
to ground (R
CISET
) sets the maximum fast-charge cur-
rent (I
CHGMAX
), the charge current in prequalification
mode (I
PREQUAL
), and the top-off threshold (I
TOP-OFF
).
The MAX8819_ supports values of I
CHGMAX
from 200mA
to 1000mA. Select the R
CISET
as follows:
Determine I
CHGMAX
by considering the characteristics
of the battery. It is not necessary to limit the charge current based on the capabilities of the expected AC-toDC adapter or USB/DC input current limit, the system
load, or thermal limitations of the PCB. The IC automatically lowers the charging current as necessary to
accommodate for these factors.
For the selected value of R
CISET
, calculate I
CHGMAX
,
I
PREQUAL
, and I
TOP-OFF
as follows:
Step-Down Converters
(REG1, REG2, REG3)
REG1, REG2, and REG3 are high-efficiency, 2MHz current-mode step-down converters with adjustable outputs.
REG1 is designed to deliver 400mA for the MAX8819A/
MAX8819B and 550mA for the MAX8819C/MAX8819D.
REG2 and REG3 are designed to deliver 300mA for the
MAX8819A/MAX8819B and 500mA for the MAX8819C/
MAX8819D.
The step-down regulator power inputs (PV_) must be
connected to SYS. The step-down regulators operate
with V
SYS
from 2.6V to 5.5V. Undervoltage lockout
ensures that the step-down regulators do not operate
with SYS below 2.55V (max).
See the
Step-Down Converter Enable/Disable (EN123)
and Sequencing
section for how to enable and disable
the step-down converters. When enabled, the
MAX8819_ gradually ramps each output up during a
2.6ms soft-start time. When enabled, the MAX8819C/
MAX8819D sequentially ramps up each output. Softstart eliminates input current surges when regulators
are enabled.
See the
Step-Down Control Scheme
section for informa-
tion about the step-down converters control scheme.
The IC uses external resistor-dividers to set the stepdown output voltages between 1V and V
SYS
. Use at
least 10μA of bias current in these dividers to ensure no
change in the stability of the closed-loop system. To set
the output voltage, select a value for the resistor connected between FB_ and GND (R
FBL
). The recommended value is 100kΩ. Next, calculate the value of the
resistor connected from FB_ to the output (R
FBH
):
REG1, REG2, and REG3 are optimized for high, medium, and low output voltages, respectively. The highest
overall efficiency occurs with V1 set to the highest output voltage and V3 set to the lowest output voltage.
REG2 can be disabled by connecting PV2 to GND.
Step-Down Control Scheme
At light load, the step-down converter switches only as
needed to supply the load. This improves light-load efficiency. At higher load currents (~80mA), the step-down
converter transitions to fixed 2MHz switching.
Step-Down Dropout and Minimum Duty Cycle
All of the step-down regulators are capable of operating in 100% duty-cycle dropout, however, REG1 has
been optimized for this mode of operation. During
100% duty-cycle operation, the high-side p-channel
MOSFET turns on constantly, connecting the input to
the output through the inductor. The dropout voltage
(VDO) is calculated as follows:
where:
R
P
= p-channel power switch R
DS(ON)
R
LSR
= external inductor ESR
The minimum duty cycle for all step-down regulators is
12.5% (typ), allowing a regulation voltage as low as 1V
over the full SYS operating range. REG3 is optimized
for low duty-cycle operation.
Step-Down Input Capacitor
The input capacitor in a step-down converter reduces
current peaks drawn from the power source and
reduces switching noise in the controller. The impedance of the input capacitor at the switching frequency
must be less than that of the source impedance of the
supply so that high-frequency switching currents do not
pass through the input source.
The step-down regulator power inputs are critical discontinuous current paths that require careful bypassing. In the PCB layout, place the step-down converter
input bypass capacitors as close as possible to each
pair of switching converter power input pins (PV_ to
PG_) to minimize parasitic inductance. If making connections to these capacitors through vias, be sure to
use multiple vias to ensure that the layout does not
insert excess inductance or resistance between the
bypass capacitor and the power pins.
The input capacitor must meet the input ripple current
requirement imposed by the step-down converter.
Ceramic capacitors are preferred due to their low ESR
and resilience to power-up surge currents. Choose the
input capacitor so that its temperature rise due to input
ripple-current does not exceed approximately +10°C.
For a step-down DC-DC converter, the maximum input
ripple current is half of the output current. This maximum input ripple current occurs when the step-down
converter operates at 50% duty factor (VIN= 2 x V
OUT
).
Bypass each step-down converter input with a 4.7μF
ceramic capacitor from PV_ to PG_. Use capacitors that
maintain their capacitance over temperature and DC
bias. Ceramic capacitors with an X7R or X5R temperature characteristic generally perform well. The capacitor
voltage rating should be 6.3V or greater.
Step-Down Output Capacitors
The output capacitance keeps output ripple small and
ensures control-loop stability. The output capacitor
must have low impedance at the switching frequency.
Ceramic, polymer, and tantalum capacitors are suitable
with ceramic exhibiting the lowest ESR and lowest highfrequency impedance. The MAX8819A/MAX8819B
require at least 10μF of output capacitance. The
MAX8819C/MAX8819D require ar least 22μF of output
capacitance.
As the case sizes of ceramic surface-mount capacitors
decreases, their capacitance vs. DC bias voltage characteristic becomes poor. Due to this characteristic, it is
possible for 0805 capacitors to perform well while 0603
capacitors of the same value may not. The MAX8819A/
MAX8819B require a nominal output capacitance of
10μF, however, after their DC bias voltage derating, the
output capacitance must be at least 7.5μF.
Step-Down Inductor
Choose the step-down converter inductance to be
4.7μH. The minimum recommended saturation current
requirement is 700mA. In PWM mode, the peak inductor currents are equal to the load current plus one half
of the inductor ripple current. See Table 3 for suggested
inductors.
Table 3. Suggested Inductors
MANUFACTURERSERIES
Sumida
Taiyo Yuden
TDK
TOKODE2812C4.71308803.0 x 2.8 x 1.2 = (10.8mm)
FDK
CDRH2D11HP4.71907503.0 x 3.0 x 1.2 = (10.8mm)
CDH2D094.72187003.0 x 3.0 x 1.0= (9.0mm)
NR30124.71307703.0 x 3.0 x 1.2 = (10.8mm)
NR30104.71907503.0 x 3.0 x 1.0 = (9.0mm)
VLF30124.71607402.8 x 2.6 x 1.2 = (8.7mm)
VLF30104.72407002.8 x 2.6 x 1.0 = (7.3mm)
MIPF25204.711011002.5 x 2.0 x 1.0 = (5mm)
MIPF20164.71609002.0 x 1.6 x 1.0 = (3.2mm)
INDUCTANCE
(µH)
ESR
(mΩ)
CURRENT RATING
(mA)
DIMENSIONS
(mm)
3
3
3
3
3
3
3
3
3
MAX8819A–MAX8819D
PMIC with Integrated Chargers and Smart
Power Selector in a 4mm x 4mm TQFN
The peak-to-peak inductor ripple current during PWM
operation is calculated as follows:
where f
S
is the 2MHz switching frequency.
The peak inductor current during PWM operation is calculated as follows:
Step-Down Converter Maximum Output Current
The maximum regulated output current from a step-down
converter is ultimately determined by the p-channel peak
current limit (IPK). The calculation follows:
As the load current is increased beyond this point, the
output voltage sags and the converter goes out of regulation because the inductor current cannot increase
above the p-channel peak current limit.
Step-Down Converter Short-Circuit Protection
The step-down converter implements short-circuit protection by monitoring the feedback voltage, V
FB_
. After soft-
start, if V
FB_
drops below 0.23V, the converter reduces its
switching frequency to fS/3. The inductor current still
reaches the p-channel peak current limit, however, at
one-third the frequency. Therefore, the output and input
currents are reduced to approximately one-third of the
maximum value in response to an output short circuit to
ground. When the short is removed, the inductor current
raises the voltage on the output capacitor and the stepdown converter resumes normal operation.
REG1 Reset (RST1)
RST1 is an active-low, open-drain output that pulls low
to indicate that FB1 is below its regulation threshold.
RST1 goes high 200ms after FB1 reaches its regulation
threshold. RST1 is high-impedance when EN123 is
high. See Figures 6 and 7.
A 50μs blanking delay is provided when FB1 is falling,
so that RST1 does not glitch if the REG1 output voltage
is dynamically adjusted by altering the resistors in its
feedback network.
Figure 5b. MAX8819C/MAX8819D Enable Logic
SYS
EN123
EN4
+
SYSOK
2.5V RISING
100mV HYST.
DIE TEMP
+165°C
DC
6.0V RISING
400mV HYST.
4.0V RISING
500mV HYST.
-
READY
+
+
-
-
+
DT165
-
DCOVLO
DCPOK
DCUVLO
2MHz
OSC
BIAS
AND
REF
64 CYCLE
DELAY
(32μs)
READY
REGON
REGON
MAX8819C
MAX8819D
SOFT-START
REG1
EN
SOFT-START
REG2
EN
SOFT-START
REG3
EN
SOFT-START
REG4
ENOK
OK
OK
OK
REG1OK
REG2OK
REG3OK
REG4OK
MAX8819A–MAX8819D
PMIC with Integrated Chargers and Smart
Power Selector in a 4mm x 4mm TQFN
Each MAX8819_ step-down converter (REG1, REG2,
REG3) has an internal 1kΩ resistor that discharges the
output capacitor when the converter is off. The discharge resistors ensure that the load circuitry powers
down completely. The internal discharge resistors are
connected when a converter is disabled and when the
device is in UVLO with an input voltage greater than
1.0V. With an input voltage less than 1.0V the internal
discharge resistors are not activated.
Step-Down Converter Enable/Disable (EN123)
and Sequencing
Figure 5a shows the MAX8819A/MAX8819B enable and
disable logic. Figure 5b shows MAX8819C/MAX8819D
enable/disable logic. Figure 6 shows an example of
enable and disable waveforms for the MAX8819A/
MAX8819B.
Figure 6 notes:
1) The device is off with no external power applied to
DC. The system voltage (V
SYS
) is equal to the bat-
tery voltage (V
BAT
).
2) An external supply is applied to DC that causes the
step-down converter to power up after the DC-toSYS soft-start time (t
SS-D-S
). When the DC input is
valid and DLIM[1:2] ≠ 11, V
SYS
increases.
3) When V1 reaches the reset trip threshold (V
THRST
),
the reset deassert delay timer starts. When the reset
deassert delay timer expires (t
DRST1
), RST1 goes
high-impedance. If RST1 is connected to the RESET
Figure 6. MAX8819A/MAX8819B Enable/Disable Waveforms Example
input of the system μP, the processor can begin its
boot-up sequence up at this time.
4) During the μP’s boot-up sequence, it asserts EN123
to keep the step-down converters enabled, even if
DC is removed.
5) After the μP has booted, it asserts EN4 to turn on the
display’s backlight.
6) CEN is asserted by the μP to start a charge cycle.
7) The external supply is removed from DC and V
SYS
falls. The converters remain enabled because the μP
has asserted EN123 and EN4, but the battery charging current drops to zero even though CEN is still
asserted. CHG goes high impedance.
8) System is turned off by deasserting EN123, EN4, and
CEN; RST1 goes low to reset the μP.
Figure 7 notes:
1) The MAX8819C/MAX8819D are off with no external
power applied to DC. The system voltage (V
SYS
) is
equal to the battery voltage (V
BAT
).
2) An external supply is applied to DC that causes the
step-down regulator to power up after the DC-toSYS soft-start time (t
SS-D-S
). When the DC input is
valid and DC is not suspended, V
SYS
rises.
3) EN123 is pulled high to start the OUT3, OUT2, and
OUT1 power-up sequence. When OUT1 reaches the
reset trip threshold (V
THRST
), the reset deassert
delay timer starts. When the reset deassert delay
timer expires (t
DRST1
200ms typ.), RST1 goes high-
impedance. If RST1 is connected to the RESET input
of the system μP, the processor can begin its bootup sequence at this time.
Figure 7. MAX8819C/MAX8819D Enable/Disable Waveforms Example
NOTES
V
V
V
V
V
V
V
V
EN123
OUT3
OUT2
OUT1
RST1
V
OUT4
DC
SYS
EN4
12
V
BAT
t
SS-D-S
34
V
< V
< V
BAT
SYS
DC
2.6ms
2.6ms
2.6ms
V
- V
SYS
D
5
HIGH IMPEDANCE
200ms
t
SS4
6
V
BAT
7
V
- V
SYS
D
V
CEN
V
CHG
t
SS_CHG
MAX8819A–MAX8819D
PMIC with Integrated Chargers and Smart
Power Selector in a 4mm x 4mm TQFN
5) CEN is asserted by the μP to start a charge cycle.
6) The external supply is removed from DC and V
SYS
falls. The regulators remain enabled because EN123
and EN4 are asserted, but the battery charging current drops to zero even though CEN is still asserted.
CHG goes high-impedance.
7) System is turned off by deasserting EN123, EN4,
and CEN. OUT1, OUT2, and OUT3 power down in
the opposite order of power-up. RST1 goes low to
reset the μP.
Step-Up Converter (REG4)
The step-up converter (REG4) operates by regulating
the voltage at FB4 to 0.5V. REG4 operates from the
system voltage (V
SYS
); this voltage can vary from 2.6V to
4.35V (MAX8819A/MAX8819C) or 5.3V (MAX8819B/
MAX8819D). The 1MHz switching frequency allows for
tiny external components. The step-up converter control
scheme optimizes the efficiency while achieving low EMI
and low input ripple.
REG4 WLED Driver Configuration
Figure 1 shows that REG4 is configured as a white light
emitting diodes (WLED) driver, typically used to drive
up to six devices with an output voltage up to 24V. The
full-scale current is set by resistor R1, according to the
following relationship:
EN4 enables REG4, disables REG4, and adjusts the voltage on FB4 in 32 linear steps. If current adjustment is not
required, EN4 acts as a simple enable/disable controller.
Driving EN4 high for at least 100μs powers up REG4 and
sets V
FB4
to 0.5V. Pulling EN4 low for at least 2ms dis-
ables REG4. To adjust V
FB4
, apply pulses as shown in
Figure 8. Dim the WLEDs by pulsing EN4 low (500ns to
500μs pulse width). Each pulse reduces the LED current
by 1/32. Note: When REG4 is disabled, OUT4 is equal to
V
SYS
minus the drop from the catch diode.
In the event that the load (typically WLEDs) opens,
V
OUT4
rises quickly until it reaches the overvoltage protection threshold (typically 25V). When this occurs,
REG4 stops switching and latches off until EN4 is reset
low for at least 2ms.
Step-Up Converter Inductor Selection
The WLED boost converter switches at 1MHz, allowing
the use of a small inductor. A 10μH inductance value is
recommended for most applications. Smaller inductances require less PCB space.
Use inductors with a ferrite core or equivalent.
Powdered iron cores are not recommended for use at
high-switching frequencies. The inductor’s saturation
current rating should preferably exceed the REG4
n-channel current limit of 700mA. Choose an inductor
with a DC resistance less than 300mΩ to maintain high
efficiency. Table 4 lists recommended inductors.
Step-Up Converter Diode Selection
The REG4 diode must be fast enough to support the
switching frequency (1MHz). Schottky diodes, such as
Central Semiconductor’s CMHSH5-4 or ON Semiconductor’s MBR0530L, are recommended. Make sure that
the diode’s peak-current rating matches or exceeds the
700mA REG4 n-channel current limit. The diode’s average current rating should match or exceed the output
current. The diode’s reverse breakdown voltage must
exceed the voltage from the converter’s output to
ground. Schottky diodes are preferred due to their low
forward voltage, however, ultra high-speed silicon rectifiers are also acceptable.
Step-Up Converter Output Capacitor Selection
For most applications, a 0.1μF ceramic output filter
capacitor is suitable. Choose a voltage rating double
the maximum output voltage to minimize the effect of
the voltage coefficient on decreasing the effective
capacitance. To ensure stability over a wide temperature range, ceramic capacitors with an X5R or X7R
dielectric are recommended. Place these capacitors as
close as possible to the IC.
Soft-Start/Inrush Current
The MAX8819_ implements soft-start on many levels to
control inrush current to avoid collapsing supply voltages, and to fully comply with the USB 2.0 specifications. All DC and charging functions implement soft-start.
The DC node only requires 4.7μF of input capacitance.
Furthermore, all regulators implement soft-start to avoid
transient overload of power inputs.
Undervoltage and Overvoltage Conditions
DC UVLO
DC undervoltage lockout (UVLO) prevents an input supply from being used when its voltage is below the operating range. When the voltage from DC to GND (VDC) is
less than the DC UVLO threshold (4.0V, typ), the DC
input is disconnected from SYS, the battery charger is
disabled and CHG is high impedance. BAT is connected
to SYS through the internal system load switch in DC
UVLO mode, allowing the battery to power the SYS
node. REG1–REG4 and the LED current sinks are
allowed to operate from the battery in DC UVLO mode.
DC OVLO
DC overvoltage lockout (OVLO) is a fail-safe mechanism and prevents an input supply from being used
when its voltage exceeds the operating range. The
absolute maximum ratings state that DC withstands
voltages up to 6V. Systems must be designed so that
DC never exceeds 6V (transient and steady-state). If
the voltage from DC to GND (VDC) should exceed the
DC OVLO threshold (5.9V typ) during a fault, the DC
input is disconnected from SYS, the battery charger is
disabled, and CHG is high impedance. BAT is connected to SYS through the internal system load switch in DC
OVLO mode, allowing the battery to power SYS through
the internal system load switch in DC OVLO mode.
REG1–REG4 are allowed to operate from the battery in
DC OVLO mode. Normal operation resumes when V
DC
falls within its normal operating range.
SYS UVLO
SYS undervoltage lockout (UVLO) prevents the regulators from being used when the input voltage is below
the operating range. When the voltage from SYS to
GND (V
SYS
) is less than the SYS UVLO threshold (2.5V,
typ), REG1–REG4, the LED current sinks, and the battery charger are disabled. Additionally, CHG, is high
impedance and RST1 is asserted.
Thermal Limiting and Overload Protection
Smart Power Selector Thermal-Overload Protection
The IC reduces the DC current limit by 5%/°C when the
die temperature exceeds +100°C. The system load
(I
SYS
) has priority over the charger current, so input
MAX8819A–MAX8819D
PMIC with Integrated Chargers and Smart
Power Selector in a 4mm x 4mm TQFN
current is first reduced by lowering charge current. If
the junction temperature still reaches +120°C in spite of
charge current reduction, no input current is drawn
from DC; the battery supplies the entire load and SYS is
regulated 70mV below BAT.
Regulator Thermal-Overload Shutdown
The IC disables all regulator outputs and the battery
charger when the junction temperature rises above
+165°C, allowing the device to cool. When the junction
temperature cools by approximately 15°C the regulators and charger resume the state indicated by the
enable input (EN123, EN4, and CEN) by repeating their
soft-start sequence. Please note that this thermal-overload shutdown is a fail-safe mechanism; proper thermal
design should ensure that the junction temperature of
the MAX8819_ never exceeds the absolute maximum
rating of +150°C.
Applications Information
Dynamic Output Voltage Adjustment for
Step-Down Converters
Dynamic output voltage adjustment can be implemented for the step-down converter by adding a resistor
and a switch from FB_ to GND. See Figure 9.
To calculate the resistor-divider, start with the lower
voltage desired and calculate the resistor-divider using
RTand RBonly. Setting RB= 100kΩ is acceptable. Use
the following equation to calculate RT:
where V
OUTL
is the desired lower output voltage and
VFBis the feedback regulation voltage, 1V (typ).
R
D
is calculated using the higher set voltage and the
following equations assuming the switch resistance is
negligible:
where R
PAR
is the parallel resistance of RBand RD,
V
OUTH
is the higher set voltage, and VFBis the feed-
back regulation voltage, 1V (typ).
For example, if V
OUTL
= 3V, V
OUTH
= 3.3V, RB=
100kΩ, then:
R
T
= 100kΩ x ((3V/1V) - 1) = 200kΩ
R
PAR
= 200kΩ/((3.3V/1V) - 1) = 86.96kΩ
RD= 1/((1/86.96kΩ) - (1/100kΩ)) = 666.7kΩ
Choose RD= 665kΩ as the closest standard 1% value.
CH1 = gate drive to switch
CH2 = V1, 1V offset; 3V to 3.3V to 3V, 10Ω load
CH3 = RST1
The scope plot (Figure 10) shows V1 switching from 3V
to 3.3V to 3V with the resistor values of the example.
When the switch is turned on, V1 slews from 3V to 3.3V
in about 20μs, which is less than the 50μs RST1 de-
glitch filter, and therefore, RST1 does not trip. When the
switch is turned off, V1 soars to about 3.35V due to the
energy in the inductor. Since V1 is above the regulation
voltage, REG1 skips until V1 decays to the regulation
voltage. The decay rate is determined by the output
capacitance and the load. In this example, the output
capacitance is 10μF and the load is 10Ω, so the time
Figure 9. Dynamic Output Voltage Control
Figure 10. Dynamic Voltage Adjustment with Example Values
OUT_
GATE DRIVE
TO SWITCH
RST1
3.35V
3.3V
3V
V1
100μs/div
FB_
R
T
R
B
R
D
5V/div
0V
500mV/div
3V
4.2V
2V/div
⎛
V
⎜
⎝
OUTL
V
RR
=×−
TB
FB
⎞
1
⎟
⎠
R
T
=
V
OUTH
−
V
FB
1
11
−
PARRB
1
R
PAR
=
R
D
RR
MAX8819A–MAX8819D
PMIC with Integrated Chargers and Smart
Power Selector in a 4mm x 4mm TQFN
constant is R x C = 100μs, and the output voltage
decays to within 1% of final value in about 500μs.
PCB Layout and Routing
Good printed circuit board (PCB) layout is necessary to
achieve optimal performance. Refer to the MAX8819A
Evaluation Kit for Maxim’s recommended layout.
Use the following guidelines for the best results:
• The LX_ rapidly switches between PV_ and PG_.
Minimize stray capacitance on LX_ to maintain high
efficiency.
• Keep the FB_ node away from noise sources such
as the inductor.
• The exposed pad (EP) is the main path for heat to
exit the IC. Connect EP to the ground plane with
thermal vias to allow heat to dissipate from the
device.
• Use short and wide traces for high-current and discontinuous current paths.
• The step-down converter power inputs are critical
discontinuous current paths that require careful
bypassing. Place the step-down converter input
bypass capacitor as close as possible to the PV_
and PG_ pins.
• Minimize the area of the loops formed by the stepdown converters’ dynamic switching currents.
Package Marking
The top of the MAX8819_ package is laser etched as
shown in Figure 11:
“8819_ETI” is the product identification code. The full
part number is MAX8819_ETI; however, in this case, the
“MAX” prefix is omitted due to space limitations. The “_”
corresponds to the “A” or “B” version.
“yww” is a date code. “y” is the last number in the
Gregorian calendar year. “ww” is the week number in
the Gregorian calendar. For example:
• “801” is the first week of 2008; the week of
January 1st, 2008.
• “052” is the fifty-second week of 2010; the week of
December 27th, 2010.
• “aaaa” is an assembly code and lot code.
• “+” denotes lead-free packaging and marks the
pin 1 location.
Figure 11. Package Marking Example
MAX8819A
MAX8819B
MAX8819C
MAX8819D
TOP VIEW
26
27
25
24
10
9
11
FB4
PG4
LX4
GND
EN4
12
COMP4
PG3
PV13
LX1
DLIM1
PG1
CHG
12
PV2
4567
20211917 16 15
LX2
PG2
CEN
DC
SYS
BAT
OVP4
LX3
3
18
28
8
DLIM2
RST1
EN123
23
13
FB1
FB3
22
14
CISET
FB2
+
EXPOSED PADDLE (EP)
Pin Configuration
Chip Information
PROCESS: S45T
PACKAGE TYPEPACKAGE CODEDOCUMENT NO.
28 TQFN-EPT2844+1
21-0139
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages
.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________