General Description
The MAX8643A high-efficiency switching regulator
delivers up to 3A load current at output voltages from
0.6V to (0.9 x V
IN
).The IC operates from 2.35V to 3.6V,
making it ideal for on-board point-of-load and postregulation applications. Total output error is less than ±1%
over load, line, and temperature.
The MAX8643A features fixed-frequency PWM mode
operation with a switching frequency range of 500kHz
to 2MHz set by an external resistor. High-frequency
operation allows for an all-ceramic capacitor design.
The high operating frequency also allows for small-size
external components.
The low-resistance on-chip nMOS switches ensure high
efficiency at heavy loads while minimizing critical inductances, making the layout a much simpler task with
respect to discrete solutions. Following a simple layout
and footprint ensures first-pass success in new designs.
The MAX8643A comes with a high-bandwidth (>14MHz)
voltage-error amplifier. The voltage-mode control architecture and the voltage-error amplifier permit a type III
compensation scheme to be utilized to achieve maximum loop bandwidth, up to 20% of the switching frequency. High loop bandwidth provides fast transient
response, resulting in less required output capacitance
and allowing for all-ceramic capacitor designs.
The MAX8643A provides two tri-state logic inputs to
select one of nine preset output voltages. The preset
output voltages allow customers to achieve ±1% output-voltage accuracy without using expensive 0.1%
resistors. In addition, the output voltage can be set to
any customer value by either using two external resistors at the feedback with 0.6V internal reference or
applying an external reference voltage to the REFIN
input. The MAX8643A offers programmable soft-start
time using one capacitor to reduce input inrush current.
The MAX8643A is available in a lead-free, 24-pin, 4mm
x 4mm thin QFN package.
Applications
POLs
ASIC/CPU/DSP Core and I/O Voltages
DDR Power Supplies
Base-Station Power Supplies
Telecom and Networking Power Supplies
RAID Control Power Supplies
Features
o Internal 37mΩ R
DS(ON)
MOSFETs
o Continuous 3A Output Current
o ±1% Output Accuracy Over Load, Line,
and Temperature
o Operates from 2.35V to 3.6V Supply
o Adjustable Output from 0.6V to (0.9 x VIN)
o Soft-Start Reduces Inrush Supply Current
o 500kHz to 2MHz Adjustable Switching Frequency
o Compatible with Ceramic, Polymer, and
Electrolytic Output Capacitors
o VID-Selectable Output Voltages
0.6, 0.7, 0.8, 1.0, 1.2, 1.5, 1.8, 2.0, and 2.5V
o Fully Protected Against Overcurrent
and Overtemperature
o Safe-Start into Prebiased Output
o Lead-Free, 24-Pin, 4mm x 4mm
Thin QFN Package
MAX8643A
3A, 2MHz Step-Down Regulator
with Integrated Switches
________________________________________________________________
Maxim Integrated Products
1
Ordering Information
19-0767; Rev 0; 3/07
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
+
Denotes a lead-free package.
*
EP = Exposed pad.
Pin Configuration appears at end of data sheet.
OUTPUT
1.8V, 3A
INPUT
2.4V, 3.6V
BST
LX
OUT
IN
EN
V
DD
CTL1
CTL2
PGND
FB
V
DD
COMP
PWRGD
FREQ
REFIN
SS
GND
PREBIAS
MAX8643A
Typical Operating Circuit
PART
MAX8643AETG+
TEMP
RANGE
-40°C to
+85°C
PIN-PACKAGE
24 Thin QFN
4mm x 4mm
PACKAGE
CODE
T2444-4
MAX8643A
3A, 2MHz Step-Down Regulator
with Integrated Switches
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VIN= VDD= 3.3V, VFB= 0.5V, TA = -40°C to +85°C. Typical values are at TA= +25°C, circuit of Figure 1, unless otherwise noted.) (Note 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
IN, VDD, PWRGD to GND ......................................-0.3V to +4.5V
COMP, FB, REFIN, OUT,
CTL_, EN, SS, FREQ to GND...................-0.3V to (V
DD
+ 0.3V)
LX Current (Note 1) .....................................................-4A to +4A
BST to LX..................................................................-0.3V to +4V
PGND to GND .......................................................-0.3V to +0.3V
Continuous Power Dissipation (T
A
= +70°C)
24-Pin TQFN-EP
(derated 27.8mW/°C above +70°C)........................2222.2mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Note 1: LX has internal clamp diodes to GND and IN. Applications that forward bias these diodes should take care not to exceed
the IC’s package power dissipation limits.
IN/V
IN and V
IN Supply Current
VDD Supply Current fS = 1MHz
Total Shutdown Current from IN
and V
VDD Undervoltage Lockout
Threshold
BST
BST Supply Current
PWM COMPARATOR
PWM Comparator Propagation
Delay
COMP
COMP Clamp Voltage, High V
COMP Slew Rate 1.4 V/µs
PWM Ramp Amplitude 1V
COMP Shutdown Resistance From COMP to GND, V
ERROR AMPLIFIER
Preset Output-Voltage Accuracy REFIN = SS -1
FB Regulation Accuracy Using
External Resistors
FB to OUT Resistor All VID settings except CTL1 = CTL2 = GND 5 8 11 kΩ
PARAMETER CONDITIONS MIN TYP MAX UNITS
DD
Voltage Range 2.35 3.60 V
DD
f
= 1MHz, no load,
DD
S
L = 0.47µH
(includes gate-drive current)
V
= V
= V
- V
= 3.6V,
IN
LX
EN
= 3.6V, V
= 0V
EN
IN
DD
BST
LX starts/stops switching
V
= V
DD
= V
BST
V
= 3.6V or 0V, V
LX
10mV overdrive 20 ns
= 2.35V to 3.6V 2 V
IN
CTL1 = CTL2 = GND 0.594 0.600 0.606 V
V
= 2.5V 4 4.6
IN
V
= 3.3V 5.5
IN
V
= 2.5V 1.4 2.3
IN
= 3.3V 2
V
IN
= 0V 13 µA
EN
VDD rising 2 2.1
VDD falling 1.8 1.9
Deglitching 2 µs
TA = +25°C 5
T
= +85°C 10
A
= V
= 0V 8 Ω
SS
Select
from
Table 1
+1 %
mA
mA
V
µA
MAX8643A
3A, 2MHz Step-Down Regulator
with Integrated Switches
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VIN= VDD= 3.3V, VFB= 0.5V, TA = -40°C to +85°C. Typical values are at TA= +25°C, circuit of Figure 1, unless otherwise noted.) (Note 2)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Open-Loop Voltage Gain 1kΩ from COMP to GND 115 dB
Error-Amplifier Unity-Gain
Bandwidth
Error-Amplifier Common-Mode
Input Range
Error-Amplifier Minimum Output
Current
FB Input Bias Current
Parallel 10kΩ, 40pF from COMP to GND (Note 3) 14 26 MHz
V
= 2.35V to 2.6V 0 V
DD
= 2.6V to 3.6V 0 V
V
DD
= 1V
V
COMP
V
= 0.7V, CTL1 = CTL2 =
FB
Sourcing 1000
Sinking -500
= +25°C -200 -40 nA
T
A
DD
DD
- 1.65
- 1.7
V
µA
CTL_
V
= 0V -7
CTL_ Input Bias Current
CTL_
V
CTL_
= V
DD
+7
µA
Rising 0.75
High-Impedance Threshold
Falling
V
DD
- 1.2V
V
Hysteresis All VID transitions 50 mV
REFIN
REFIN Input Bias Current V
REFIN Common-Mode Range
= 0.6V TA = +25°C -500 -100 nA
REFIN
V
= 2.3V to 2.6V 0 V
DD
= 2.6V to 3.6V 0 V
V
DD
DD
DD
- 1.65
- 1.7
V
REFIN Offset Voltage CTL1 = CTL2 = GND, TA = +25°C -3 +3 mV
LX (ALL PINS COMBINED)
V
= V
- V
LX On-Resistance, High Side ILX = -2A
LX On-Resistance, Low Side ILX = 2A
LX Current-Limit Threshold V
LX Leakage Current V
LX Switching Frequency V
= 2.5V, high-side sourcing 4 5.5 A
IN
= 3.6V, V
IN
= 2.5V to 3.3V
IN
EN
= V
SS
= 0V
IN
BST
= V
V
IN
BST
V
= 2.5V 36
IN
= 3.3V 34 55
V
IN
TA = +25°C
T
= +85°C
A
R
= 50kΩ 0.9 1 1.1
FREQ
= 23.2kΩ 1.8 2.0 2.2
R
FREQ
= 2.5V 39
LX
- V
= 3.3V 37 58
LX
V
= 0V -2
LX
V
= 3.6V +2
LX
V
= 0V 1
LX
= 3.6V 1
V
LX
mΩ
mΩ
µA
MHz
Frequency Range 500 2000 kHz
LX Minimum Off-Time V
LX Maximum Duty Cycle R
= 2.5V to 3.3V 40 75 ns
IN
FREQ
= 50kΩ, V
= 2.5V to 3.3V 93 96 %
IN
LX Minimum On-Time 80 ns
RMS LX Output Current 3A
MAX8643A
3A, 2MHz Step-Down Regulator
with Integrated Switches
4 _______________________________________________________________________________________
Note 2: Specifications are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by
design and characterization.
Note 3: Guaranteed by design.
ELECTRICAL CHARACTERISTICS (continued)
(VIN= VDD= 3.3V, VFB= 0.5V, TA = -40°C to +85°C. Typical values are at TA= +25°C, circuit of Figure 1, unless otherwise noted.) (Note 2)
Typical Operating Characteristics
(Typical values are at VIN= VDD= 3.3V, V
OUT
= 1.8V, R
FREQ
= 50kΩ, I
OUT
= 3A, and TA = +25°C, unless otherwise noted.)
EFFICIENCY vs. OUTPUT CURRENT
OUTPUT CURRENT (A)
EFFICIENCY (%)
MAX8643A toc02
60
65
75
70
80
85
90
95
100
0.1 1 10
V
OUT
= 1.5V
V
OUT
= 1.88V
VIN = VDD = 2.5V
V
OUT
= 1.2V
ENABLE
EN Input Logic-Low 0.7 V
EN Input Logic-High 1.7 V
EN, Input Current
SS
SS Charging Current V
SS Discharge Resistance 500 Ω
THERMAL SHUTDOWN
Thermal-Shutdown Threshold +165 °C
Thermal-Shutdown Hysteresis 20 °C
POWER-GOOD (PWRGD)
Power-Good Threshold Voltage VFB falling, 3mV hysteresis 87 90 93 %
Power-Good Falling-Edge Deglitch 48
PWRGD Output-Voltage Low I
PWRGD Leakage Current V
OVERCURRENT LIMIT
Current-Limit Startup Blanking 128
Restart Time 1024
PARAMETER CONDITIONS MIN TYP MAX UNITS
V
= 0V or 3.6V,
EN
= 3.6V
V
DD
= 0.45V 7 8 9 µA
SS
= 4mA 0.03 0.15 V
PWRGD
DD
= V
PWRGD
= 3.6V, V
TA = +25°C 1
= +85°C 0.01
T
A
= 0.9V 0.01 µA
FB
µA
Clock
cycles
Clock
cycles
Clock
cycles
EFFICIENCY vs. OUTPUT CURRENT
100
90
80
V
70
EFFICIENCY (%)
60
50
VIN = VDD = 3.3V
40
0.1 1
OUT
V
= 1.2V
OUT
OUTPUT CURRENT (A)
= 1.8V
V
= 2.5V
OUT
MAX8643A toc01
10
Typical Operating Characteristics (continued)
(Typical values are at VIN= VDD= 3.3V, V
OUT
= 1.8V, R
FREQ
= 50kΩ, I
OUT
= 3A, and TA = +25°C, unless otherwise noted.)
MAX8643A
3A, 2MHz Step-Down Regulator
with Integrated Switches
_______________________________________________________________________________________
5
EFFICIENCY vs. OUTPUT CURRENT
100
95
90
85
80
75
EFFICIENCY (%)
V
VIN = 2.5V
= 3.3V
V
DD
OUT
OUTPUT CURRENT (A)
70
65
60
0.1 1 10
V
= 1.2V
OUT
= 1.5V
V
= 1.8V
OUT
LOAD TRANSIENT
V
OUT
I
OUT
40μs/div
MAX8643A toc03
MAX8643A toc06
VIN = VDD = 3.3V
FREQUENCY vs. INPUT VOLTAGE
1950
1800
1650
1500
1350
FREQUENCY (kHz)
1200
1050
900
2.2 2.6 3.0 3.4 3.8
AC-COUPLED
50mV/div
1A/div
0A
-40°C
+25°C
-40°C
+25°C
INPUT VOLTAGE (V)
V
OUT
V
I
LX
LX
+85°C
+85°C
-0.02
MAX8643A toc04
-0.04
-0.06
-0.08
-0.10
-0.12
OUTPUT VOLTAGE CHARGE (%)
-0.14
-0.16
SWITCHING WAVEFORMS
100ns/div
0
V
= 1.8V
OUT
V
012345
LOAD CURRENT (A)
MAX8643A toc07
= 1.2V
OUT
AC-COUPLED
20mV/div
2A/div
0A
2V/div
0V
VIN = VDD = 3.3V
V
= 2.5V
OUT
LOAD REGULATION
MAX8643A toc05
SOFT-START WAVEFORMS
V
EN
V
OUT
R
400μs/div
LOAD
= 1Ω
MAX8643A toc08
2V/div
0V
1V/div
0V
V
EN
V
OUT
SHUTDOWN WAVEFORMS
R
= 1Ω
LOAD
10μs/div
MAX8643A toc09
2V/div
0V
1V/div
0V
MAX8643A
3A, 2MHz Step-Down Regulator
with Integrated Switches
6 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(Typical values are at VIN= VDD= 3.3V, V
OUT
= 1.8V, R
FREQ
= 50kΩ, I
OUT
= 3A, and TA = +25°C, unless otherwise noted.)
INPUT CURRENT vs. INPUT VOLTAGE
INPUT VOLTAGE (V)
INPUT CURRENT (μA)
MAX8643A toc10
2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
0
1
2
3
4
5
6
7
8
9
10
VEN = 0V
CURRENT LIMIT vs. OUTPUT VOLTAGE
OUTPUT VOLTAGE (V)
CURRENT LIMIT (A)
MAX8643A toc11
0.5 1.0 1.5 2.0 2.5
0
1
2
3
4
5
6
7
HICCUP CURRENT LIMIT
400μs/div
MAX8643A toc12
I
IN
I
OUT
V
OUT
5A/div
1A/div
1V/div
0A
0A
0V
RMS INPUT CURRENT DURING SHORT CIRCUIT
vs. INPUT VOLTAGE (C4 = 0.022μF)
INPUT VOLTAGE (V)
RMS INPUT CURRENT (A)
MAX8643A toc13
2.0 2.5 3.0 3.5 4.0
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
V
OUT
= 0V
EXPOSED PAD TEMPERATURE
vs. AMBIENT TEMPERATURE
TEMPERATURE (°C)
EXPOSED PAD TEMPERATURE (°C)
MAX8643A toc14
0 20406080100
10
20
30
40
50
60
70
80
90
100
110
V
OUT
= 1.8V
3A LOAD
MEASURED ON A MAX8643EVKIT
FEEDBACK VOLTAGE vs. TEMPERATURE
TEMPERATURE (°C)
FEEDBACK VOLTAGE (V)
MAX8643A toc15
-40 -15 10 35 60 85
0.56
0.57
0.58
0.59
0.60
0.61
0.62
0.63
0.64
SOFT-START WITH REFIN
200μs/div
MAX8643A toc16
V
PWRGD
V
OUT
V
REFIN
I
IN
1V/div
2V/div
1A/div
0V
0V
0A
0.5V/div
0V
STARTING INTO PREBIAS OUTPUT
100μs/div
C
SS
= 6800pF, CO = 122μF, L = 0.56μH, V
OUT
= 2.5V
MAX8643A toc17
2V/div
2V/div
V
EN
V
OUT
V
PWRGD
0V
0V
1V/div
0V
MAX8643A
3A, 2MHz Step-Down Regulator
with Integrated Switches
_______________________________________________________________________________________ 7
Pin Description
PIN NAME FUNCTION
1 PREBIAS
2V
3, 4
5 REFIN
6SS
7 GND Analog Circuit Ground
8 COMP
9FB
10 OUT
11 FREQ Oscillator Frequency Selection. Connect a resistor from FREQ to GND to select the switching frequency.
12 PWRGD
13 BST High-Side MOSFET Driver Supply. Bypass BST to LX with a 0.1µF capacitor.
14, 15, 16 LX
17–20 PGND Power Ground. Connect all PGND pins externally to the power ground plane.
21, 22, 23 IN
24 EN Enable Input. Logic input to enable/disable the MAX8643A.
— EP Exposed Paddle. Connect to a large ground plane to optimize thermal performance.
CTL1,
CTL2
Leave pin unconnected to prevent discharging of output capacitor during soft-start. Connect to GND
otherwise. (See the Soft-Starting into a Prebiased Output section.)
Supply Voltage and Bypass Input. Connect VDD to IN with a 10Ω resistor. Connect a 1µF ceramic
DD
capacitor from V
Preset Output Voltage Selection Input. CTL1 and CTL2 set the output voltage to one of nine preset
voltages. See Table 1 for preset voltages.
External Reference Input. Connect REFIN to SS to use the internal 0.6V reference. Connecting REFIN to an
external reference voltage forces FB to regulate the voltage applied to REFIN. REFIN is internally pulled to
GND when the IC is in shutdown mode.
Soft-Start Input. Connect a capacitor from SS to GND to set the startup time. See the Soft-Start and REFIN
section for details on setting the soft-start time.
Output of the Voltage-Error Amplifier. Connect the necessary compensation network from COMP to FB.
COMP is internally pulled to GND when the IC is in shutdown mode.
Feedback Input. Connect FB to the center tap of an external resistor-divider from the output to GND to set
the output voltage from 0.6V to 90% of VIN. Connect FB through an RC network to the output when using
CTL1 and CTL2 to select any of nine preset voltages.
Output Voltage Sense. Connect to the output. Leave OUT unconnected when an external resistor-divider
is used.
P ow er - G ood O utp ut. O p en- d r ai n outp ut that i s hi g h i m p ed ance w hen V
i nter nal l y p ul l ed l ow w hen V
IC i s i n shutd ow n m od e, V
Inductor Connection. All LX pins are internally connected together. Connect all LX pins to the output
inductor. LX is high impedance when the IC is in shutdown mode.
Power-Supply Input. Input supply range is from 2.35V to 3.6V. Bypass with 22µF ceramic capacitance to
PGND externally. See the Typical Application Circuit.
to GND.
DD
≥ 90% of V
fal l s b el ow 90% of i ts r eg ul ati on p oi nt. P W RG D i s i nter nal l y p ul l ed l ow w hen the
F B
or V
D D
i s b el ow the U V LO thr eshol d , or the IC i s i n ther m al shutd ow n.
I N
F B
or 0.6V . P W RGD i s
R E F IN
MAX8643A
3A, 2MHz Step-Down Regulator
with Integrated Switches
8 _______________________________________________________________________________________
Block Diagram
V
DD
MAX8643A
EN
SS
REFIN
OUT
8kΩ
FB
SHUTDOWN
CONTROL
BIAS
GENERATOR
VOLTAGE
REFERENCE
SOFT-START
ERROR
AMPLIFIER
UVLO
CIRCUITRY
THERMAL
SHUTDOWN
CURRENT-LIMIT
PWM
COMPARATOR
COMPARATOR
CONTROL
LOGIC
LX
ILIM THRESHOLD
BST CAPACITOR
CHARGING SWITCH
IN
BST
IN
LX
PGND
PREBIAS
CTL1
CTL2
COMP
VID
VOLTAGECONTROL
CIRCUITRY
COMP LOW
DETECTOR
0.9 x V
1V
P-P
OSCILLATOR
SHDN
FB
REFIN
FREQ
PWRGD
GND
MAX8643A
3A, 2MHz Step-Down Regulator
with Integrated Switches
_______________________________________________________________________________________ 9
Figure 1. 1MHz, All-Ceramic Capacitor Design with V
OUT
= 1.8V
Detailed Description
The MAX8643A high-efficiency, voltage-mode switching regulator is capable of delivering up to 3A of output
current. The MAX8643A provides output voltages from
0.6V to (0.9 x VIN) from 2.35V to 3.6V input supplies,
making it ideal for on-board point-of-load applications.
The output voltage accuracy is better than ±1% over
load, line, and temperature.
The MAX8643A features a wide switching frequency
range, allowing the user to achieve all-ceramic capacitor designs and fast transient responses. The high operating frequency minimizes the size of external
components. The MAX8643A is available in a small
(4mm x 4mm), lead-free, 24-pin thin QFN package. The
REFIN function makes the MAX8643A an ideal candidate for DDR and tracking power supplies. Using internal low-R
DS(ON)
(37mΩ) n-channel MOSFETs for both
high- and low-side switches maintains high efficiency at
both heavy-load and high-switching frequencies.
The MAX8643A employs voltage-mode control architecture with a high-bandwidth (> 14MHz) error amplifier. The voltage-mode control architecture allows up to
2MHz switching frequency, reducing board area. The
op-amp voltage-error amplifier works with type 3 com-
pensation to fully utilize the bandwidth of the high-frequency switching to obtain fast transient response.
Adjustable soft-start time provides flexibilities to minimize input startup inrush current. An open-drain,
power-good (PWRGD) output goes high when V
FB
reaches 90% of V
REFIN
or 0.54V.
Controller Function
The controller logic block is the central processor that
determines the duty cycle of the high-side MOSFET
under different line, load, and temperature conditions.
Under normal operation, where the current-limit and
temperature protection are not triggered, the controller
logic block takes the output from the PWM comparator
and generates the driver signals for both high-side and
low-side MOSFETs. The break-before-make logic and
the timing for charging the bootstrap capacitors are
calculated by the controller logic block. The error signal
from the voltage-error amplifier is compared with the
ramp signal generated by the oscillator at the PWM
comparator and, thus, the required PWM signal is produced. The high-side switch is turned on at the beginning of the oscillator cycle and turns off when the ramp
voltage exceeds the V
COMP
signal or the current-limit
threshold is exceeded. The low-side switch is then
turned on for the remainder of the oscillator cycle.
Typical Application Circuit
INPUT
2.4V TO 3.6V
22μF
C6
0.01μF
C7
R4
50kΩ
V
DD
1μF
R5
10Ω
C5
C4
0.022μF
IN
V
DD
CTL2
CTL1
EN
FREQ
REFIN
SS
PREBIAS
MAX8643A
GND
BST
OUT
PGND
COMP
PWRGD
C10
0.1μF
L1
LX
FB
1500pF
0.47μH
C3
560pF
R3
158Ω
C2
R2
2.67kΩ
V
C1
33pF
DD
R1
20kΩ
OUTPUT
1.8V, 3A
C8
22μFC90.01μF
MAX8643A
3A, 2MHz Step-Down Regulator
with Integrated Switches
10 ______________________________________________________________________________________
Current Limit
The internal, high-side MOSFET has a typical 5.5A
peak current-limit threshold. When current flowing out
of LX exceeds this limit, the high-side MOSFET turns off
and the synchronous rectifier turns on. The synchronous rectifier remains on until the inductor current falls
below the low-side current limit. This lowers the duty
cycle and causes the output voltage to droop until the
current limit is no longer exceeded. The MAX8643A
uses a hiccup mode to prevent overheating during
short-circuit output conditions.
During current limit if V
FB
drops below 420mV and
stays below this level for 12µs or more, the part enters
hiccup mode. The high-side MOSFET and the synchronous rectifier are turned off and both COMP and REFIN
are internally pulled low. If REFIN and SS are connected together, then both are pulled low. The part remains
in this state for 1024 clock cycles and then attempts to
restart for 128 clock cycles. If the fault-causing current
limit has cleared, the part resumes normal operation.
Otherwise, the part reenters hiccup mode again.
Soft-Start and REFIN
The MAX8643A utilizes an adjustable soft-start function
to limit inrush current during startup. An 8µA (typ) current source charges an external capacitor connected to
SS. The soft-start time is adjusted by the value of the
external capacitor from SS to GND. The required
capacitance value is determined as:
where tSSis the required soft-start time in seconds. The
MAX8643A also features an external reference input
(REFIN). The IC regulates FB to the voltage applied to
REFIN. The internal soft-start is not available when
using an external reference. A method of soft-start
when using an external reference is shown in Figure 2.
Connect REFIN to SS to use the internal 0.6V reference.
Undervoltage Lockout (UVLO)
The UVLO circuitry inhibits switching when VDDis
below 2V (typ). Once V
DD
rises above 2V (typ), UVLO
clears and the soft-start function activates. A 100mV
hysteresis is built in for glitch immunity.
BST
The gate-drive voltage for the high-side, n-channel
switch is generated by a flying-capacitor boost circuit.
The capacitor between BST and LX is charged from the
V
IN
supply while the low-side MOSFET is on. When the
low-side MOSFET is switched off, the voltage of the
capacitor is stacked above LX to provide the necessary
turn-on voltage for the high-side internal MOSFET.
Frequency Select (FREQ)
The switching frequency is resistor programmable from
500kHz to 2MHz. Set the switching frequency of the IC
with a resistor (R
FREQ
) connected from FREQ to GND.
R
FREQ
is calculated as:
where fSis the desired switching frequency in Hz.
Power-Good Output (PWRGD)
PWRGD is an open-drain output that goes high impedance when V
FB
is above 0.9 x V
REFIN
. PWRGD pulls
low when V
FB
is below 90% of its regulation for at least
48 clock cycles. PWRGD is low during shutdown.
Programming the Output Voltage
(CTL1, CTL2)
As shown in Table 1, the output voltage is pin programmable by the logic states of CTL1 and CTL2. CTL1 and
CTL2 are tri-level inputs: VDD, unconnected, and GND.
Table 1. CTL1 and CTL2 Output Voltage
Selection
Figure 2. Typical Soft-Start Implementation with External
Reference
R1
R2
At
×806μ
C
=
C
SS
V
.
REFIN
MAX8643A
R
k
FREQ
095
.
50
=×−
1
Ω
sf
μ
005
(.)
S
s
μ
CTL1 CTL2 V
GND GND 0.6
V
DD
GND Unconnected 0.8
GND V
Unconnected GND 1.2
Unconnected Unconnected 1.5
Unconnected V
V
DD
V
DD
V
DD
DD
DD
GND 2.0
Unconnected 2.5
OUT
0.7
1.0
1.8
(V)
MAX8643A
3A, 2MHz Step-Down Regulator
with Integrated Switches
______________________________________________________________________________________ 11
The logic states of CTL1 and CTL2 should be programmed only before power-up. Once the part is
enabled, CTL1 and CTL2 should not be changed. If the
output voltage needs to be reprogrammed, cycle
power or EN and reprogram before enabling.
Shutdown Mode
Drive EN to GND to shut down the IC and reduce quiescent current to less than 12µA. During shutdown, the LX
is high impedance. Drive EN high to enable the
MAX8643A.
Thermal Protection
Thermal-overload protection limits total power dissipation
in the device. When the junction temperature exceeds T
J
= +165°C, a thermal sensor forces the device into shutdown, allowing the die to cool. The thermal sensor turns
the device on again after the junction temperature cools
by 20°C, causing a pulsed output during continuous
overload conditions. The soft-start sequence begins after
recovery from a thermal-shutdown condition.
Applications Information
IN and VDDDecoupling
To decrease the noise effects due to the high switching
frequency and maximize the output accuracy of
the MAX8643A, decouple VINwith a 22µF capacitor
from VINto PGND. Also decouple VDDwith a 1µF from
VDDto GND. Place these capacitors as close to the IC
as possible.
Inductor Selection
Choose an inductor with the following equation:
where LIR is the ratio of the inductor ripple current to full
load current at the minimum duty cycle. Choose LIR
between 20% to 40% for best performance and stability.
Use an inductor with the lowest possible DC resistance
that fits in the allotted dimensions. Powdered iron ferrite
core types are often the best choice for performance.
With any core material, the core must be large enough
not to saturate at the current limit of the MAX8643A.
Output-Capacitor Selection
The key selection parameters for the output capacitor are
capacitance, ESR, ESL, and voltage-rating requirements.
These affect the overall stability, output ripple voltage,
and transient response of the DC-DC converter. The out-
put ripple occurs due to variations in the charge stored
in the output capacitor, the voltage drop due to the
capacitor’s ESR, and the voltage drop due to the
capacitor’s ESL. Calculate the output voltage ripple
due to the output capacitance, ESR, and ESL:
where the output ripple due to output capacitance,
ESR, and ESL is:
or whichever is larger.
The peak inductor current (I
P-P
) is:
Use these equations for initial capacitor selection.
Determine final values by testing a prototype or an
evaluation circuit. A smaller ripple current results in less
output voltage ripple. Since the inductor ripple current
is a factor of the inductor value, the output voltage ripple decreases with larger inductance. Use ceramic
capacitors for low ESR and low ESL at the switching
frequency of the converter. The ripple voltage due to
ESL is negligible when using ceramic capacitors.
Load-transient response depends on the selected output capacitance. During a load transient, the output
instantly changes by ESR x ΔI
LOAD
. Before the controller can respond, the output deviates further,
depending on the inductor and output capacitor values. After a short time, the controller responds by regulating the output voltage back to its predetermined
value. The controller response time depends on the
closed-loop bandwidth. A higher bandwidth yields a
faster response time, preventing the output from deviating further from its regulating value. See the
Compen-
sation Design
section for more details.
OUTS
VVV
×−
()
L
OUT IN OUT
=
f V LIR I
×××
S IN OUT MAX
()
VV
RIPPLE RIPPLE C
VV
RIPPLE ESR RIPPLE ESL
=+
() ()
()
+
V
RIPPLE C
()
V I x ESR
RIPPLE ESR P P()=−
V
RIPPLE ESL
()
V
RIPPLE ESL
()
=
xC xf
8
I
PP
=
t
ON
I
PP
=
t
OFF
I
PP
−
−
−
x ESL
x ESL
VV
I
PP
IN OUTSOUT
=
−
−
fL
×
V
x
V
IN
MAX8643A
3A, 2MHz Step-Down Regulator
with Integrated Switches
Input-Capacitor Selection
The input capacitor reduces the current peaks drawn
from the input power supply and reduces switching
noise in the IC. The total input capacitance must be
equal to or greater than the value given by the following
equation to keep the input ripple voltage within specs
and minimize the high-frequency ripple current being
fed back to the input source:
where V
IN-RIPPLE
is the maximum allowed input ripple
voltage across the input capacitors and is recommended to be less than 2% of the minimum input voltage. D
is the duty cycle (V
OUT
/ VIN), and tSis the switching
period (1/f
S
).
The impedance of the input capacitor at the switching
frequency should be less than that of the input source so
high-frequency switching currents do not pass through
the input source but are instead shunted through the
input capacitor. High source impedance requires high
input capacitance. The input capacitor must meet the
ripple current requirement imposed by the switching currents. The RMS input ripple current is given by:
where I
RIPPLE
is the input RMS ripple current.
Compensation Design
The power transfer function consists of one double pole
and one zero. The double pole is introduced by the output filtering inductor, L, and the output filtering capacitor,
CO. The ESR of the output filtering capacitor determines
the zero. The double pole and zero frequencies are
given as follows:
where RLis equal to the sum of the output inductor’s
DCR and the internal switch resistance, R
DSON
. A typical
value for R
DSON
is 37mΩ. ROis the output load resis-
tance, which is equal to the rated output voltage divided
by the rated output current. ESR is the total equivalent
series resistance of the output filtering capacitor. If there
is more than one output capacitor of the same type in
parallel, the value of the ESR in the above equation is
equal to that of the ESR of a single output capacitor
divided by the total number of output capacitors.
The high switching frequency range of the MAX8643A
allows the use of ceramic output capacitors. Since the
ESR of ceramic capacitors is typically very low, the frequency of the associated transfer function zero is higher
than the unity-gain crossover frequency, f
C
, and the zero
cannot be used to compensate for the double pole created by the output filtering inductor and capacitor. The double pole produces a gain drop of 40dB/decade and a
phase shift of 180°/decade. The error amplifier must compensate for this gain drop and phase shift to achieve a
stable high-bandwidth closed-loop system. Therefore,
use type III compensation as shown in Figure 3 and
Figure 4. Type III compensation possesses three poles
and two zeros with the first pole, f
P1_EA
, located at zero
frequency (DC). Locations of other poles and zeros of the
type III compensation are given by:
Figure 3. Type III Compensation Network
12 ______________________________________________________________________________________
Dxt xI
C
IN MIN
_
=
V
IN RIPPLE
S OUT
−
ff
PLC P LC
12
__
VVV
×−()
II
RIPPLE LOAD
=×
OUT IN OUT
V
IN
==
π
2
xLxC x
f
Z ESR
_
=
x ESR x C
2π
1
⎛
R ESR
O
⎜
⎝
1
O
+
O
RR
OL
f
MAX8643A
CTL1
CTL2
CTL1
CTL2
MAX8643A
R3
8kΩ
⎞
⎟
⎠
+
VOLTAGE
SELECT
=
ZEA1
_
LX
OUT
FB
COMP
a) EXTERNAL RESISTOR-DIVIDER
LX
OUT
FB
COMP
b) INTERNAL PRESET VOLTAGE
1
xR xC
π
211
L
C
OUT
C1
R1
C2
L
C
OUT
C1
R1
C2
V
OUT
R3
R4
R2
C3
V
OUT
R2
C3
MAX8643A
The above equations are based on the assumptions that
C1>>C2, and R3>>R2, which are true in most applications. Placements of these poles and zeros are determined by the frequencies of the double pole and ESR
zero of the power transfer function. It is also a function
of the desired closed-loop bandwidth. The following
section outlines the step-by-step design procedure to
calculate the required compensation components for
the MAX8643A. When the output voltage of the
MAX8643A is programmed to a preset voltage, R3 is
internal to the IC and R4 does not exist (Figure 3b).
When externally programming the MAX8643A (Figure
3a), the output voltage is determined by:
The zero-cross frequency of the closed-loop, fC, should
be between 10% and 20% of the switching frequency,
fS. A higher zero-cross frequency results in faster transient response. Once f
C
is chosen, C1 is calculated
from the following equation:
Due to the underdamped nature of the output LC double pole, set the two zero frequencies of the type III
compensation less than the LC double-pole frequency
to provide adequate phase boost. Set the two zero frequencies to 80% of the LC double-pole frequency.
Hence:
Setting the second compensation pole, f
P2_EA
, at
f
Z_ESR
yields:
Set the third compensation pole at 1/2 of the switching
frequency to gain some phase margin. Calculate C2 as
follows:
The above equations provide accurate compensation
when the zero-cross frequency is significantly higher
than the double-pole frequency. When the zero-cross
frequency is near the double-pole frequency, the actual
zero-cross frequency is higher than the calculated frequency. In this case, lowering the value of R1 reduces
the zero-cross frequency. Also, set the third pole of the
type III compensation close to the switching frequency
if the zero-cross frequency is above 200kHz to boost
the phase margin. The recommended range for R3 is
2kΩ to 10kΩ. Note that the loop compensation remains
unchanged if only R4’s resistance is altered to set different outputs.
Soft-Starting into a Prebiased Output
When the PREBIAS pin is left unconnected, the
MAX8643A is capable of soft-starting up into a prebiased
output without discharging the output capacitor. This
type of operation is also termed monotonic startup.
However, in order to avoid output voltage glitches during
soft-start, it should be ensured that the inductor current
is in continuous conduction mode during the end of the
soft-start period. This is done by satisfying the following
equation:
3A, 2MHz Step-Down Regulator
with Integrated Switches
______________________________________________________________________________________ 13
Figure 4. Type III Compensation Illustration
COMPENSATION
TRANSFER
FUNCTION
DOUBLE POLE
GAIN (dB)
POWER-STAGE
TRANSFER
FUNCTION
FIRST AND SECOND ZEROS
f
f
f
PEA2
ZEA1
PEA3
=
_
_
_
xR xC
π
211
=
xR xC
π
212
=
xR xC
π
223
OPEN-LOOP
GAIN
THIRD
POLE
SECOND
POLE
1
1
1
.
R
06 3
R
4
=
×
−
.
06
V
()
OUT
V
25
.
C
1
=
xxRx
231
IN
R
L
+×
()π
R
O
f
C
R
C
1
=
3
=
1
xC
08 1
1
xR
08 3
L x C x R ESR
x
OO
RR
L x C x R ESR
x
OO
RR
R
23=
C x ESR
O
C
+
()
+.
LO
+
()
+.
LO
C
2
=
1
xR x f
12
×π
S
VtI
OSSPP
C
×≥
O
−
2
MAX8643A
3A, 2MHz Step-Down Regulator
with Integrated Switches
14 ______________________________________________________________________________________
where COis the output capacitor, VOis the output voltage, tSSis the soft-start time set by the soft-start capacitor
CSS, and I
P-P
is the peak-to-peak inductor ripple current
(as defined in the
Output Capacitor Selection
section).
Depending on the application, one of these parameters
may drive the selection of the others. See the Starting into
Prebias Output waveforms in the
Typical Operating
Characteristics
section for an example selection of the
above parameters. Connecting the PREBIAS pin to GND
disables the prebias soft-start feature and causes the
MAX8643A to discharge any voltage present on the output capacitors and then commence its soft-start.
PCB Layout Considerations and
Thermal Performance
Careful PCB layout is critical to achieve clean and stable
operation. It is highly recommended to duplicate the
MAX8643A EV kit layout for optimum performance. If
deviation is necessary, follow these guidelines for good
PCB layout:
1) Connect input and output capacitors to the power
ground plane; connect all other capacitors to the signal ground plane.
2) Place capacitors on V
DD
, VIN, and SS as close as
possible to the IC and its corresponding pin using
direct traces. Keep power ground plane (connected
to PGND) and signal ground plane (connected to
GND) separate.
3) Keep the high-current paths as short and wide as
possible. Keep the path of switching current short
and minimize the loop area formed by LX, the output capacitors, and the input capacitors.
4) Connect IN, LX, and PGND separately to a large
copper area to help cool the IC to further improve
efficiency and long-term reliability.
5) Ensure all feedback connections are short and
direct. Place the feedback resistors and compensation components as close to the IC as possible.
6) Route high-speed switching nodes, such as LX,
away from sensitive analog areas (FB, COMP).
Chip Information
PROCESS: BiCMOS
THIN QFN
MAX8643A
19
20
21
22
12 3456
18 17 16 15 14 13
23
24
12
11
10
9
8
7
PGND
IN
PGND
IN
EN
PREBIAS
V
DD
CTL1
CTL2
REFIN
SS
PGND
PGND
LX
LX
BST
IN
PWRGD
OUT
FREQ
FB
GND
COMP
LX
TOP VIEW
+
Pin Configuration
MAX8643A
3A, 2MHz Step-Down Regulator
with Integrated Switches
______________________________________________________________________________________ 15
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages
.)
24L QFN THIN.EPS
PACKAGE OUTLINE,
12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm
21-0139
1
E
2
MAX8643A
3A, 2MHz Step-Down Regulator
with Integrated Switches
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products. Inc.
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages
.)
PACKAGE OUTLINE,
12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm
21-0139
2
E
2
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