MAXIM MAX793, MAX794, MAX795 User Manual

General Description

The MAX793/MAX794/MAX795 microprocessor (µP)
supervisory circuits monitor and control the activities of
+3.0V/+3.3V µPs by providing backup-battery switchover,
among other features such as low-line indication, µP
reset, write protection for CMOS RAM, and a watchdog
(see the

Selector Guide

below). The backup-battery volt­age can exceed VCC, permitting the use of 3.6V lithium
batteries in systems using 3.0V to 3.3V for VCC.

The MAX793/MAX795 offer a choice of reset threshold
voltage range (denoted by suffix letter): 3.00V to 3.15V
(T), 2.85V to 3.00V (S), and 2.55V to 2.70V (R). The
MAX794’s reset threshold is set externally with a resistor
divider. The MAX793/MAX794 are available in 16-pin
DIP and narrow SO packages, and the MAX795 comes
in 8-pin DIP and SO packages.

________________________Applications

Battery-Powered Computers and Controllers

Embedded Controllers

Intelligent Controllers

Critical µP Power Monitoring

Portable Equipment

____________________________Features

MAX793/MAX794/MAX795
o Precision Supply-Voltage Monitor:

Fixed Reset Trip Voltage (MAX793/MAX795)
Adjustable Reset Trip Voltage (MAX794)

o Guaranteed Reset Assertion to VCC= 1V
o Backup-Battery Power Switching—Battery

Voltage Can Exceed V

CC

o On-Board Gating of Chip-Enable Signals—7ns

Max Propagation Delay

MAX793/MAX794 Only

o Battery Freshness Seal
o Battery OK Output (MAX793)
o Uncommitted Voltage Monitor for Power-Fail or

Low-Battery Warning

o Independent Watchdog Timer (1.6s timeout)
o Manual Reset Input

MAX793/MAX794/MAX795

3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits

________________________________________________________________

Maxim Integrated Products

1

19-0366; Rev 6; 3/10

FEATURE

Active-Low Reset

Active-High Reset

Programmable Reset
Threshold

Low-Line Early Warning
Output

MAX793







MAX794









MAX795



Backup-Battery
Switchover

External Switch Driver

Power-Fail Comparator













Battery OK Output







_____________________Selector Guide

__________Typical Operating Circuit

Watchdog Input

Battery Freshness Seal









Manual Reset Input







Chip-Enable Gating

 

Pin-Package 16-DIP/SO 16-DIP/SO 8-DIP/SO

Pin Configurations appear at end of data sheet.

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.

Ordering Information

Ordering Information continued at end of data sheet.

*

The MAX793/MAX795 offer a choice of reset threshold voltage.
Select the letter corresponding to the desired reset threshold
voltage range (T = 3.00V to 3.15V, S = 2.85V to 3.00V, R =

2.55V to 2.70V) and insert it into the blank to complete the part
number. The MAX794’s reset threshold is adjustable.

Devices are available in both leaded and lead-free packaging.
Specify lead free by adding the + symbol at the end of the part
number when ordering.

PART* TEMP RANGE

MAX793_CPE 0°C to +70°C 16 Plastic DIP

MAX793_CSE 0°C to +70°C 16 Narrow SO

PIN­PACKAGE

(OPTIONAL)

V

CC

BATT

WDO

MR

PFO

PFI

Si9433DY

SILICONIX

PMOS

BATT ON

MAX793

LOWLINE

GND

OUT

CE OUT

CE IN

WDI

RESET

BATT OK

0.1µF

CMOS

RAM

ADDRESS
DECODER

V

CC

V

CC

A0-A15

I/O
NMI

µP

RESET

3.6V

3.0V OR 3.3V

+5V SUPPLY

FAILURE

+5V

0.1µF

0.1µF

µA

MAX793/MAX794/MAX795

3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VCC= 3.17V to 5.5V for the MAX793T/MAX795T, VCC= 3.02V to 5.5V for the MAX793S/MAX795S, VCC= 2.72V to 5.5V for the
MAX793R/MAX794/MAX795R, V

BATT

= 3.6V, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

Terminal Voltage (with respect to GND)

V

CC

......................................................................-0.3V to +6.0V

V

BATT

...................................................................-0.3V to +6.0V

All Other Inputs ..................-0.3V to the higher of V

CC

or V

BATT

Continuous Input Current

V

CC

.................................................................................200mA

V

BATT

................................................................................50mA

GND ..................................................................................20mA

Output Current

V

OUT

................................................................................200mA

All Other Outputs ..............................................................20mA

Continuous Power Dissipation (T

A

= +70°C)

8-Pin Plastic DIP (derate 9.09mW/°C above +70°C) .....727mW

8-Pin SO (derate 5.88mW/°C above +70°C)..................471mW

16-Pin Plastic DIP (derate 10.53mW/°C above +70°C) .842mW
16-Pin Narrow SO (derate 9.52mW/°C above +70°C) ...696mW

Operating Temperature Ranges

MAX793_C_ _/MAX794C_ _/MAX795_C_ _ ......... 0°C to +70°C

MAX793_E_ _/MAX794E_ _/MAX795_E_ _ ........-40°C to +85°C

Storage Temperature Range .............................-65°C to +160°C

Lead Temperature (soldering, 10s) .................................+300°C

Soldering Temperature (reflow) .......................................+260°C

MAX79_E

MAX79_C

V

BATT

> V

CC

(Note 6)

I

OUT

= 250µA (Note 4)

I

OUT

= 30mA (Note 4)

VSW> VCC> 1.75V (Note 5)

I

OUT

= 75mA

V

BATT

= 2.3V

CONDITIONS

Battery Switch Threshold
(V

CC

falling)

V

2.30 2.41 2.52

V

SW

2.55 2.68 2.80

2.69 2.82 2.95

mV20 65

VCC-

V

BATT

V

V

BATT

- 0.14

V

OUT

OUT Output Voltage in
Battery-Backup Mode

V

BATT

- 0.1 V

BATT

- 0.034

V

1.1 5.5

1.0 5.5

Operating Voltage Range,
V

CC

, V

BATT

(Note 1)

V

VCC- 0.001 VCC- 0.5mV

V

OUT

OUT Output Voltage in
Normal Mode

VCC- 0.12 VCC- 0.050

VCC- 0.3 VCC- 0.125

µA0.5

Battery Leakage Current
(Note 3)

µA1

BATT Supply Current
(excluding I

OUT

) (Note 2)

UNITSMIN TYP MAXSYMBOLPARAMETER

VCC= 0V, V

OUT

= 0V µA1

BATT Leakage Current,
Freshness Seal Enabled

I

OUT

= 250µA

I

OUT

= 1mA

MAX793T/MAX795T
MAX793S/MAX795S

This value is identical to the reset threshold,
VCCrising for V

BATT

> V

RST

VCC-

V

BATT

MAX793R/MAX795R/
MAX794

V

BATT

< V

RST

mV25 65

Battery Switch Threshold
(V

CC

rising) (Note 7)

MAX793/MAX794,
MR = V

CC

µA

62 80

I

SUPPLY

46 60

VCCSupply Current
(excluding I

OUT

, I

CE OUT

)

VCC= 2.1V,
V

BATT

= 2.3V

µA

32 45

I

SUPPLY

VCCSupply Current in
Battery-Backup Mode
(excluding I

OUT

)

VCC< 3.6V

VCC< 5.5V

MAX793/MAX794

MAX795 24 35

MAX795

49 70

35 50VCC< 3.6V

VCC< 5.5V

MAX793/MAX794/MAX795

3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(VCC= 3.17V to 5.5V for the MAX793T/MAX795T, VCC= 3.02V to 5.5V for the MAX793S/MAX795S, VCC= 2.72V to 5.5V for the
MAX793R/MAX794/MAX795R, V

BATT

= 3.6V, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.)

CONDITIONS

2.85 2.925 3.00

3.00 3.075 3.15

UNITSMIN TYP MAXSYMBOLPARAMETER

VCCfalling

3.00 3.085 3.17

2.55 2.625 2.70

V

RST

V

V

RST IN

V

VCCfalling

VCCrising

RESET IN Threshold
(MAX794 only)

1.212 1.240 1.262

Reset Threshold (Note 8)

2.55 2.635 2.72

2.85 2.935 3.02

V

LR

mV

MAX793

LOWLINE-to-Reset
Threshold, (V

LOWLINE

-

V

RST

), VCCFalling

VCC< 3.6V

51525

30 45 60

mV

MAX793S/MAX795S

MAX793T/MAX795T

MAX794

MAX793

3.08

Low-Line Comparator
Hysteresis

3.23

mV

10

10

mst

RP

140 200 280Reset Timeout Period

V

MAX793R/MAX795R 2.78

nA

V

PFI

rising

V

PFI

falling

PFI Input Current

MAX794

V

-25 2 25

V

TH

1.212 1.250 1.287

PFI Input Threshold

1.212 1.240 1.262

V

LL

1.317

LOWLINE Threshold,
V

CC

Rising

VV

BOK

2.00 2.25 2.50

BATT OK Threshold
(MAX793)

V

OH

VI

SOURCE

= 300µA, VCC= V

RST

max

BATT OK, BATT ON, WDO,
LOWLINE Output-Voltage
High

I

SOURCE

= 300µA, VCC= V

RST

min

0.8V

CC

0.86V

CC

VV

OH

0.8V

CC

0.86V

CC

RESET Output-Voltage High

mV10 20PFI Hysteresis, PFI Rising

MAX793T/MAX795T

MAX793S/MAX795S

MAX793R/MAX795R

MAX793T/MAX795T

MAX793S/MAX795S

MAX793R/MAX795R

nA

RESET IN Leakage Current
(MAX794 only)

-25 2 25

MAX794

V

OH

VI

SOURCE

= 65µA, VCC= V

RST

max

PFO Output-Voltage High

0.8V

CC

V

OH

VI

SOURCE

= 100µA, VCC= 2.3V, V

BATT

= 3V

BATT ON Output­Voltage High

0.8V

BATT

I

LEAK

µAVCC= V

RST

max

RESET Output Leakage
Current (Note 9)

-1 -1

I

SC

µAVCC= 3.3V, V

PFO

= 0V

PFO Output Short to GND
Current

180 500

V

OL

V

I

SINK

= 1.2mA; RESET, LOWLINE tested

with V

CC

= V

RST

min; RESET, BATTOK,

WDO tested with V

CC

= V

RST

max

PFO, RESET, RESET, WDO,
LOWLINE Output-Voltage

Low

0.08 0.2V

CC

INPUT AND OUTPUT LEVELS

VCCrising 1.212 1.250 1.282

MAX793/MAX794/MAX795

3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits

4 _______________________________________________________________________________________

CONDITIONS

V

OL

V

V

OL

VI

SINK

= 3.2mA, VCC= V

RST

max

MAX79_E, V

BATT

= VCC= 1.2V, I

SINK

= 200µA

BATT ON Output­Voltage Low

MAX79_C, V

BATT

= VCC= 1.0V, I

SINK

= 40µA

0.2V

CC

RESET Output-Voltage Low

UNITSMIN TYP MAXSYMBOLPARAMETER

V

IL

V

t

MR

nsMAX793/MAX794 only

V

RST

max < VCC< 5.5V

MR Pulse Width

100

All Inputs Including PFO
(Note 10)

0.3V

CC

V

IH

0.7V

CC

0.17 0.3

0.13 0.3

ELECTRICAL CHARACTERISTICS (continued)

(VCC= 3.17V to 5.5V for the MAX793T/MAX795T, VCC= 3.02V to 5.5V for the MAX793S/MAX795S, VCC= 2.72V to 5.5V for the
MAX793R/MAX794/MAX795R, V

BATT

= 3.6V, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.)

t

MD

ns

MAX793/MAX794 only, MR = 0V

MAX793/MAX794 only

µA

MR-to-Reset Delay

25 70 250

MR Pullup Current

75 250

Ω

nsVCC= V

RST

max, Figure 9

Enable mode, VCC= V

RST

max

CE IN-to-CE OUT
Propagation Delay

Disable mode

27

CE IN-to-CE OUT
Resistance

V

OH

V

OL

V

VCC= V

RST

max, I

OUT

= 1.6mA,

V

CE IN

= 0V

VCC= V

RST

max, I

OUT

= -1mA,

V

CE IN

= V

CC

CE OUT Drive from CE IN

0.2V

CC

0.8V

CC

nA

46

I

LEAK

±10

CE IN Leakage Current

Note 1: VCCsupply current, logic-input leakage, watchdog functionality (MAX793/MAX794), MR functionality (MAX793/MAX794),

PFI functionality (MAX793/MAX794), and state of RESET and RESET (MAX793/MAX794) tested at V

BATT

= 3.6V and VCC=

5.5V. The state of RESET is tested at V

CC

= VCCmin.

Note 2: Tested at V

BATT

= 3.6V, VCC= 3.5V and 0V. The battery current rises to 10µA over a narrow transition window around V

CC

= 1.9V.

Note 3: Leakage current into the battery is tested under the worst-case conditions at V

CC

= 5.5V, V

BATT

= 1.8V and VCC= 1.5V,

V

BATT

= 1.0V.

Note 4: Guaranteed by design.
Note 5: When V

SW

> VCC> V

BATT

, OUT remains connected to VCCuntil VCCdrops below V

BATT

. The VCC-to-V

BATT

comparator

has a small 15mV typical hysteresis to prevent oscillation. For V

CC

< 1.75V (typical), OUT switches to BATT regardless of

V

BATT

.

Note 6: When V

BATT

> VCC> VSW, OUT remains connected to VCCuntil VCCdrops below the battery switch threshold (VSW).

Note 7: OUT switches from BATT to V

CC

when VCCrises above the reset threshold, if V

BATT

> V

RST

. In this case, switchover back

to V

CC

occurs at the exact voltage that causes reset to be asserted, however, switchover occurs 200ms prior to reset. If

V

BATT

< V

RST

, OUT switches from BATT to VCCwhen VCCexceeds V

BATT

.

Note 8: The reset threshold tolerance is wider for V

CC

rising than for VCCfalling to accommodate the 10mV typical hysteresis,

which prevents internal oscillation.

Note 9: The leakage current into or out of the RESET pin is tested with RESET not asserted (RESET output high impedance).
Note 10: PFO is normally an output, but is used as an input when activating the battery freshness seal.

µs10

Reset to CE OUT High Delay

t

WD

s

0V < VCC< 5.5V

Watchdog Timeout Period

IOH= 500µA, VCC< 2.3V

µA

1.00 1.60 2.25

-1 0.01 1WDI Input Current

VV

OH

0.8V

BATT

CE OUT Output-Voltage
High (reset active)

nsWDI Pulse Width 100

MANUAL RESET INPUT

CHIP-ENABLE GATING

WATCHDOG (MAX793/MAX794 only)

MAX793/MAX794/MAX795

3.0V/3.3V/Adjustable Microprocessor
Supervisory Circuits

_______________________________________________________________________________________

5

__________________________________________Typical Operating Characteristics

(TA = +25°C, unless otherwise noted.)

VCC-TO-OUT ON-RESISTANCE

vs. TEMPERATURE

3.0

2.8

2.6

2.4

2.2
VCC = 3.0V

2.0

1.8

1.6

-TO-OUT ON-RESISTANCE (Ω)

CC

1.4

V

1.2

1.0

-40 100

VCC = 5V

20-20 0 8040 60

TEMPERATURE (°C)

BATTERY SUPPLY CURRENT vs.

TEMPERATURE (BATTERY-BACKUP MODE)

0.10

0.08

0.06

0.04

SUPPLY CURRENT (µA)

0.02

0

-40 100

20-20 0 8040 60

TEMPERATURE (°C)

MAX793

LOWLINE-TO-RESET THRESHOLD

vs. TEMPERATURE

100

90

80

70

60

50

40

30

20

LOWLINE-TO-RESET THRESHOLD (mV)

10

0

-40 100

20-20 0 8040 60

TEMPERATURE (°C)

I

= 30mA

OUT

VCC = 3.3V

VCC = 0V

= 3.6V

V

BATT

VCC FALLING

MAX793 TOC1

100

BATT-TO-OUT ON-RESISTANCE (Ω)

MAX793 TOC4

RESET TIMEOUT PERIOD (ms)

MAX793 TOC7

PROPAGATION DELAY (µs)

BATT-TO-OUT ON-RESISTANCE

vs. TEMPERATURE

160

140

120

V

= 3.6V

BATT

80

60

40

-40 100

V

= 3.0V

BATT

V

= 5V

BATT

20-20 0 8040 60

TEMPERATURE (°C)

I

OUT

V

CC

= 250µA
= 0V

RESET TIMEOUT PERIOD

vs. TEMPERATURE

250

200

150

100

50

0

-40 100
TEMPERATURE (°C)

VCC RISING FROM
OV TO V

20-20 0 8040 60

MAX

RST

MAX793/MAX794

LOWLINE COMPARATOR PROPAGATION DELAY

vs. TEMPERATURE

10

8

6

4

2

0

VCC RISING

VCC FALLING

-40 100

40mV OVERDRIVE

20-20 0 8040 60

TEMPERATURE (°C)

MAX793 TOC2

MAX793 TOC5

MAX793 TOC8

VCC SUPPLY CURRENT vs. TEMPERATURE

(NORMAL OPERATING MODE)

70

60

MAX795, VCC = 5V

50

40

30

SUPPLY CURRENT (µA)

20

CC

V

10

0

MAX795, VCC = 3.3V

-40 100

MAX793/4, VCC = 5V

MAX793/4, VCC = 3.3V

V

= VCC = V

BATT

20-20 0 8040 60

TEMPERATURE (°C)

RESET COMPARATOR PROPAGATION DELAY

vs. TEMPERATURE (V

30

25

20

15

10

PROPAGATION DELAY (µs)

5

0

-40 100

20-20 0 8040 60

TEMPERATURE (°C)

FALLING)

CC

MAX793/MAX794

PFI THRESHOLD vs. TEMPERATURE

1.250

1.245

1.240

PFI THRESHOLD (V)

1.235

1.230

-40 100

20-20 0 8040 60

TEMPERATURE (°C)

OUT

MAX793 TOC3

MAX793 TOC6

MAX793 TOC9

MAX793/MAX794/MAX795

3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits

6 _______________________________________________________________________________________

____________________________Typical Operating Characteristics (continued)

(TA = +25°C, unless otherwise noted.)

1.242

1.241

1.240

1.239

1.238

1.237

1.236

30

25

20

15

10

5

0

-40 100

MAX794

RESET IN THRESHOLD AND LOWLINE-TO-RESET IN

THRESHOLD vs. TEMPERATURE

TEMPERATURE (°C)

RESET IN THRESHOLD (V)

LOWLINE-TO-RESET IN THRESHOLD (mV)

20-20 0 8040 60

V

LOWLINE

- V

RST

V

RESET IN

VCC FALLING

MAX793 TOC10

2.5

2.0

1.5

1.0

0.5

0

-40 100

MAX793

BATT OK THRESHOLD vs. TEMPERATURE

MAX793 TOC11

TEMPERATURE (°C)

BATT OK THRESHOLD (V)

20-20 0 8040 60

V

BATT

FALLING

60

50

40

30

20

10

0

-40 100

CE IN-TO-CE OUT ON-RESISTANCE

vs. TEMPERATURE

TEMPERATURE (°C)

CE IN-TO-CE OUT ON-RESISTANCE (Ω)

20-20 0 8040 60

VCC = V

RST

MAX

MAX793 TOC12

1.70

1.65

1.60

1.55

1.50

-40 100

MAX793/MAX794

WATCHDOG TIMEOUT PERIOD

vs. TEMPERATURE

MAX793 TOC13

TEMPERATURE (°C)

WATCHDOG TIMEOUT PERIOD (sec)

20-20 0 8040 60

20

15

10

5

0

-40 100

MAX793/MAX794

BATTERY FRESHNESS SEAL

LEAKAGE CURRENT vs. TEMPERATURE

MAX793 TOC14

TEMPERATURE (°C)

LEAKAGE CURRENT (nA)

20-20 0 8040 60

V

BATT

= 5.5V

V

CC

= 0V

V

OUT

= 0V

1.002

1.001

1.000

0.999

0.998

0.997

0.996

-40 100

RESET THRESHOLD

vs. TEMPERATURE (NORMALIZED)

MAX793 TOC15

TEMPERATURE (°C)

V

RST

(NORMALIZED)

20-20 0 8040 60

VCC FALLING

10

8

6

4

2

0

-40 100

MAX793/MAX794

PFI TO PFO PROPAGATION DELAY

vs. TEMPERATURE

MAX793 TOC16

TEMPERATURE (°C)

PROPAGATION DELAY (µs)

20-20 0 8040 60

V

PFI

FALLING

20mV OVERDRIVE

MAX793/MAX794/MAX795

3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits

_______________________________________________________________________________________ 7

______________________________________________________________Pin Description

PIN

Supply Output for CMOS RAM. When VCCrises above the reset threshold or above
V

BATT

, OUT is connected to VCCthrough an internal p-channel MOSFET switch. When

V

CC

falls below VSWand V

BATT

, BATT connects to OUT.

OUT1 1

Reset Input. Connect to an external resistor-divider to select the reset threshold. The
reset threshold can be programmed anywhere in the V

SW

to 5.5V range.

RESET IN
(MAX794)

3 —

Battery Status Output. High in normal operating mode when V

BATT

exceeds V

BOK

, other-

wise low. V

BATT

is checked continuously. Disabled and logic low while VCCis below VSW.

BATT OK

(MAX793)

Main Supply InputV

CC

2 2

Power-Fail Comparator Output. When PFI is less than V

PFT

or when VCCfalls below

V

SW

, PFO goes low; otherwise, PFO remains high. PFO is also used to enable the bat-

tery freshness seal (see

Battery Freshness Seal

and

Power-Fail Comparator

sections).

PFO

7 —

Active-High Reset Output. Sources and sinks current. RESET is the inverse of RESET.

RESET13

Chip-Enable Output. CE OUT goes low only when CE IN is low and reset is not asserted.
If CE IN is low when reset is asserted, CE OUT remains low for 10µs or until CE IN goes
high, whichever occurs first. CE OUT is pulled up to OUT.

CE OUT

12

—

6

GroundGND6

Power-Fail Comparator Input. When PFI is less than V

PFT

or when VCCfalls below VSW,

PFO goes low; otherwise, PFO remains high (see

Power-Fail Comparator

section).

Connect to V

CC

if unused.

PFI4

Chip-Enable Input. The input to the chip-enable gating circuit. Connect to GND if unused.

CE IN

11 5

4

—

Watchdog Output. WDO goes low if WDI remains either high or low for longer than the
watchdog timeout period. WDO returns high on the next transition of WDI. WDO is a
logic high for V

SW

< VCC< V

RST

, and low when VCCis below VSW.

WDO

9 —

Manual Reset Input. A logic low on MR asserts reset. Reset remains asserted as long as
MR is low and for 200ms after MR returns high. The active-low input has an internal
70µA pullup current. It can be driven from a TTL- or CMOS-logic line or shorted to
ground with a switch. Leave open if unused.

MR

8 —

Watchdog Input. If WDI remains either high or low for longer than the watchdog timeout
period, the internal watchdog timer runs out and WDO goes low. WDO returns high on
the next transition of WDI. Connect WDO to MR to generate a reset due to a watchdog
fault.

WDI10 —

Early Power-Fail Warning Output. Low when VCCfalls to VLR. This output can be used to
generate an NMI to provide early warning of imminent power failure.

LOWLINE

14 —

Open-Drain, Active-Low Reset Output. Pulses low for 200ms when triggered, and stays
low whenever V

CC

is below the reset threshold or when MR is a logic low. It remains low

for 200ms after either V

CC

rises above the reset threshold, the watchdog triggers a reset

(WDO connected to MR), or MR goes low to high.

RESET

15 7

Backup-Battery Input. When VCCfalls below VSWand V

BATT

, OUT switches from V

CC

to

BATT. When V

CC

rises above the reset threshold or above V

BATT

, OUT reconnects to

V

CC

. V

BATT

can exceed VCC. Connect VCC, OUT, and BATT together if no battery is

used.

BATT16 8

Logic Output/External Bypass Switch-Driver Output. High when OUT switches to BATT.
Low when OUT switches to V

CC

. Connect the base/gate of PNP/PMOS transistor to

BATT ON for I

OUT

requirements exceeding 75mA.

BATT ON5 3

MAX793/

MAX794

FUNCTIONNAME

MAX795

MAX793/MAX794/MAX795

3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits

8 _______________________________________________________________________________________

_______________Detailed Description

General Timing Characteristics

The MAX793/MAX794/MAX795 are designed for 3.3V
and 3V systems, and provide a number of supervisory
functions (see the

Selector Guide

on the front page).
Figures 1 and 2 show the typical timing relationships of
the various outputs during power-up and power-down
with typical VCCrise and fall times.

Manual Reset Input (MAX793/MAX794)

Many microprocessor-based products require manual­reset capability, allowing the operator, a test technician,
or external logic circuitry to initiate a reset. On the
MAX793/MAX794, a logic low on MR asserts reset. Reset
remains asserted while MR is low, and for tRP(200ms)
after it returns high. During the first half of the reset time-

out period (t

RP

), the state of MR is ignored if PFO is exter-

nally forced low to facilitate enabling the battery fresh­ness seal. MR has an internal 70µA pullup current, so it
can be left open if it is not used. This input can be driven
with TTL- or CMOS-logic levels, or with open-drain/collec­tor outputs. Connect a normally open momentary switch
from MR to GND to create a manual-reset function; exter­nal debounce circuitry is not required. If MR is driven
from long cables or the device is used in a noisy environ­ment, connect a 0.1µF capacitor from MR to ground to
provide additional noise immunity.

Reset Outputs

A microprocessor’s (µP’s) reset input starts the µP in a
known state. These MAX793/MAX794/MAX795 µP
supervisory circuits assert a reset to prevent code exe­cution errors during power-up, power-down, and

Figure 1. Timing Diagram, VCCRising

V

RST

V

SW

V

CC

V

(MAX793/MAX794)

LOWLINE

(PULLED UP TO VCC)

V

RESET

V

LL

5µs

t

RP

t

(MAX793/MAX794)

V

RESET

V

CE OUT

V

WDO

(MAX793/MAX794)

V

BOK

(MAX793)

PFO
(MAX793/MAX794)

BATT ON

SHOWN FOR V
TYPICAL PROPAGATION DELAYS REFLECT A 40mV OVERDRIVE.

MAX794: V

= 0V to 3.3V, V

CC

RESET IN

= VCC (V

V

BATT

= 3.6V, CE IN = GND.

BATT

/ V

RST IN

RST

)

25µs

25µs

25µs

25µs

tRP/

tRP/

2

2

RP

(PFO FOLLOWS PFI)

brownout conditions. RESET is guaranteed to be a
logic low for 0V < VCC< V

RST

, provided V

BATT

is

greater than 1V. Without a backup battery (V

BATT

=

VCC= V

OUT

), RESET is guaranteed valid for VCC≥ 1V.

Once VCCexceeds the reset threshold, an internal
timer keeps RESET low for the reset timeout period
(tRP); after this interval, RESET becomes high imped­ance (Figure 2). RESET is an open-drain output, and
requires a pullup resistor to VCC(Figure 3). Use a

4.7kΩ to 1MΩ pullup resistor that provides sufficient
current to assure the proper logic levels to the µP.

If a brownout condition occurs (VCCdips below the
reset threshold), RESET goes low. Each time RESET is
asserted, it stays low for the reset timeout period. Any
time VCCgoes below the reset threshold, the internal
timer restarts.

The watchdog output (WDO) can also be used to initi­ate a reset. See the

Watchdog Output

section.

The RESET output is the inverse of the RESET output,
and it can both source and sink current.

MAX793/MAX794/MAX795

3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits

_______________________________________________________________________________________ 9

Figure 2. Timing Diagram, VCCFalling

V

LL

V

RST

V

CC

V

LOWLINE

(MAX793/MAX794)

V

RESET

(RESET PULLED UP TO VCC)

V

RESET

(MAX793/MAX794)

4µs

20µs

20µs

V

SW

V

CE OUT

V

WDO

(MAX793/MAX794)

V

BOK

(MAX793)

V

PFO

(MAX793/MAX794)

V

BATT ON

SHOWN FOR V
TYPICAL DELAY TIMES REFLECT A 40mV OVERDRIVE

MAX794: V

CC

RESET IN

= 3.3V to 0V, V

= V

CC (VRST IN

= 3.6V, CE IN = GND, PFI = VCC.

BATT

/ V

RST

25µs

V

25µs

25µs

25µs

25µs

BATT

V

BATT

10µs

)

MAX793/MAX794/MAX795

Reset Threshold

The MAX793T/MAX795T are intended for 3.3V systems
with a ±5% power-supply tolerance and a 10% systems
tolerance. Except when MR is asserted, reset does not
assert as long as the power supply remains above

3.15V (3.3V - 5%). Reset is guaranteed to assert before
the power supply falls below 3.0V (3.3V - 10%).

The MAX793S/MAX795S are designed for 3.3V ±10%
power supplies. Except when MR is asserted, they are
guaranteed not to assert reset as long as the supply
remains above 3.0V (3.0V is just above 3.3V - 10%).
Reset is guaranteed to assert before the power supply
falls below 2.85V (3.3V - 14%).

The MAX793R/MAX795R are optimized to monitor 3.0V
±10% power supplies. Reset does not occur until V

CC

falls below 2.7V (3.0V - 10%), but is guaranteed to
occur before the supply falls below 2.55V (3.0V - 15%).

Program the MAX794’s reset threshold with an external
voltage divider to RESET IN. The reset-threshold toler­ance is a combination of the RESET IN tolerance and
the tolerance of the resistors used to make the external
voltage divider. Calculate the reset threshold as follows:

V

RST

= V

RST IN

(R1 / R2 + 1)

Using the standard application circuit (Figure 3), the
reset threshold can be programmed anywhere in the
range of V

SW

(the battery switch threshold) to 5.5V.

Reset is asserted when V

CC

falls below VSW.

Battery Freshness Seal

The MAX793/MAX794’s battery freshness seal discon­nects the backup battery from internal circuitry until it is
needed. This allows an OEM to ensure that the backup
battery connected to BATT is fresh when the final prod­uct is put to use. To enable the freshness seal, connect
a battery to BATT, ground PFO, bring VCCabove the
reset threshold, and hold it there until reset is deassert­ed following the reset timeout period, then bring V

CC

back down again (Figure 4). Once the battery fresh­ness seal is enabled (disconnecting the backup battery
from the internal circuitry and anything connected to
OUT), it remains enabled until VCCis brought above
V

RST

. Note that connecting PFO to MR does not inter-

fere with battery freshness seal operation.

BATT OK Output (MAX793)

BATT OK indicates the status of the backup battery.
When reset is not asserted, the MAX793 checks the
battery voltage continuously. If V

BATT

is below V

BOK

(2.0V min), BATT OK goes low; otherwise, it remains
pulled up to VCC. BATT OK also goes low when V

CC

goes below VSW.

Watchdog Input (MAX793/MAX794)

In the MAX793/MAX794, the watchdog circuit monitors
the µP’s activity. If the µP does not toggle the watchdog
input (WDI) within 1.6s, WDO goes low. The internal

1.6s timer is cleared and WDO returns high either when

3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits

10 ______________________________________________________________________________________

Figure 3. MAX794 Standard Application Circuit

Figure 4. Battery Freshness Seal Enable Timing

(OPTIONAL)

3.6V

3.3V

R1

R2

+5V

0.1µF

0.1µF

+5V SUPPLY

FAILURE

Si9433DY

SILICONIX

D

V

BATT ON

CC

RESET IN

BATT

WDO

MR

PFO

MAX794

S

PMOS

OUT

CE OUT

CE IN

WDI

LOWLINE

RESET

0.1µF

CMOS

RAM

ADDRESS
DECODER

V

CC

4.7kΩ

V

CC

A0-A15

I/O

NMI

RESET

V

CC

RESET

PFO
(EXTERNALLY HELD AT 0V)

RESET PULLED UP TO V

V

RST V

CC

t

RP

PFO STATE LATCHED,
FRESHNESS SEAL ENABLED.

RST

PFI

GND

V

RST

R1

=

V

RST IN

+ 1

(

)

R2

a reset occurs or when a transition (low-to-high or high­to-low) takes place at WDI. As long as reset is assert­ed, the timer remains cleared and does not count. As
soon as reset is released or WDI changes state, the
timer starts counting (Figure 5). WDI can detect pulses
as short as 100ns. Unlike the 5V MAX690 family, the
watchdog function cannot be disabled.

Watchdog Output (MAX793/MAX794)

In the MAX793/MAX794, WDO remains high (WDO is
pulled up to VCC) if there is a transition or pulse at WDI
during the watchdog timeout period. WDO goes low if
no transition occurs at WDI during the watchdog timeout
period. The watchdog function is disabled and WDO is
a logic high when reset is asserted if VCCis above VSW.
WDO is a logic low when VCCis below VSW.

If a system reset is desired on every watchdog fault,
simply diode-OR connect WDO to MR (Figure 6).
When a watchdog fault occurs in this mode, WDO goes
low, pulling MR low, which causes a reset pulse to be
issued. Ten microseconds after reset is asserted, the
watchdog timer clears and WDO returns high. This
delay results in a 10µs pulse at WDO, allowing external
circuitry to capture a watchdog fault indication. A con­tinuous high or low on WDI causes 200ms reset pulses
to be issued every 1.6s.

Chip-Enable Signal Gating

Internal gating of chip-enable (CE) signals prevents erro­neous data from corrupting CMOS RAM in the event of an
undervoltage condition. The MAX793/MAX794/MAX795
use a series transmission gate from CE IN to CE OUT
During normal operation (reset not asserted), the CE
transmission gate is enabled and passes all CE transi­tions. When reset is asserted, this path becomes dis­abled, preventing erroneous data from corrupting the
CMOS RAM. The short CE propagation delay from CE IN
to CE OUT enables these µP supervisors to be used with
most µPs. If CE IN is low when reset asserts, CE OUT
remains low for typically 10µs to permit completion of the
current write cycle.

Chip-Enable Input

The CE transmission gate is disabled and CE IN is high
impedance (disabled mode) while reset is asserted.
During a power-down sequence when VCCpasses the
reset threshold, the CE transmission gate disables and
CE IN immediately becomes high impedance if the volt­age at CE IN is high. If CE IN is low when reset asserts,
the CE transmission gate disables at the moment CE IN
goes high, or 10µs after reset asserts, whichever
occurs first (Figure 8). This permits the current write
cycle to complete during power-down.

MAX793/MAX794/MAX795

3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits

______________________________________________________________________________________ 11

V

Figure 5. Watchdog Timing Relationship

Figure 6. Generating a Reset on Each Watchdog Fault

CC

RESET

V

V

RST

t

RP

CC

MAX793/MAX794

WDO

MR

RESET

4.7kΩ

TO µP

WDO

t

WD

WDI

WDO CONNECTED TO µP INTERRUPT
RESET PULLED UP TO V

CC

V

CC

t

RP

∼10µs

WDO

t

RESET

WDI

RP

t

WP

MAX793/MAX794/MAX795

The CE transmission gate remains disabled and CE IN
remains high impedance (regardless of CE IN activity)
for the first half of the reset timeout period (tRP/ 2), any
time a reset is generated. While disabled, CE IN is high
impedance. When the CE transmission gate is enabled,
the impedance of CE IN appears as a 46Ω resistor in
series with the load at CE OUT.

The propagation delay through the CE transmission
gate depends on V

CC

, the source impedance of the

drive connected to CE IN, and the loading on CE OUT.
The CE propagation delay is production tested from the
50% point on CE IN to the 50% point on CE OUT using
a 50Ω driver and 50pF of load capacitance (Figure 9).
For minimum propagation delay, minimize the capaci­tive load at CE OUT and use a low-output-impedance
driver.

Chip-Enable Output

When the CE transmission gate is enabled, the imped­ance of CE OUT is equivalent to a 46Ω resistor in series
with the source driving CE IN. In the disabled mode,
the transmission gate is off and an active pullup con­nects CE OUT to OUT (Figure 8). This pullup turns off
when the transmission gate is enabled.

Early Power-Fail Warning

(MAX793/MAX794)

Critical systems often require an early warning indicat­ing that power is failing. This warning provides time for
the µP to store vital data and take care of any additional
“housekeeping” functions, before the power supply
gets too far out of tolerance for the µP to operate reli­ably. The MAX793/MAX794 offer two methods of
achieving this early warning. If access to the unregulat­ed supply is feasible, the power-fail comparator input
(PFI) can be connected to the unregulated supply
through a voltage divider, with the power-fail compara­tor output (PFO) providing the NMI to the µP (Figure

3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits

12 ______________________________________________________________________________________

Figure 7. Chip-Enable Transmission Gate

Figure 8. Chip-Enable Timing

MAX793
MAX794
MAX795

CHIP-ENABLE

OUTPUT

CONTROL

OUT

P

RESET

GENERATOR

CE IN

P

CE OUT

N

V

RST

V

CC

V

RST

V

SW

V

RST

V

RST

V

SW

CE OUT

V

BATT

t

RESET
(PULLED TO VCC)

CE IN

V

= 3.6V

BATT

RESET PULLED UP TO V

RP

/2

t

RP

CC

10µs

V

BATT

V

CC

MAX793/MAX794/MAX795

3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits

______________________________________________________________________________________ 13

10). If there is no easy access to the unregulated sup­ply, the LOWLINE output can be used to generate an
NMI to the µP (see

LOWLINE Output

section).

LLOOWWLLIINNEE

Output (MAX793/MAX794)

The low-line comparator monitors VCCwith a threshold
voltage typically 45mV above the reset threshold (10mV
of hysteresis) for the MAX793, and 15mV above RESET
IN (4mV of hysteresis) for the MAX794. For normal
operation (V

CC

above the reset threshold), LOWLINE is

pulled to V

CC

. Use LOWLINE to provide an NMI to the

µP when power begins to fall.

In most battery-operated portable systems, reserve
energy in the battery provides ample time to complete
the shutdown routine once the low-line warning is
encountered and before reset asserts. If the system
must also contend with a more rapid V

CC

fall time, such
as when the main battery is disconnected or a high­side switch is opened during normal operation, use
capacitance on the VCCline to provide time to execute
the shutdown routine (Figure 11).

First, calculate the worst-case time required for the sys­tem to perform its shutdown routine. Then, with the worst­case shutdown time, the worst-case load current, and the
minimum low-line to reset threshold (VLRmin), calculate
the amount of capacitance required to allow the shut­down routine to complete before reset is asserted:

C

HOLD

> I

LOAD

x t

SHDN

/ V

LR

where I

LOAD

is the current being drained from the
capacitor, VLRis the low-line to reset threshold differ­ence (VLL- V

RST

), and t

SHDN

is the time required for

the system to complete an orderly shutdown routine.

Power-Fail Comparator (MAX793/MAX794)

The MAX793/MAX794’s PFI input is compared to an
internal reference. If PFI is less than the power-fail
threshold (V

PFT

), PFO goes low. The power-fail com-

parator is intended for use as an undervoltage detector
to signal a failing power supply (Figure 12). However,
the comparator does not need to be dedicated to this
function because it is completely separate from the rest
of the circuitry.

Figure 9. CE Propagation Delay Test Circuit

Figure 10. Using the Power-Fail Comparator to Generate
Power-Fail Warning

Figure 11. Using LOWLINE to Provide Power-Fail Warning
to the µP

V

CC

V

CC

3.6V

25Ω EQUIVALENT
SOURCE IMPEDANCE

50Ω CABLE

50Ω

50Ω

INCLUDES LOAD CAPACITANCE AND SCOPE PROBE CAPACITANCE.

*C

L

BATT

CE IN

MAX793
MAX794
MAX795

GND

CE OUT

50pF
C

*

L

UNREGULATED
SUPPLY

REGULATOR

R1

R2

3.0V OR 3.3V

V

CC

MAX793
MAX794

PFI

PFO

GND

TO µP NMI

> I

3.0V OR 3.3V

C

HOLD

x t

LOAD

LR

SHDN

V

CC

LOWLINE

MAX793
MAX794

GND

TO µP NMI

REGULATOR

C

HOLD

V

MAX793/MAX794/MAX795

3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits

14 ______________________________________________________________________________________

The power-fail comparator turns off and PFO goes low
when VCCfalls below VSWon power-down. During the
first half of the reset timeout period (tRP), PFO is forced
high, irrespective of V

PFI

. At the beginning of the sec-

ond half of tRP, the power-fail comparator is enabled
and PFO follows PFI. If the comparator is unused, con­nect PFI to VCCand leave PFO unconnected. PFO can
be connected to MR so that a low voltage on PFI gener­ates a reset (Figure 12b). In this configuration, when
the monitored voltage causes PFI to fall below V

PFT

,

PFO pulls MR low, causing a reset to be asserted.
Reset remains asserted as long as PFO holds MR low,
and for 200ms after PFO pulls MR high when the moni­tored supply is above the programmed threshold.

Backup-Battery Switchover

In the event of a brownout or power failure, it may be
necessary to preserve the contents of RAM. With a
backup battery installed at BATT, the devices automati­cally switch RAM to backup power when VCCfalls. In
order to allow the backup battery (e.g., a 3.6V lithium
cell) to have a higher voltage than VCC, this family of µP
supervisors (designed for 3.3V and 3V systems) does
not always connect BATT to OUT when V

BATT

is
greater than VCC. BATT connects to OUT (through a
140Ω switch) either when VCCfalls below VSWand

V

BATT

is greater than VCC, or when VCCfalls below

1.75V (typ) regardless of the BATT voltage.

Switchover at VSWensures that battery-backup mode is
entered before V

OUT

gets too close to the 2.0V mini­mum required to reliably retain data in most CMOS
RAM, (switchover at higher VCCvoltages would
decrease backup-battery life). When VCCrecovers,
switchover is deferred either until VCCcrosses V

BATT

if

V

BATT

is below V

RST

, or when VCCrises above the

reset threshold (V

RST

) if V

BATT

is above V

RST

. This
power-up switchover technique prevents VCCfrom
charging the backup battery through OUT when using
an external transistor driven by BATT ON. OUT con­nects to VCCthrough a 4Ω (max) PMOS power switch
when VCCcrosses the reset threshold (Figure 13).

BATT ON (MAX793/MAX794)

BATT ON is high when OUT is connected to BATT.
Although BATT ON can be used as a logic output to
indicate the battery switchover status, it is most often
used as a gate or base drive for an external pass tran­sistor for high-current applications (see

Driving an

External Switch with BATT ON

in the

Applications

Information

section). When VCCexceeds V

RST

on
power-up, BATT ON sinks 3.2mA at 0.4V. In battery­backup mode, this terminal sources 100µA from BATT.

Figure 12. Using the Power-Fail Comparator to Monitor an Additional Power Supply: (a) VINIs Negative, (b) VINIs Positive

PFO

V

CC

V

TRIP

VH = (V

R1

R2

V

=

PFT

PFT + VPFH

IN

PFI PFO

V

TRIPVH

R1

R2

+

(

)

R2

R1

R2

+

)

(

)

R2

3.0V OR 3.3V

V

R1

PFI PFO

R2

V

CC

TRIP

IN

1

1

= R2

(V

+ V

PFT

= R2

(V

V

L

)

PFT

(

+

)

PFH

(

R1

R2

1

1

+

–

)

R1

R2

V

V

CC

MAX793
MAX794

GND

V

PFO

V

V

PFT

V

PFH

TRIP, VL

IN

= 1.237V
= 10mV

ARE NEGATIVE

V

V

TRIP

L

V

CC

–

)

R1

V

CC

R1

0V

WHERE

NOTE: V

V

CC

MAX793
MAX794

GND

3.0V OR 3.3V

(b)(a)

MR

V

IN

__________Applications Information

These µP supervisory circuits are not short-circuit pro­tected. Shorting V

OUT

to ground, excluding power-up
transients such as charging a decoupling capacitor,
destroys the device. Decouple both VCCand BATT
pins to ground by placing 0.1µF ceramic capacitors as
close to the device as possible.

Driving an External Switch with BATT ON

BATT ON can be directly connected to the base of a
PNP transistor or the gate of a PMOS transistor. The
PNP connection is straightforward: connect the emitter

to V

CC

, the collector to OUT, and the base to BATT ON
(Figure 14a). No current-limiting resistor is required, but
a resistor connecting the base of the PNP to BATT ON
can be used to limit the current drawn from VCC, pro­longing battery life in portable equipment.

If you are using a PMOS transistor, however, it must be
connected backwards from the traditional method.
Connect the gate to BATT ON, the drain to VCC, and
the source to OUT (Figure 14b). This method orients
the body diode from VCCto OUT and prevents the
backup battery from discharging through the FET when
its gate is high. Two PMOS transistors in the Siliconix
LITTLE FOOT®series are specified with VGSdown to

-2.7V. The Si9433DY has a maximum 100mΩ drain­source on-resistance with 2.7V of gate drive and a 2A
drain-source current. The Si9434DY specifies a 60mΩ
drain-source on-resistance with 2.7V of gate drive and
a 5.1A drain-source current.

Using a Super Cap as a Backup

Power Source

Super caps are capacitors with extremely high capaci­tance values (e.g., order of 0.47F) for their size. Figure
15 shows two ways to use a super cap as a backup
power source. The super cap can be connected
through a diode to the 3V input (Figure 15a); or, if a 5V
supply is also available, the super cap can be charged
up to the 5V supply (Figure 15b), allowing a longer
backup period. Since V

BATT

can exceed V

CC

while
VCCis above the reset threshold, there are no special
precautions when using these µP supervisors with a
super cap.

Operation without a

Backup Power Source

These µP supervisors were designed for battery­backed applications. If a backup battery is not used,
connect BATT, OUT, and VCCtogether, or use a differ­ent µP supervisor.

Replacing the Backup Battery

The backup power source can be removed while V

CC

remains valid, without danger of triggering a reset
pulse, provided that BATT is decoupled with a 0.1µF
capacitor to ground. As long as VCCstays above the
reset threshold, battery-backup mode cannot be
entered.

MAX793/MAX794/MAX795

3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits

______________________________________________________________________________________ 15

CE IN

High impedance

CE OUT

Pulled to BATT

RESET

Logic low

BATT Connected to OUT

LOWLINE

Logic low

RESET Pulled up to V

CC

WDO

Logic low

WDI Disabled

BATT OK Logic low

PFO

Logic low

MR

Disabled, but still pulled up to V

CC

PFI Disabled

V

CC

Disconnected from OUT

BATT ON Pulled up to BATT

OUT

Connected to BATT through an internal
140Ω switch

PIN NAME STATUS

Table 1. Input and Output Status in
Battery-Backup Mode

Figure 13. Battery Switchover Timing

LITTLE FOOT is a registered trademark of Siliconix Inc.

3.6V

3.3V

V

SW

V

RST

V

CC

3.6V

V

OUT

V

= 3.6V

BATT

3.3V

MAX793/MAX794/MAX795

Adding Hysteresis to the Power-Fail

Comparator (MAX793/MAX794)

The power-fail comparator has a typical input hystere­sis of 10mV. This is sufficient for most applications
where a power-supply line is being monitored through
an external voltage divider (see the section

Monitoring

an Additional Power Supply

).

If additional noise margin is desired, connect a resistor
between PFO and PFI as shown in Figure 16a. Select
the ratio of R1 and R2 such that PFI sees V

PFT

when

VINfalls to its trip point (V

TRIP

). R3 adds the additional
hysteresis and should typically be more than 10 times
the value of R1 or R2. The hysteresis window extends

both above (V

H

) and below (VL) the original trip point

(V

TRIP

).

Connecting an ordinary signal diode in series with R3,
as shown in Figure 16b, causes the lower trip point (VL)
to coincide with the trip point without hysteresis (V

TRIP

),

so the entire hysteresis window occurs above V

TRIP

.
This method provides additional noise margin without
compromising the accuracy of the power-fail threshold
when the monitored voltage is falling. It is useful for
accurately detecting when a voltage falls past a thresh­old. The current through R1 and R2 should be at least
1µA to ensure that the 25nA (max over temperature)
PFI input current does not shift the trip point. R3 should
be larger than 82kΩ so it does not load down the PFO
pin. Capacitor C1 is optional, and adds noise rejection.

3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits

16 ______________________________________________________________________________________

Figure 14. Driving an External Transistor with BATT ON

Figure 15. Using a Super Cap as a Backup Source

3.0V OR 3.3V

BATT ONV

CC

OUT

TO CMOS RAM

CC

D

BATT ONV

PMOS FET

BODY DIODE

S

G

OUT

MAX793
MAX794
MAX795

GND

3.0V OR 3.3V

V

1N4148

BATT

0.47F

MAX793

CC

MAX794

GND

OUT

RESET

V

CC

TO STATIC
RAM

TO µP

MAX793
MAX794
MAX795

GND

(b)(a)

+5V

3.0V OR

1N4148

0.47F

(b)(a)

3.3V

V

BATT

MAX793

CC

MAX794

GND

OUT

RESET

V

CC

TO STATIC
RAM

TO µP

Monitoring an Additional Power Supply

These µP supervisors can monitor either positive or
negative supplies using a resistor voltage divider to
PFI. PFO can be used to generate an interrupt to the µP
or to cause reset to assert (Figure 12).

Interfacing to µPs with

Bidirectional Reset Pins

Since the RESET output is open drain, the MAX793/
MAX794/MAX795 interface easily with µPs that have
bidirectional reset pins, such as the Motorola 68HC11.
Connecting the RESET output of the µP supervisor
directly to the RESET input of the microcontroller with a
single pullup resistor allows either device to assert
reset (Figure 17).

Negative-Going V

CC

Transients

These supervisors are relatively immune to short-dura­tion negative-going VCCtransients (glitches) while issu­ing resets to the µP during power-up, power-down, and
brownout conditions. Therefore, resetting the µP when
VCCexperiences only small glitches is usually not rec­ommended.

MAX793/MAX794/MAX795

3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits

______________________________________________________________________________________ 17

Figure 16. Adding Hysteresis to the Power-Fail Comparator: (a) Symmetrical Hysteresis, (b) Hysteresis Only on Rising V

IN

Figure 17. Interfacing to µPs with Bidirectional Reset I/O

V

IN

R1

R2 R3

C1*

PFO

0V

0V

= (V

= R1

R1 + R2

= V

(

)

PFT

+ V

PFT

PFH

( )

VPFT

V

TRIP

V

H

V

L

PFI

PFO

TO µP

V

L

V

TRIP

R2

1

) (R1)

1
R1

1

+

+

( )

R1

R2

1

1

+

+

R2

–

R3

V

MAX793
MAX794

GND

1
R3

V

CC

R3

CC

V

H

WHERE

*OPTIONAL

V

= 1.237V

PFT

V

= 10mV

PFH

V

IN

R1

R2 R3

C1*

TO µP

PFO

V

IN

(b)(a)

0V

V

TRIP

V

H

WHERE

0V

= V

= R1 (V

V

TRIP

R1 + R2

(

PFT

V
V

VD

V

)

R2

1

+ V

PFT

= 1.237V

PFT

= 10mV

PFH

= DIODE FORWARD VOLTAGE DROP
= V

L

+

( )

PFH)

R1

TRIP

PFI

PFO

1
R2

+

MAX793
MAX794

1

R3

V

GND

–

CC

*OPTIONAL

V

V

H

V

D

R3

IN

V

CC

RESET

GENERATOR

V

CC

RESET

N

RESET

V

CC

µP

MAX793
MAX794
MAX795

GND

GND

MAX793/MAX794/MAX795

Figure 18 shows maximum transient duration vs. reset­comparator overdrive, for which reset pulses are not
generated. The graph was produced using negative­going VCCpulses, starting at 3.3V and ending below
the reset threshold by the magnitude indicated (reset
comparator overdrive). The graph shows the maximum
pulse width a negative-going VCCtransient can typically
have without causing a reset pulse to be issued. As
the amplitude of the transient increases (i.e., goes far­ther below the reset threshold), the maximum allowable
pulse width decreases. Typically, a V

CC

transient that
goes 40mV below the reset threshold and lasts for 10µs
or less does not cause a reset pulse to be issued.

A 0.1µF bypass capacitor mounted close to the V

CC

pin provides additional transient immunity.

Watchdog Software Considerations

There is a way to help the watchdog timer monitor soft­ware execution more closely, which involves setting
and resetting the watchdog input at different points in
the program rather than pulsing the watchdog input
high-low-high or low-high-low. This technique avoids a
stuck loop, in which the watchdog timer would continue
to be reset within the loop, keeping the watchdog from
timing out. Figure 19 shows an example of a flow dia­gram where the I/O driving the watchdog input is set
high at the beginning of the program, set low at the
beginning of every subroutine or loop, then set high
again when the program returns to the beginning. If the
program should hang in any subroutine, the problem
would quickly be corrected, since the I/O is continually
set low and the watchdog timer is allowed to time out,
causing a reset or interrupt to be issued.

3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits

18 ______________________________________________________________________________________

Figure 18. Maximum Transient Duration without Causing a
Reset Pulse vs. Reset Comparator Overdrive

Figure 19. Watchdog Flow Diagram

100

90

80

70

60

50

40

30

20

MAXIMUM PULSE DURATION (µs)

10

0

10 20 30 100

RESET COMPARATOR OVERDRIVE, V

40 50 60 70 80 90

- VCC (mV)

RST

MAX793-FIG 18

START

SET WDI

HIGH

PROGRAM

CODE

Subroutine or

Program Loop

SET WDI LOW

RETURN

MAX793/MAX794/MAX795

3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits

______________________________________________________________________________________ 19

_________________Pin Configurations

Chip Information

TRANSISTOR COUNT: 1271

_Ordering Information (continued)

*

The MAX793/MAX795 offer a choice of reset threshold voltage.
Select the letter corresponding to the desired reset threshold
voltage range (T = 3.00V to 3.15V, S = 2.85V to 3.00V, R =

2.55V to 2.70V) and insert it into the blank to complete the part
number. The MAX794’s reset threshold is adjustable.

Devices are available in both leaded and lead-free packaging.
Specify lead free by adding the + symbol at the end of the part
number when ordering.

Package Information

For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages

. Note that a “+”, “#”, or “-” in
the package code indicates RoHS status only. Package draw­ings may show a different suffix character, but the drawing per­tains to the package regardless of RoHS status.

PACKAGE TYPE PACKAGE CODE DOCUMENT NO.

8 SO S8-2

21-0041

8 Plastic Dip R8-1

21-0043

16 Plastic Dip P16-1

21-0043

16 Narrow SO S16-1

21-0041

PART* TEMP RANGE

MAX793_EPE -40°C to +85°C 16 Plastic DIP

MAX793_ESE -40°C to +85°C 16 Narrow SO

MAX794CPE 0°C to +70°C 16 Plastic DIP

MAX794CSE 0°C to +70°C 16 Narrow SO

MAX794EPE -40°C to +85°C 16 Plastic DIP

MAX794ESE -40°C to +85°C 16 Narrow SO

MAX795_CPA 0°C to +70°C 8 Plastic DIP

MAX795_CSA 0°C to +70°C 8 SO

MAX795_EPA -40°C to +85°C 8 Plastic DIP

MAX795_ESA -40°C to +85°C 8 SO

PIN­PACKAGE

TOP VIEW

OUT

(RESET IN) BATT OK

BATT ON

GND

BATT ON

GND

( ) ARE FOR MAX794

V

PFI

PFO

MR

OUT

V

1

2

CC

3

4

5

6

7

8

1

2

CC

3

4

MAX793
MAX794

DIP/Narrow SO

MAX795

DIP/SO

16

15

14

13

12

11

10

9

8

7

6

5

BATT

RESET

LOWLINE

RESET

CE OUT

CE IN

WDI

WDO

BATT

RESET

CE OUT

CE IN

MAX793/MAX794/MAX795

3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

20

____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

© 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

Revision History

REVISION

NUMBER

0 2/95 Initial release —

5 2/07 Revised Electrical Characteristics.4

6 3/10 Revised Absolute Maximum Ratings and Chip-Enable Input section. 1, 2

REVISION

DATE

DESCRIPTION

PAGES

CHANGED