MAXIM MAX7456 Technical data
MAX7456
Single-Channel Monochrome On-Screen
Display with Integrated EEPROM
________________________________________________________________ Maxim Integrated Products 1
19-0576; Rev 0; 8/07
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
General Description
The MAX7456 single-channel monochrome on-screen
display (OSD) generator lowers system cost by eliminating the need for an external video driver, sync separator, video switch, and EEPROM. The MAX7456 serves
all national and international markets with 256 user-programmable characters in NTSC and PAL standards.
The MAX7456 easily displays information such as company logo, custom graphics, time, and date with arbitrary characters and sizes. The MAX7456 is preloaded
with 256 characters and pictographs and can be reprogrammed in-circuit using the SPITMport.
The MAX7456 is available in a 28-pin TSSOP package
and is fully specified over the extended (-40°C to
+85°C) temperature range.
Applications
Security Switching Systems
Security Cameras
Industrial Applications
In-Cabin Entertainment
Consumer Electronics
Features
♦ 256 User-Defined Characters or Pictographs in
Integrated EEPROM
♦ 12 x 18 Pixel Character Size
♦ Blinking, Inverse, and Background Control
Character Attributes
♦ Selectable Brightness by Row
♦ Displays Up to 16 Rows x 30 Characters
♦ Sag Compensation On Video-Driver Output
♦ LOS, VSYNC, HSYNC, and Clock Outputs
♦ Internal Sync Generator
♦ NTSC and PAL Compatible
♦ SPI-Compatible Serial Interface
♦ Delivered with Preprogrammed Character Set
Ordering Information
PART
PKG
CODE
MAX7456EUI+
English/
Japanese
U28E-5
*EP = Exposed pad.
+Denotes a lead-free package.
Note: This device is specified over the -40°C to +85°C operating temperature range.
Pin Configuration appears at end of data sheet.
SERIAL
INTERFACE
DISPLAY
ADDRESS
VIDEO
DRIVER
VIDEO
TIMING
GENERATOR
DISPLAY
MEMORY
(SRAMS)
CHARACTER
ADDRESS
PIXEL
CODE
SYNC
PIXEL
CONTROL
CHARACTER
MEMORY
(NVM)
OSD
GENERATOR
SAG
NETWORK
OSD
MUX
DAC
SYSTEM
CLOCK
POR
SYNC
SEPARATOR
XTAL
OSCILLATOR
CLAMP
VIN
CLKIN
XFB
CLKOUT
RESET
HSYNC
VSYNC
LOS
CS
SCLK
SDIN
SDOUT
AVDD
AGND
DVDD
DGND
PVDD
PGND
VOUT
SAG
MAX7456
Simplified Functional Diagram
SPI is a trademark of Motorola, Inc.
EVALUATION KIT
AVAILABLE
PIN-PACKAGE LANGUAGE
28 TSSOP-EP*
MAX7456
Single-Channel Monochrome On-Screen
Display with Integrated EEPROM
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDD to AGND ........................................................-0.3V to +6V
DVDD to DGND ........................................................-0.3V to +6V
PVDD to PGND.........................................................-0.3V to +6V
AGND to DGND.....................................................-0.3V to +0.3V
AGND to PGND .....................................................-0.3V to +0.3V
DGND to PGND.....................................................-0.3V to +0.3V
VIN, VOUT, SAG to AGND......................-0.3V to (V
AVDD
+ 0.3V)
HSYNC, VSYNC, LOS to AGND ...............................-0.3V to +6V
RESET to AGND .....................................-0.3V to (V
AVDD
+ 0.3V)
CLKIN, CLKOUT, XFB to DGND ............-0.3V to (V
DVDD
+ 0.3V)
SDIN, SCLK, CS, SDOUT to DGND........-0.3V to (V
DVDD
+ 0.3V)
Maximum Continuous Current into V
OUT
........................±100mA
Continuous Power Dissipation (T
A
= +70°C)
28-Pin TSSOP (derate 27mW/°C above +70°C).......2162mW*
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
ELECTRICAL CHARACTERISTICS
(V
AVDD
= +4.75V to +5.25V, V
DVDD
= +4.75V to +5.25V, V
PVDD
= +4.75V to +5.25V, TA= T
MIN
to T
MAX
. Typical values are at V
AVDD
= V
DVDD
= V
PVDD
= +5V, TA= +25°C, unless otherwise noted.) (Note 1)
PARAMETER
CONDITIONS MIN
UNITS
POWER SUPPLIES
Analog Supply Voltage V
AVDD
5 5.25 V
Digital Supply Voltage V
DVDD
5 5.25 V
Driver Supply Voltage V
PVDD
5 5.25 V
Analog Supply Current I
AVDD
VIN = 1V
P-P
(100% white flat field signal),
VOUT load, R
L
= 150Ω
24 35 mA
Digital Supply Current I
DVDD
VIN = 1V
P-P
(100% white flat field signal),
VOUT load, R
L
= 150Ω
25 30 mA
Driver Supply Current I
PVDD
VIN = 1V
P-P
(100% white flat field signal),
VOUT load, R
L
= 150Ω
58 80 mA
NONVOLATILE MEMORY
Data Retention TA = +25°C 100 Years
Endurance TA = +25°C
Stores
DIGITAL INPUTS (CS, SDIN, RESET, SCLK)
Input High Voltage V
IH
2.0 V
Input Low Voltage V
IL
0.8 V
Input Hysteresis V
HYS
50 mV
Input Leakage Current VIN = 0 or V
DVDD
±10 µA
Input Capacitance C
IN
5pF
DIGITAL OUTPUTS (SDOUT, CLKOUT, VSYNC, HSYNC, LOS)
Output High Voltage V
OH
I
SOURCE
= 4mA (SDOUT, CLKOUT) 2.4 V
Output Low Voltage V
OL
I
SINK
= 4mA 0.45 V
Tri-State Leakage Current SDOUT, CS = V
DVDD
±10 µA
*As per JEDEC51 Standard (Multilayer Board).
SYMBOL
TYP MAX
4.75
4.75
4.75
100,000
MAX7456
Single-Channel Monochrome On-Screen
Display with Integrated EEPROM
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= +4.75V to +5.25V, V
DVDD
= +4.75V to +5.25V, V
PVDD
= +4.75V to +5.25V, TA= T
MIN
to T
MAX
. Typical values are at V
AVDD
= V
DVDD
= V
PVDD
= +5V, TA= +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS MIN
TYP
MAX
UNITS
CLOCK INPUT (CLKIN)
Clock Frequency 27 MHz
Clock-Pulse High 14 ns
Clock-Pulse Low 14 ns
Input High Voltage
0.7 x
V
Input Low Voltage
0.3 x
V
Input Leakage Current VIN = 0V or V
DVDD
±50 µA
CLOCK OUTPUT (CLKOUT)
Duty Cycle 5pF and 10kΩ to DGND 40 50 60 %
Rise Time 5pF and 10kΩ to DGND 3 ns
Fall Time 5pF and 10kΩ to DGND 3 ns
VIDEO CHARACTERISTICS
DC Power-Supply Rejection
V
AVDD
= V
DVDD
= V
PVDD
= 5V;
V
IN
= 1V
P-P
, measured at VOUT
40 dB
AC Power-Supply Rejection
V
AVDD
= V
DVDD
= V
PVDD
= 5V;
V
IN
= 1V
P-P
, measured at VOUT;
f = 5MHz; power-supply ripple = 0.2V
P-P
30 dB
Short-Circuit Current VOUT to PGND 230 mA
Line-Time Distortion LTD Figures 1a, 1b 0.5 %
Output Impedance Z
OUT
Figures 1a, 1b 0.2 Ω
Gain Figures 1a, 1b
2.0 2.11 V/V
Black Level At VOUT, Figures 1a, 1b
AGND
V
Input-Voltage Operating Range
V
IN
Figures 1a, 3 (Note 2) 0.5 1.2 V
P-P
Input-Voltage Sync Detection
Range
V
INSD
Figures 1a, 3 (Note 3) 0.5 2.0 V
P-P
Maximum Output-Voltage Swing
V
OUT
Figures 1a, 1b 2.4 V
P-P
Output-Voltage Sync Tip Level 0.7 V
Large Signal Bandwidth (0.2dB)
BW V
OUT
= 2V
P-P
, Figures 1a, 1b 6 MHz
VIN to VOUT Delay 30 ns
Differential Gain DG 0.5 %
Differential Phase DP 0.5
Degrees
OSD White Level
VOUT 100% white level with respect to
black level
1.45 V
Horizontal Pixel Jitter Between consecutive horizontal lines 24 ns
Video Clamp Settling Time 32 Lines
V
DVDD
1.89
V
DVDD
+ 1.5
1.25 1.33
MAX7456
Single-Channel Monochrome On-Screen
Display with Integrated EEPROM
4 _______________________________________________________________________________________
TIMING CHARACTERISTICS
(V
AVDD
= +4.75V to +5.25V, V
DVDD
= +4.75V to +5.25V, V
PVDD
= +4.75V to +5.25V, TA= T
MIN
to T
MAX
. Typical values are at V
AVDD
= V
DVDD
= V
PVDD
= +5V, TA= +25°C, unless otherwise noted.) (Note 1)
PARAMETER
CONDITIONS MIN
UNITS
SPI TIMING
SCLK Period t
CP
100 ns
SCLK Pulse-Width High t
CH
40 ns
SCLK Pulse-Width Low t
CL
40 ns
CS Fall to SCLK Rise Setup t
CSS0
30 ns
CS Fall After SCLK Rise Hold t
CSH0
0ns
CS Rise to SCLK Setup t
CSS1
30 ns
CS Rise After SCLK Hold t
CSH1
0ns
CS Pulse-Width High t
CSW
100 ns
SDIN to SCLK Setup t
DS
30 ns
SDIN to SCLK Hold t
DH
0ns
SDOUT Valid Before SCLK t
DO1
20pF to ground 25 ns
SDOUT Valid After SCLK t
DO2
20pF to ground 0 ns
CS High to SDOUT High
Impedance
t
DO3
20pF to ground 300 ns
CS Low to SDOUT Logic Level t
DO4
20pF to ground 20 ns
HSYNC, VSYNC, AND LOS TIMING
LOS, VSYNC, and HSYNC Valid
before CLKOUT Rising Edge
t
DOV
20pF to ground 30 ns
NTSC external sync mode, Figure 4 375
VOUT Sync to VSYNC Falling
Edge Delay
PAL external sync mode, Figure 6 400
ns
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= +4.75V to +5.25V, V
DVDD
= +4.75V to +5.25V, V
PVDD
= +4.75V to +5.25V, TA= T
MIN
to T
MAX
. Typical values are at V
AVDD
= V
DVDD
= V
PVDD
= +5V, TA= +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS MIN
TYP
MAX
UNITS
OSD CHARACTERISTICS
OSD Rise Time
OSD insertion mux register
OSDM[5,4,3] = 011b
60 ns
OSD Fall Time
OSD insertion mux register
OSDM[5,4,3] = 011b
60 ns
OSD insertion mux register
OSDM[2,1,0] = 011b
75 ns
OSD Insertion Mux Switch Time
SYMBOL
TYP MAX
t
VOUT-VSF
MAX7456
Single-Channel Monochrome On-Screen
Display with Integrated EEPROM
_______________________________________________________________________________________ 5
Note 1: See the standard test circuits of Figure 1. RL= 75Ω, unless otherwise specified. All digital input signals are timed from a
voltage level of (V
IH
+ VIL) / 2. All parameters are tested at TA= +85°C and values through temperature range are guaran-
teed by design.
Note 2: The input-voltage operating range is the input range over which the output signal parameters are guaranteed (Figure 3).
Note 3: The input-voltage sync detection range is the input composite video range over which an input sync signal is properly
detected and the OSD signal appears at VOUT. However, the output voltage specifications are not guaranteed for input signals exceeding the maximum specified in the input operating voltage range (Figure 3).
TIMING CHARACTERISTICS (continued)
(V
AVDD
= +4.75V to +5.25V, V
DVDD
= +4.75V to +5.25V, V
PVDD
= +4.75V to +5.25V, TA= T
MIN
to T
MAX
. Typical values are at V
AVDD
= V
DVDD
= V
PVDD
= +5V, TA= +25°C, unless otherwise noted.) (Note 1)
PARAMETER
CONDITIONS MIN
UNITS
NTSC external sync mode, Figure 4 400
VOUT Sync to VSYNC Rising
Edge Delay
PAL external sync mode, Figure 6 425
ns
NTSC internal sync mode, Figure 5 40
VSYNC Falling Edge to VOUT
Sync Delay
PAL internal sync mode, Figure 7 45
ns
NTSC internal sync mode, Figure 5 32
VSYNC Rising Edge to VOUT
Sync Delay
PAL internal sync mode, Figure 7 30
ns
VOUT Sync to HSYNC Falling
Edge Delay
NTSC and PAL external sync mode,
Figure 8
310 ns
VOUT Sync to HSYNC Rising
Edge Delay
NTSC and PAL external sync mode,
Figure 8
325 ns
HSYNC Falling Edge to VOUT
Sync Delay
NTSC and PAL internal sync mode,
Figure 9
115 ns
HSYNC Rising Edge to VOUT
Sync Delay
NTSC and PAL internal sync mode,
Figure 9
115 ns
All Supplies High to CS Low t
PUD
Power-up delay 50 ms
NVM Write Busy t
NVW
12 ms
Figure 1. Standard Test Circuits
SYMBOL
t
VOUT-VSR
t
VSF-VOUT
t
VSR-VOUT
t
VOUT-HSF
t
VOUT-HSR
t
HSF-VOUT
t
HSR-VOUT
TYP MAX
SIGNAL
GEN
R
75Ω
IN
C
IN
0.1µF
VIN
a) INPUT TEST CIRCUIT
MAX7456
VOUT
C
MAX7456
SAG
L
22pF
b) ONE STANDARD VIDEO LOAD, DC-COUPLED
R
L
150Ω
MAX7456
Single-Channel Monochrome On-Screen
Display with Integrated EEPROM
6 _______________________________________________________________________________________
IMAGE WITH ON-SCREEN GRAPHICS
MAX7456 toc01
10µs/div
100% COLOR BARS RESPONSE
CVBS OUT
(200mV/div)
MAX7456 toc02
75% COLOR BARS VECTOR DIAGRAM
CVBS OUT
MAX7456 toc03
10µs/div
60% MULTIBURST RESPONSE
CVBS OUT
(200mV/div)
MAX7456 toc04
Typical Operating Characteristics
(V
AVDD
= +5V, V
DVDD
= +5V, V
PVDD
= +5V, TA= +25°C, unless otherwise noted. See the Typical Operating Circuit of Figure 2, if applicable.)
MAX7456
Single-Channel Monochrome On-Screen
Display with Integrated EEPROM
_______________________________________________________________________________________ 7
10µs/div
100% SWEEP RESPONSE
CVBS OUT
(200mV/div)
MAX7456 toc05
DIFFERENTIAL PHASE
MAX7456 toc06
STEP
DIFFERENTIAL PHASE (deg)
6th5th4th3rd2nd1st
0
0.05
0.10
CVBS OUT
0.15
0.20
-0.05
DIFFERENTIAL GAIN
MAX7456 toc07
STEP
DIFFERENTIAL GAIN (%)
6th5th4th3rd2nd1st
0
0.05
0.10
0.15
0.20
-0.05
CVBS OUT
400ns/div
2T RESPONSE
CVBS IN
(200mV/div)
CVBS OUT
(200mV/div)
MAX7456 toc08
400ns/div
12.5T RESPONSE
CVBS IN
(200mV/div)
CVBS OUT
(200mV/div)
MAX7456 toc09
200ns/div
OSD OUTPUT 100% WHITE PIXEL
CVBS OUT
(200mV/div)
MAX7456 toc10
Typical Operating Characteristics (continued)
(V
AVDD
= +5V, V
DVDD
= +5V, V
PVDD
= +5V, TA= +25°C, unless otherwise noted. See the Typical Operating Circuit of Figure 2, if applicable.)
MAX7456
Single-Channel Monochrome On-Screen
Display with Integrated EEPROM
8 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(V
AVDD
= +5V, V
DVDD
= +5V, V
PVDD
= +5V, TA= +25°C, unless otherwise noted. See the Typical Operating Circuit of Figure 2, if applicable.)
10µs/div
LINE-TIME DISTORTION
CVBS OUT
(200mV/div)
MAX7456 toc11
2µs/div
H TIMING (EXTERNAL-SYNC MODE)
CVBS OUT
(200mV/div)
MAX7456 toc12
2µs/div
H TIMING (INTERNAL-SYNC MODE)
CVBS OUT
(200mV/div)
MAX7456 toc13
500µs/div
LOSS-OF-SYNC (LOW TO HIGH)
CVBS OUT
(200mV/div)
LOS
(1V/div)
MAX7456 toc14
500µs/div
LOSS-OF-SYNC (HIGH TO LOW)
CVBS OUT
(200mV/div)
LOS
(1V/div)
MAX7456 toc15
MAX7456
Single-Channel Monochrome On-Screen
Display with Integrated EEPROM
_______________________________________________________________________________________ 9
Pin Description
PIN NAME FUNCTION
1, 2, 13–16,
27, 28
N.C. No Connection. Not internally connected.
3 DVDD Digital Power-Supply Input. Bypass to DGND with a 0.1µF capacitor.
4 DGND Digital Ground
5 CLKIN
Crystal Connection 1. Connect a parallel resonant, fundamental mode crystal between CLKIN and XFB
for use as a crystal oscillator, or drive CLKIN directly with a 27MHz system reference clock.
6 XFB
Crystal Connection 2. Connect a parallel resonant, fundamental mode crystal between CLKIN and XFB
for use as a crystal oscillator, or leave XFB unconnected when driving CLKIN with a 27MHz system
reference clock.
7
Clock Output. 27MHz logic-level output system clock.
8 CS Active-Low Chip-Select Input. SDOUT goes high impedance when CS is high.
9 SDIN Serial Data Input. Data is clocked in at rising edge of SCLK.
10 SCLK
Serial Clock Input. Clocks data into SDIN and out of SDOUT. Duty cycle must be between 40% and 60%.
11
Serial Data Output. Data is clocked out at the falling edge of SCLK. High impedance when CS is high.
12 LOS
Loss-of-Sync Output (Open-Drain). LOS goes high when the VIN sync pulse is lost for 32 consecutive
lines. LOS goes low when 32 consecutive valid sync pulses are received. Connect to a 1kΩ pullup
resistor to DVDD or another positive supply voltage suitable for the receiving device.
17
Vertical Sync Output (Open-Drain). VSYNC goes low following the video input’s vertical sync interval.
VSYNC is either recovered from VIN or internally generated when in internal sync mode. Connect to a
1kΩ pullup resistor to DVDD or another positive supply voltage suitable for the receiving device.
18
Horizontal Sync Output (Open-Drain). HSYNC goes low following the video input’s horizontal sync
interval. HSYNC is either recovered from VIN or internally generated when in internal sync mode. Connect
to a 1kΩ pullup resistor to DVDD or another positive supply voltage suitable for the receiving device.
19
System Reset Input. The minimum RESET pulse width is 50ms. All SPI registers are reset to their default
values after 100µs following the rising edge of RESET. These registers are not accessible for reading or
writing during that time. The display memory is reset to its default value of 00H in all locations after 20µs
following the rising edge of RESET.
20 AGND Analog Ground
21 AVDD Analog Power-Supply Input. Bypass to AGND with a 0.1µF capacitor.
22 VIN PAL or NTSC CVBS Video Input
23 PGND Driver Ground. Connect to AGND at a single point.
24 PVDD Driver Power-Supply Input. Bypass to PGND with a 0.1µF capacitor.
25 SAG Sag Correction Input. Connect to VOUT if not used. See Figure 1b.
26 VOUT Video Output
—EP
Exposed Pad. Internally connected to AGND. Connect EP to the AGND plane for improved heat
dissipation. Do not use EP as the only ground connection.
CLKOUT
SDOUT
VSYNC
HSYNC
RESET
MAX7456
Single-Channel Monochrome On-Screen
Display with Integrated EEPROM
10 ______________________________________________________________________________________
Detailed Description
The MAX7456 single-channel monochrome on-screen
display (OSD) generator integrates all the functions needed to generate a user-defined OSD and insert it into the
output signal. The MAX7456 accepts a composite NTSC
or PAL video signal. The device includes an input clamp,
sync separator, video timing generator, OSD insertion
mux, nonvolatile character memory, display memory,
OSD generator, crystal oscillator, an SPI-compatible interface to read/write the OSD data, and a video driver (see
the Simplified Functional Diagram). Additionally, the
MAX7456 provides vertical sync (VSYNC), horizontal
sync (HSYNC), and loss-of sync (LOS) outputs for system
synchronization. A clock output signal (CLKOUT) allows
daisy-chaining of multiple devices.
See the MAX7456 Register Description section for an
explanation of register notation use in this data sheet.
The 256 user-defined 12 x 18 pixel character set
comes preloaded and is combined with the input video
stream to generate a CVBS signal with OSD video output. A maximum of 256 12 x 18 pixel characters can be
reprogrammed in the NVM. In NTSC mode, 13 rows x
30 characters are displayed. In PAL mode, 16 rows x
30 characters are displayed. When the input video signal is absent, the OSD image can still be displayed by
using the MAX7456’s internal video timing generator.
Video Input
The MAX7456 accepts standard NTSC or PAL CVBS
signals at VIN. The video signal input must be AC-coupled with a 0.1µF capacitor and is internally clamped.
An input coupling capacitance of 0.1µF is required to
guarantee the specified line-time distortion (LTD) and
video clamp settling time. The video clamp settling time
changes proportionally to the input coupling capacitance, and LTD changes inversely proportional to the
capacitance.
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
MAX7456
SDIN
+5V
27MHz
SDOUT
+5V
CVBS OUT
SAG
PGND
RESET
HSYNC
VSYNC
DGND
CLKIN
XFB
CLKOUT
CS
SDIN
SCLK
SDOUT
LOS
N.C.
SCLK
CS
CVBS IN
LOS
VS
HS
N.C.
N.C.
N.C.
CLKOUT
N.C.
N.C.
AGND
N.C.
N.C.
+5V
0.1µF
C
OUT
75Ω
75Ω
1kΩ1kΩ1kΩ
0.1µF
0.1µF
0.1µF
C
SAG
DVDD
VOUT
PVDD
VIN
AVDD
Figure 2. Typical Operating Circuit
MAX7456
Single-Channel Monochrome On-Screen
Display with Integrated EEPROM
______________________________________________________________________________________ 11
Input Clamp
The MAX7456’s clamp is a DC-restore circuit that uses
the input coupling capacitor to correct any DC shift of
the input signal, on a line-by-line basis, such that the
sync tip at VIN is approximately 550mV. This establishes a DC level at VIN suitable for the on-chip sync
detection and video processing functions. This circuitry
also removes low-frequency noise such as 60Hz hum
or other additive low-frequency noise.
Sync Separator
The sync separator detects the composite sync pulses
on the video input and extracts the timing information to
generate HSYNC and VSYNC. It is also used for internal OSD synchronization and loss-of-sync (LOS) detection. LOS goes high if no sync signal is detected at VIN
for 32 consecutive lines, and goes low if 32 consecutive horizontal sync signals are detected. During a LOS
condition, when VM0[5] = 0 (Video Mode 0 register, bit
5), only the OSD appears at the VOUT. At this time, the
input image is set to a gray level at VOUT as determined by VM1[6:4]. The behavior of all sync modes is
shown in Table 1.
COLOR BURST
SYNC TIP
LEVEL
BLACK LEVEL
WHITE LEVEL
MAXIMUM VIDEO SWING
INPUT VOLTAGE
MINIMUM VIDEO SWING
VIN
Figure 3. Definition of Terms
VIDEO MODE VIN VSYNC HSYNC LOS VOUT
Video Active Active Low VIN + OSD
Auto Sync Select Mode
VM0[5, 4] = 0x
No input Active Active High OSD only
Video Active Active Low VIN + OSD
External Sync Select
VM0[5, 4] = 10
No input Inactive (high) Inactive (high) High DC
Video Active Active High OSD only
Internal Sync Select
VM0[5, 4] = 11
No input Active Active High OSD only
Table 1. Video Sync Modes
X = Don’t care.
MAX7456
Single-Channel Monochrome On-Screen
Display with Integrated EEPROM
12 ______________________________________________________________________________________
Video Timing Generator
The video timing generator is a digital circuit generating all internal and external (VSYNC and HSYNC) timing signals. VSYNC and HSYNC can be synchronized
to VIN, or run independently of any input when in internal sync mode. The video timing generator can generate NTSC or PAL timing using the same 27MHz crystal
(see Figures 4–9).
Crystal Oscillator
The internal crystal oscillator generates the system
clock used by the video timing generator. The oscillator
uses a 27MHz crystal or can be driven by an external
27MHz TTL clock at CLKIN. For external clock mode,
connect the 27MHz TTL input clock to CLKIN and leave
XFB unconnected.
Display Memory (SRAM)
The display memory stores 480 character addresses
that point to the characters stored in the NVM character
memory. The content of the display memory is userprogrammable through the SPI-compatible serial interface. The display-memory address corresponds to a
fixed location on a monitor (see Figure 10). Momentary
breakup of the OSD image can be prevented by writing
to the display memory during the vertical blanking interval. This can be achieved by using VSYNC as an interrupt to the host processor to initiate writing to the
display memory.
t
VOUT-VSF
1/2H
VERTICAL SYNCHRONIZATION
PULSE INTERVAL
VOUT
(ODD FIELD)
VOUT
(EVEN FIELD)
VSYNC
HSYNC
(ODD FIELD)
HSYNC
(EVEN FIELD)
50%
50%
t
VOUT-VSR
50%
50%
50%
Figure 4. VOUT,
VSYNC
, and
HSYNC
Timing (NTSC, External Sync Mode)
MAX7456
Single-Channel Monochrome On-Screen
Display with Integrated EEPROM
______________________________________________________________________________________ 13
t
VSF-VOUT
1/2H
VERTICAL SYNCHRONIZATION
PULSE INTERVAL
VOUT
(ODD FIELD)
VOUT
(EVEN FIELD)
VSYNC
HSYNC
(ODD FIELD)
HSYNC
(EVEN FIELD)
50%
50%
t
VSR-VOUT
50%
50%
50%
50%
Figure 5. VOUT,
VSYNC
, and
HSYNC
Timing (NTSC, Internal Sync Mode)
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