with I2C Interface and High Level of ESD Protection
General Description
The MAX7370 I2C-interfaced peripheral provides microprocessors with management of up to 64 key switches,
with optional GPIO and PWM-controlled LED drivers.
The key-switch drivers interface with metallic or resistive
switches with on-resistances up to 5kI. Key inputs are
monitored statically, not dynamically, to ensure low-EMI
operation. The IC features autosleep and autowake
modes to further minimize the power consumption of
the device. The autosleep feature puts the device in a
low-power state (1µA typ) after a timeout period. The
autowake feature configures the device to return to
normal operating mode from sleep upon a keypress.
The key controller debounces and maintains a FIFO
buffer of keypress and release events (including autorepeat, if enabled). An interrupt (INT) output can be
configured to alert keypresses, as they occur, or at the
maximum rate.
The same index rows and columns in the device can be
used as a direct logic-level translator.
If the device is not used for key-switch control, all
keyboard pins can be used as GPIOs. Each GPIO can
be programmed to one of the two externally applied
logic voltage levels. Four column ports (COL7–COL4)
can also be configured as LED drivers that feature
constant-current and PWM intensity control. The maximum
constant-current level for each open-drain LED port is
20mA. The intensity of the LED on each open-drain port
can be individually adjusted through a 256-step PWM
control.
The device is offered in a 24-pin (3.5mm x 3.5mm) TQFN
package with an exposed pad, and small 25-bump
(2.159mm x 2.159mm) wafer-level package (WLP) for
cell phones, pocket PCs, and other portable consumer
electronic applications.
The device operates over the -40°C to +85°C extended
temperature range.
Applications
Cell Phones
Notebooks
PDAs
Handheld Games
Portable Consumer Electronics
For related parts and recommended products to use with this part,
refer to www.maxim-ic.com/MAX7370.related.
Features
SMonitors Up to 64 Keys
SIntegrated High-ESD Protection
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX7370
8 x 8 Key-Switch Controller and LED Driver/GPIOs
with I2C Interface and High Level of ESD Protection
ABSOLUTE MAXIMUM RATINGS
VCC, VLA to GND ....................................................-0.3V to +4V
COL3–COL0, ROW7–ROW0 to GND ....... -0.3V to (VCC + 0.3V)
COL7–COL4 to GND ............................................... -0.3V to +6V
SDA, SCL, AD0, INT to GND ..................................-0.3V to +6V
VLA to VCC ...........................................................-0.3V to +2.3V
DC Current on COL7–COL4 to GND .................................25mA
DC Current on COL3–COL0, ROW7–ROW0 to GND ...........7mA
VCC, VLA, GND Current .....................................................80mA
DC Current VCC, VLA to COL3–COL0, ROW7–ROW0 .........5mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
with I2C Interface and High Level of ESD Protection
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 1.62V to 3.6V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = 3.3V, TA = +25NC.) (Notes 2, 3)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
I2C TIMING SPECIFICATIONS
SCL Serial-Clock Frequencyf
Bus Free Time Between a STOP and
START Condition
Hold Time (Repeated) START Conditiont
Repeated START Condition Setup Timet
STOP Condition Setup Timet
Data Hold Timet
Data Setup Timet
SCL Clock Low Periodt
SCL Clock High Periodt
Rise Time of Both SDA and SCL
Signals, Receiving
Fall Time of Both SDA and SCL Signals,
Receiving
Fall Time of SDA Signal, Transmittingt
Pulse Width of Spike Suppressedt
Capacitive Load for Each Bus LineC
Bus Time Outt
ESD PROTECTION
t
HD, STA
SU, STA
SU, STO
HD, DAT
SU, DAT
LOW
HIGH
F, TX
TIMEOUT
SCL
BUF
t
t
SP
Bus timeout enabled0.05400
Bus timeout disabled0400
1.3
0.6
0.6
0.6
(Note 6)0.9
100ns
1.3
0.7
(Notes 4, 5)
R
(Notes 4, 5)
F
(Notes 4, 7)
(Notes 4, 8)50ns
(Note 4)400pF
B
141927ms
20 +
0.1C
20 +
0.1C
20 +
0.1C
B
B
B
kHz
Fs
Fs
Fs
Fs
Fs
Fs
Fs
300ns
300ns
250ns
IEC 61000-4-2 Air-Gap Discharge
ROW7–ROW0, COL7–COL0
IEC 61000-4-2 Contact Discharge
All Other PinsHuman Body Model
Note 2: All parameters are tested at TA = +25°C. Specifications over temperature are guaranteed by design.
Note 3: All digital inputs at VCC or GND.
Note 4: Guaranteed by design.
Note 5: CB = total capacitance of one bus line in pF. tR and tF measured between 0.8V and 2.1V.
Note 6: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) to bridge
the undefined region of SCL’s falling edge.
Note 7: I
Note 8: Input filters on the SDA, SCL, and AD0 inputs suppress noise spikes less than 50ns.
= 6mA. CB = total capacitance of one bus line in pF. tR and tF measured between 0.8V and 2.1V.
with I2C Interface and High Level of ESD Protection
Pin/Bump Configurations
TOP VIEW
(BUMP SIDE DOWN)
MAX7370
TOP VIEW
ROW0
ROW1
ROW2
ROW3
GND
ROW4
CC
INT
V
18 17 16 15 14 13
19
20
21
22
23
24
1+23456
ROW5
SCL
MAX7370
ROW6
ROW7
COL7
SDA
AD0
EP*
COL6
LA
V
COL5
12
COL0
11
COL1
10
COL2
COL3
9
GND
8
COL4
7
TQFN
*CONNECT EP TO GROUND.
PINBUMP
TQFNWLP
NAMEFUNCTION
1A2ROW5Row 5 Input from Key Matrix or GPIO Port
2B2ROW6Row 6 Input from Key Matrix or GPIO Port
3A3ROW7Row 7 Input from Key Matrix or GPIO Port
4B3COL7
5A4COL6
6A5COL5
7B4COL4
8, 23
B1, B5,
C3
GNDGround
Column 7 Output from Key Matrix or Open-Drain GPIO Port. COL7 can be configured as a
constant-current sink.
Column 6 Output from Key Matrix or Open-Drain GPIO Port. COL6 can be configured as a
constant-current sink.
Column 5 Output from Key Matrix or Open-Drain GPIO Port. COL5 can be configured as a
constant-current sink.
Column 4 Output from Key Matrix or Open-Drain GPIO Port. COL4 can be configured as a
constant-current sink.
9C5COL3Column 3 Output from Key Matrix or GPIO Port
10C4COL2Column 2 Output from Key Matrix or GPIO Port
11D5COL1Column 1 Output from Key Matrix or GPIO Port
12E5COL0Column 0 Output from Key Matrix or GPIO Port
with I2C Interface and High Level of ESD Protection
Pin Description (continued)
PIN
TQFNWLP
13D4V
NAMEFUNCTION
Second Logic Level for GPIO Level Shifting (where VCC P VLA P 3.6V)
LA
14E4AD0Address Input. Selects up to four device slave addresses (Table 3).
15D3SDAI2C-Compatible, Serial-Data I/O
16E3SCLI2C-Compatible, Serial-Clock Input
17E2
18D2V
INTActive-Low Key-Switch Interrupt Output. INT is open-drain and requires a pullup resistor.
Positive Supply Voltage. Bypass to GND with a 0.1FF capacitor as close as possible to the device.
CC
19E1ROW0Row 0 Input from Key Matrix or GPIO Port
20D1ROW1Row 1 Input from Key Matrix or GPIO Port
21C2ROW2Row 2 Input from Key Matrix or GPIO Port
22C1ROW3Row 3 Input from Key Matrix or GPIO Port
24A1ROW4Row 4 Input from Key Matrix or GPIO Port
——EP
Exposed Pad (TQFN Only). Internally connected to GND. Connect to a large ground plane to
maximize thermal performance. Not intended as an electrical connection point.
with I2C Interface and High Level of ESD Protection
Detailed Description
autowake are enabled/disabled by programming the
configuration register (0x01).
The MAX7370 is a microprocessor peripheral low-noise
key-switch controller that monitors up to 64 key switches
with optional autorepeat, and key events that are presented in a 16-byte FIFO. Key-switch functionality can
be traded to provide up to 16 logic inputs. The device
also features 12 push-pull GPOs configured for digital
I/O and four open-drain GPOs configurable as constantcurrent outputs for LED applications up to 5V. The device
supports a second 1.62V to 3.6V power supply for level
translation. The second logic supply voltage (VLA) must
be set equal to or higher than VCC.
The device features an automatic sleep mode and automatic wakeup that further reduce supply current consumption. The device can be configured to enter sleep
mode after a programmable time following a key event.
To prevent overloading the microprocessor with too
many interrupts, interrupt requests can be triggered
after a programmable number of FIFO entries have been
exceeded, and/or after a set period of time (0x05). The
key-switch status is checked by reading the key-switch
FIFO. A 1-byte read access returns both the next key
event in the FIFO (if there is one) and the FIFO status.
Up to four of the key-switch outputs function as open-
drain GPOs capable of driving additional LEDs when the
application requires fewer keys to be scanned. For each
key-switch output used as a GPO, the number of moni-
tored key switches reduces by eight.
The device meets ESD requirements for ±8kV contact dis-
charge and 15kV Air-Gap Discharge on all key-switch pins.
The FIFO content is maintained and can be read in sleep
mode. The device does not enter autosleep when a key
is held down. The autowake feature takes the device
On power-up, all control registers are set to power-up
values (Table 1) and the device is in sleep mode.
out of sleep mode following a keypress. Autosleep and
Table 1. Register Address Map and Power-Up Conditions
Initial Power-Up
ADDRESS
CODE (hex)
0x00Read only0x3FKeys FIFORead FIFO keyscan data out
0xFFDebounceKey debounce time setting
0x00Interrupt
0x00Key repeatDelay and frequency for key repeat
0x07SleepIdle time to autosleep
0xFFKey-switch sizeKeyscan switch array size
0x00
0x00
0x00
0xFF
0x0F
REGISTER
FUNCTION
LED driver
enable
GPIO
direction 1
GPIO
direction 2
GPO output
mode 1
GPO output
mode 2
Power-down, key-release enable, autowake, and I2C
timeout enable
Key-switch interrupt and INT frequency setting
LED driver enable register
GPIO input/output control register 1 for
ROW7–ROW0
GPIO input/output control register 2 for COL7–COL0
GPO open-drain/push-pull output setting for
ROW7–ROW0
GPO open-drain/push-pull output setting for
COL7–COL0
DESCRIPTION
MAX7370
8 x 8 Key-Switch Controller and LED Driver/GPIOs
with I2C Interface and High Level of ESD Protection
Table 1. Register Address Map and Power-Up Conditions (continued)
ADDRESS
CODE (hex)
0x38
0x39
0x3A
0x3B
0x3C
0x40
0x42
0x43
0x45
0x48Read only0x00I2C timeout flagI2C timeout since last POR
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POWER-UP
VALUE (hex)
0x00
0x00
0xFFGPIO values 1Debounced input or output values of ROW7–ROW0
0xFFGPIO values 2Debounced input or output values of COL7–COL0
0x00
0x00
0x00GPIO debounceROW7–ROW0 debounce time setting
0xC0
0x00Common PWMCommon PWM duty-cycle setting
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
0xFF
0x00
0x00
REGISTER
FUNCTION
GPIO supply
voltage 1
GPIO supply
voltage 2
GPIO level-
shifter enable
GPIO global
configuration
LED constant-
current setting
COL4 PWM
ratio
COL5 PWM
ratio
COL6 PWM
ratio
COL7 PWM
ratio
COL4 LED
configuration
COL5 LED
configuration
COL6 LED
configuration
COL7 LED
configuration
Interrupt
mask 1
Interrupt
mask 2
GPI trigger
mode 1
GPI trigger
mode 2
GPIO voltages supplied by VCC or VLA for
ROW7–ROW0
GPIO voltages supplied by VCC or VLA for
COL7–COL0
GPIO direct level-shifter pair enable
GPIO global enable, GPIO reset, LED fade enable
COL7–COL4 constant-current output setting
COL4 individual duty-cycle setting
COL5 individual duty-cycle setting
COL6 individual duty-cycle setting
COL7 individual duty-cycle setting
COL4 interrupt, PWM mode control, and blinkperiod settings
COL5 interrupt, PWM mode control, and blinkperiod settings
COL6 interrupt, PWM mode control, and blinkperiod settings
COL7 interrupt, PWM mode control, and blinkperiod settings
Interrupt mask for ROW7–ROW0
Interrupt mask for COL7–COL0
GPI edge-triggered detection setting for
ROW7–ROW0
GPI edge-triggered detection setting for
COL7–COL0
with I2C Interface and High Level of ESD Protection
Keyscan Controller
Key inputs are scanned statically, not dynamically, to
ensure low-EMI operation. Since inputs only toggle in
response to switch changes, the key matrix can be
routed closer to sensitive circuit nodes.
The keyscan controller debounces and maintains a FIFO
buffer of keypress and release events (including autorepeated keypresses, if autorepeat is enabled). Table 2
shows the key-switch order. The user-programmable keyswitch debounce time and autosleep timer are derived
from the 64kHz clock, which in turn is derived from the
128kHz oscillator. Time delay for autorepeat and keyswitch interrupt is based on the key-switch debounce
time. There is no limitation for the number of keys pressed
simultaneously as long as no ghost keys are generated.
If the application requires fewer keys to be scanned, the
unused key-switch ports can be configured as GPIOs.
Keys FIFO Register (0x00)
The Keys FIFO register contains the information pertaining to the status of the keys FIFO, as well as the key events
that have been debounced. See Table 7. Bits D[5:0]
denote which of the 64 keys have been debounced and
the keys are numbered as shown in Table 2.
Bit D7 indicates if there is more data in the FIFO, except
when D[5:0] indicate key 63 or key 62. When D[5:0] indicate key 63 or key 62, the host should read the FIFO one
more time to determine whether there is more data in the
FIFO. Use key 62 and key 63 for rarely used keys. D6
indicates if it is a keypress or release event, except when
D[5:0] indicate key 63 or key 62.
Reading the keyscan FIFO clears the interrupt (INT),
depending on the setting of bit D5 in the configuration
register (0x01).
Configuration Register (0x01)
The Configuration register controls the I2C bus time-
out feature, enables key-release detection, enables
autowake, and determines how INT is deasserted. Write
to bit D7 to put the device into sleep mode or operating
mode. Autosleep and autowake, when enabled, also
change the status of D7. See Table 8.
Debounce Register (0x02)
The Debounce register sets the keypress and key-
release time for each debounce cycle. Bits D[3:0] set the
debounce time for keypresses, while bits D[7:4] set the
debounce time for key releases. Both debounce times
are configured in increments of 2ms starting at 2ms and
ending at 32ms. See Table 9.
Interrupt Register (0x03)
The Interrupt register contains information related to the
settings of the interrupt request function, as well as the sta-
tus of the INT output. If bits D[7:0] are set to 0x00, the INT
is disabled. There are two types of interrupts, the FIFO-
based interrupt and time-based interrupt. Set bits D[4:0]
to assert interrupts at the end of the selected number of
debounce cycles following a key event. See Table 10.
This number ranges from 1–31 debounce cycles. Setting
bits D[5:7] set the FIFO-based interrupt when there are
2–14 key events stored in the FIFO. Both interrupts can be
configured simultaneously and INT asserts depending on
which condition is met first. INT deasserts depending on
the status of bit D5 in the configuration register.
Autorepeat Register (0x05)
The device autorepeat feature notifies the host that at
least one key has been pressed for a continuous period.
The Autorepeat register enables or disables this feature,
sets the time delay after the last key event before the key-
repeat code (0x7E) is entered into the FIFO, and sets
with I2C Interface and High Level of ESD Protection
the frequency at which the key-repeat code is entered
into the FIFO thereafter. The key being pressed is not
entered again into the FIFO. Bit D7 specifies whether
the autorepeat function is enabled with 0, denoting
autorepeat disabled, and 1, denoting autorepeat
enabled. Bits D[3:0] specify the autorepeat delay in
terms of debounce cycles, ranging from eight debounce
cycles to 128 debounce cycles. See Table 11. Bits D[6:4]
specify the autorepeat rate or frequency ranging from
4–32 debounce cycles.
Only one autorepeat code is entered into the FIFO,
regardless of the number of keys pressed. The autorepeat code continues to be entered in the FIFO at the
frequency set by bits D[3:0] until another key event is
recorded. Following the key-release event, if any keys are
still pressed, the device restarts the autorepeat sequence.
Autosleep Register (0x06)
Autosleep puts the device in sleep mode to draw minimal
current. When enabled, the device enters sleep mode
if no keys are pressed for the autoshutdown time. See
Table 12.
Key-Switch Array Size Register (0x30)
Bits D[7:4] set the row size of the key-switch array, and
bits D[3:0] set the column size of the key-switch array.
See Table 13. Set the bits to 0 if no key switches are
used. The key-switch array should be connected beginning at ROW0 and COL0. If not used as a key-switch
matrix pin, then the pin can function as a GPIO port.
Key-Switch Sleep Mode
In sleep mode, the device draws minimal current. Switchmatrix current sources are turned off and pulled up to
VCC. When autosleep is enabled, key-switch inactivity
for a period longer than the autosleep time puts the part
into sleep mode (FIFO data is maintained). Writing a 1 to
D7 or a keypress can take the device out of sleep mode.
Bit D7 in the configuration register gives the sleep-mode
status and can be read any time.
Autowake
Keypresses initiate autowake and the device goes into
operating mode. Keypresses that autowake the device
are not lost. When a key is pressed while the device is in
sleep mode, all analog circuitry, including switch-matrix
current sources, turn on in 2ms. The initial key needs to
be pressed for 2ms plus the debounce time to be stored
in the FIFO. Write a 0 to bit D1 in the configuration register (0x01) to disable autowake.
FIFO Overflow
The FIFO overflow status occurs when the FIFO is full
(16 bytes) and additional events occur. If key release is
disabled, then the FIFO overflow status occurs when the
FIFO is full and not upon additional key events. When
the FIFO is overflowed, the first byte read from the FIFO
buffer is the overflow byte (0x7F). The order of the
original 16 bytes of event data is preserved, but further
events could be lost. When the FIFO is full, if the 18th
key event is a key release, then the FIFO overflow status
is removed.
GPIOs
The device has 16 GPIO ports, four of which have LED
control functions. The ports can be used as logic inputs
or logic outputs. COL7–COL4 are also configurable as
constant-current PWM LED drivers. Each port’s logic
level is referenced to VCC or VLA. The GPIO ports’ inputs
can also be debounced. When in PWM mode, the ports
are set up to start their PWM cycle in 45N phase increments. This prevents large current spikes on the LED
supply voltage when driving multiple LEDs.
LED Driver Enable Register (0x31)
Bits D[3:0] correspond to COL7–COL4 on the device.
Set the corresponding bit to 1 for enabling the LED driver
circuitry and 0 for normal GPIO function. See Table 14.
GPIO Direction 1 and 2 Registers (0x34, 0x35)
These registers configure the pins as an input or an output
port. GPIO Direction 1 register bits D[7:0] correspond with
ROW7–ROW0. See Table 15. GPIO Direction 2 register
bits D[7:0] correspond with COL7–COL0. See Table 16.
Set the corresponding bit to 0 to configure as input and 1
to configure as output.
When the port is initially programmed as an input, there
is a delay of one debounce period prior to detecting
a transition on the input port. This is to prevent a false
interrupt from occurring when changing a port from an
output to an input.
with I2C Interface and High Level of ESD Protection
GPO Output Mode 1 and 2 Registers (0x36, 0x37)
These registers configure the pin as an open-drain
or push-pull output. GPO Output Mode 1 register bits
D[7:0] correspond with ROW7–ROW0. See Table 17.
GPO Output Mode 2 register bits D[7:0] correspond with
COL7–COL0. See Table 18. Set the corresponding bit to
0 to configure the output mode as open-drain and 1 to
configure the output mode as push-pull.
GPIO Supply Voltage 1 and 2
Registers (0x38, 0x39)
These registers configure input and output voltages to
be referenced to VCC or VLA. GPIO Supply Voltage 1
register bits D[7:0] correspond with ROW7–ROW0. See
Table 19. GPIO Supply Voltage 2 register bits D[7:0] cor-
respond with COL7–COL0. See Table 20. Set the bit to 0
for input/output voltages referenced to VCC or set the bit
to 1 for the input/output voltage referenced to VLA.
GPIO Values 1 and 2 Registers (0x3A, 0x3B)
The GPIO Values 1 and 2 registers contain the debounced
input data for all the GPIOs for ROW7–ROW0 and COL7–
COL0, respectively. See Tables 21 and 22. There is one
debounce period delay prior to detecting a transition on
the input port. This prevents a false interrupt from occurring when changing a port from an output to an input. The
GPIO Values 1 and 2 registers report the state of all input
ports regardless of any interrupt mask settings.
When writing to the GPIO Values 1 and 2 registers, the
corresponding port voltage is set high when written 1 or
cleared when written 0. Reading the port when configured as an output always returns the value 0 for the corresponding port regardless of the output value.
GPIO Level-Shifter Enable Register (0x3C)
Enabling bit D_ in this register enables the direct level
shifter between GPIO pins COL_ and ROW_. See
Table 23. As an example, setting D5 to logic-high
enables level shifting between COL5 and ROW5. The
direction of the level shifter is controlled by the GPIO
Direction 2 register (0x35). When setting the corresponding bit in the GPIO Direction 2 register to 0, COL_ are
inputs, and ROW_ are outputs. When setting the bit to 1,
ROW_ become inputs and COL_ become outputs.
GPIO Global Configuration Register (0x40)
The GPIO Global Configuration register controls the main
settings for the GPIO ports. See Table 24. Bit D5 enables
interrupt generation for I2C timeouts. D4 is the main
enable/shutdown bit for the GPIOs. Bit D3 functions as a
software reset for the GPIO registers (0x31 to 0x5B). Bits
D[2:0] set the fade-in/out time for the LED drivers.
GPIO Debounce Configuration Register (0x42)
The GPIO Debounce Configuration Register sets the
amount of time a GPIO must be held in order for the
device to register a logic transition. See Table 25. The
GPIO debounce setting is independent of the key-switch
debounce setting. Five bits (D[4:0]) set 32 possible
debounce times from 9ms up to 40ms.
LED Constant-Current Setting Register (0x43)
The LED Constant-Current Setting register sets the global
constant-current amount. See Table 26. Bit D0 selects
the global current values between 10mA and 20mA.
This setting only applies to the LED driver-enabled pins,
COL7–COL4.
Common PWM Ratio Register (0x45)
The Common PWM Ratio register stores the common
constant-current output PWM duty cycle. See Table 27.
The values stored in this register translate over to a PWM
ratio in the same manner as the individual PWM ratio registers (0x50 to 0x53). Ports can use their own individual
PWM value or the common PWM value. Write to this register to change the PWM ratio of several ports at once.
I2C Timeout Flag Register (0x48) (Read Only)
The I2C Timeout Flag register contains a single bit
(D0) that indicates if an I2C timeout has occurred. See
Table 28. Read this register to clear an I2C timeout-
initiated interrupt.
COL4–COL7 Individual PWM Ratio
Registers (0x50 to 0x53)
Each LED driver port has an individual PWM ratio register,
0x50 to 0x53. See Table 29. Use values 0x00 to 0xFE in
these registers to configure the number of cycles out of
256 the output sinks current (LED is on), from 0 cycles to
254 cycles. Use 0xFF to have an output continuously sink
current (always on). For applications requiring multiple
ports to have the same intensity, program a particular
port’s configuration register (0x54 to 0x57) to use the
Common PWM Ratio register (0x45). New PWM settings
take place at the beginning of a PWM cycle, to allow
changes from common intensity to individual intensity with
no interruption in the PWM cycle.
with I2C Interface and High Level of ESD Protection
COL4–COL7 LED Configuration
Registers (0x54 to 0x57)
Registers 0x54 to 0x57 set individual configurations for
each port. See Table 30. D5 sets the port’s PWM setting
to either the common or individual PWM setting. Bits
D[4:2] enable and set the port’s individual blink period
from 0 to 4096ms. Bits D[1:0] set a port’s blink duty cycle.
Interrupt Mask 1 and 2 Registers (0x58, 0x59)
The Interrupt Mask 1 and 2 registers control which ports
trigger an interrupt for ROW7–ROW0 and COL7–COL0,
respectively. See Tables 31 and 32. Set the bit to 0 to
enable the interrupt. Set the bit to 1 to mask the interrupt.
If the port that has generated the interrupt is not masked,
the interrupt causes the INT signal to assert. A read of the
GPIO Values 1 and 2 registers (0x3A, 0x3B) is required
to deassert the INT pin. Note that transitions that occur
while the INT signal is asserted, but before the read of the
GPIO Values 1 and 2 registers, set the appropriate bit of
the GPIO Values 1 and 2 registers only, but has no effect
on the INT pin as it is already asserted. However, transitions that occur when the I2C is active cannot be latched
into the GPIO Values 1 and 2 registers until after the read
has taken place. If there are transitions that cause the
INT signal to assert, during the time of an I2C read, they
cause the INT signal to reassert once the read transaction has taken place. Note that the interrupt configurations only apply when a port is configured as an input.
GPI Trigger Mode 1 and 2 Registers (0x5A, 0x5B)
The GPI Trigger Mode 1 and 2 registers control how ports
can trigger an interrupt for ROW7–ROW0 and COL7–
COL0, respectively. See Tables 33 and 34. Set the bit to
0 for rising-edge triggering. Set the bit to 1 for rising- and
falling-edge triggering.
The inputs are debounced (if enabled) by taking a snapshot of the port state when the transition occurs, and
another after the debounce time has elapsed—ensuring
that the state of the port is stable prior to triggering the
interrupt. After the debounce cycle, an interrupt is generated and the INT pin asserted if it is not masked for that
particular port. Regardless of whether or not the INT signal is masked, the GPIO Values 1 and 2 registers (0x3A,
0x3B) report the state of all input ports.
Sleep Mode
The device is put into sleep mode by clearing bit D7 in
the Configuration register, or after power-on reset (POR).
In sleep mode, the keyscan controller is disabled and the
device draws minimal current. No additional supply current is drawn if no keys are pressed. All switch-matrix current sources are turned off, and row outputs ROW7–ROW0
are low and column outputs COL7–COL0 become high.
The device is taken out of sleep mode and put into operating mode by setting bit D7 in the configuration register.
The keyscan controller FIFO buffers are cleared and key
monitoring starts. Note that rewriting the configuration
register with bit D7 high, when bit D7 was already high,
does not clear the FIFOs. The FIFOs are only cleared
when the device is changing state from sleep mode to
operating mode.
In sleep mode, the internal oscillator is disabled and
I2C timeout features are disabled. The GPO or LED
ports consume current even in sleep mode. The part
does not enter sleep mode if any of the GPIOs or LED
drivers are enabled.
LED Fade
Set the fade cycle time in the GPIO Global Configuration
register (0x40) to a non-zero value to enable fade in/out.
See Table 24. Fade in increases an LED’s PWM intensity
in 16 even steps, from zero to its stored value. Fade out
decreases an LED’s PWM intensity in 16 even steps from
its current value to zero. Fading occurs automatically in
any of the following scenarios:
fade in. Changing an individual PWM intensity during fade in automatically cancels that port’s fade and
immediately outputs at its newly programmed intensity.
out. Changing an individual PWM intensity during
fade out automatically cancels that port’s fade and
immediately turns off.
LED PWM
Each port has an individual PWM ratio register. The value
stored in this register configures the number of cycles
out of 255 that the output is sinking current (LED is on).
Setting a value of 0xFF in an individual intensity register
sets the output to continuously sink current (always on).
Conversely, setting a value of 0x00 in an individual intensity register sets the output in a high-impedance state
(always off).
For applications requiring multiple ports to have the
same intensity, the common PWM ratio intensity setting
can be used in lieu of the individual intensity setting. To
use the common intensity setting, program bit D5 of the
corresponding port’s configuration register to logic-high.
Setting a port to use the common PWM ratio setting
copies the value of the common intensity register into
the individual intensity register at the beginning of each
PWM cycle. This allows an output port to be seamlessly
changed from common intensity to individual intensity
with no interruption in the PWM cycle.
Outputs are configured to sink a constant current of either
10mA or 20mA during the period of time when the output
is on. The setting in the individual GPIO constant-current
setting register (0x43) controls the value of the current.
LED Blink
Each LED driver-supported port has its own blink-control
settings through registers 0x54 to 0x57. See Table 30.
The blink period ranges from 0 (blink disabled) to 4.096s.
Settable blink duty cycles range from 6.25% to 50%. All
blink periods start at the same PWM cycle for synchronized blinking between multiple ports.
Each port has its own counter to generate blink timing.
The blink counter can be programmed to cause the output to gate off and on at a programmable rate. The blink
period can be set to 256ms, 512ms, 1.024s, 2.048s, or
4.096s using D[4:2] of the port’s individual configuration
register. The percentage of time that the LED is on for
one blink cycle is set to 50%, 25%, 12.5%, or 6.25% by
D[1:0] of the individual configuration register.
Interrupts
Three possible sources generate INT: key-switch FIFO
level/debounce cycle settings, I2C timeout, or GPIOs
configured as inputs (registers 0x03, 0x48, 0x5A, and
0x5B). Read the respective data/status registers for each
type of interrupt to clear INT. If multiple sources generate
the interrupt, all the related status registers must be read
to clear INT.
Serial Interface
Figure 1 shows the two-wire serial interface timing details.
SDA
t
SU, DAT
t
LOW
t
SCL
t
HD, STA
START
CONDITION
Figure 1. Two-Wire Serial Interface Timing Details
with I2C Interface and High Level of ESD Protection
Serial Addressing
The device operates as a slave that sends and receives
data through an I2C-compatible two-wire interface. The
interface uses a serial-data line (SDA) and a serialclock line (SCL) to achieve bidirectional communication
between master(s) and slave(s). A master (typically a
microcontroller) initiates all data transfers to and from the
device and generates the SCL clock that synchronizes
the data transfer.
The device’s SDA line operates as both an input and an
open-drain output. A pullup resistor, typically 4.7kω, is
required on SDA. The device’s SCL line operates only as
an input. A pullup resistor is required on SCL if there are
multiple masters on the two-wire interface, or if the master
in a single-master system has an open-drain SCL output.
Each transmission consists of a START (S) condition
(Figure 2) sent by a master, followed by the device’s 7-bit
slave address plus R/W bit, a register address byte, one
or more data bytes, and finally, a STOP (P) condition.
START and STOP Conditions
Both SCL and SDA remain high when the interface is not
busy. A master signals the beginning of a transmission
with a START condition by transitioning SDA from high
to low while SCL is high. When the master has finished
communicating with the slave, it issues a STOP condition
by transitioning SDA from low to high while SCL is high.
The bus is then free for another transmission.
Bit Transfer
One data bit is transferred during each clock pulse
(Figure 3). The data on SDA must remain stable while
SCL is high.
Acknowledge
The acknowledge bit is a clocked 9th bit (Figure 4), which
the recipient uses to handshake receipt of each byte of
data. Thus, each byte transferred effectively requires 9
bits. The master generates the 9th clock pulse, and the
recipient pulls down SDA during the acknowledge clock
pulse; therefore, the SDA line is stable low during the
high period of the clock pulse. When the master is transmitting to the device, the device generates the acknowledge bit because the device is the recipient. When the
device is transmitting to the master, the master generates
the acknowledge bit because the master is the recipient.
with I2C Interface and High Level of ESD Protection
START
CONDITION
1 2 8 9
TRANSMITTER
Figure 4. Acknowledge
Figure 5. Slave Address
SCL
SDA BY
SDA BY
RECEIVER
SDA
SCL
S
011A3A2A11
MSB
Table 3. Two-Wire Interface Address Map
AD0
PIN
GND
V
CC
SDA10
SCL11
A7A6A5A4A3A2A1A0
0111
The device has two 7-bit long slave addresses. The bit
following a 7-bit slave address is the R/W bit, which is
low for a write command and high for a read command.
The first 4 bits (MSBs) of the device slave addresses
are always 0111. Slave address bits A[3:1] correspond,
by the matrix in Table 3, to the states of the device
address input pin AD0, and A0 corresponds to the
R/W bit (Figure 5). The AD0 input can be connected
to any of four signals: GND, VCC, SDA, or SCL, giving four possible slave-address pairs, allowing up to
four devices to share the same bus. Because SDA and
SCL are dynamic signals, care must be taken to ensure
that AD0 transitions no sooner than the signals on
SDA and SCL.
The device monitors the bus continuously, waiting for a
START condition, followed by its slave address. When
the device recognizes its slave address, it acknowledges
and is then ready for continued communication.
DEVICE ADDRESS
00
01
Slave Addresses
0
R/W
CLOCK PULSE FOR
ACKNOWLEDGE
ACKR/W
LSB
Bus Timeout
The device features a 20ms (min) bus timeout on the
two-wire serial interface, largely to prevent the device
from holding the SDA I/O low during a read transaction should the SCL lock up for any reason before a
serial transaction is completed. Bus timeout operates by
causing the device to internally terminate a serial transaction, either read or write, if the time between adjacent
edges on SCL exceeds 20ms. After a bus timeout, the
device waits for a valid START condition before responding to a consecutive transmission. This feature can be
enabled or disabled under user control by writing to the
configuration register.
Message Format for Writing
the Keyscan Controller
A write to the device comprises the transmission of the slave
address with the R/W bit set to zero, followed by at least one
byte of information. The first byte of information is the command byte. The command byte determines which register
of the device is to be written by the next byte, if received.
If a STOP condition is detected after the command byte
is received, the device takes no further action (Figure 6)
beyond storing the command byte.
Any bytes received after the command byte are data bytes.
The first data byte goes into the internal register of the
device selected by the command byte (Figure 7).
If multiple data bytes are transmitted before a STOP condition is detected, these bytes are generally stored in subsequent internal registers of the device, because the command-byte address generally autoincrements (Table 4).
with I2C Interface and High Level of ESD Protection
COMMAND BYTE IS STORED ON RECEIPT OF
SAAP0SLAVE ADDRESSCOMMAND BYTE
Figure 6. Command Byte Received
ACKNOWLEDGE FROM MAX7370
SA
R/W
Figure 7. Command and Single Data Byte Received
ACKNOWLEDGE FROM MAX7370
SA
ACKNOWLEDGE CONDITION
ACKNOWLEDGE FROM MAX7370
R/W
D7 D6 D5 D4D3 D2 D1 D0D1 D0D3 D2D5 D4D7 D6
D7 D6 D5 D4D3 D2 D1 D0D1 D0D3 D2D5 D4D7 D6
ACKNOWLEDGE FROM MAX7370
ACKNOWLEDGE FROM MAX7370
D7D6 D5D4 D3 D2 D1 D0
ACKNOWLEDGE FROM MAX7370
ACKNOWLEDGE FROM MAX7370
P0SLAVE ADDRESSCOMMAND BYTEDATA BYTE
1 BYTE
AUTOINCREMENT
COMMAND BYTE ADDRESS
ACKNOWLEDGE FROM MAX7370
P0SLAVE ADDRESSCOMMAND BYTEDATA BYTE
R/W
Figure 8. N Data Bytes Received
Message Format for Reading
the Keyscan Controller
The device is read using the internally stored command
byte as an address pointer, the same way the stored
command byte is used as an address pointer for a
write. The pointer generally autoincrements after each
data byte is read using the same rules as for a write
(Table 4). Thus, a read is initiated by first configuring the
device’s command byte by performing a write (Figure 6).
The master can now read N consecutive bytes from the
device, with the first data byte being read from the register addressed by the initialized command byte. When
performing read-after-write verification, remember to
reset the command byte’s address because the stored
command byte address is generally autoincremented
after the write (Figure 8, Table 4).
with I2C Interface and High Level of ESD Protection
Operation with Multiple Masters
When the device is operated on a two-wire interface with
multiple masters, a master reading the device uses a
repeated start between the write that sets the device’s
address pointer, and the read(s) that takes the data
from the location(s). This is because it is possible for
master 2 to take over the bus after master 1 has set
up the device’s address pointer but before master 1
has read the data. If master 2 subsequently resets the
device’s address pointer, master 1’s read can be from an
unexpected location.
Command Address Autoincrementing
Address autoincrementing allows the device to be
configured with fewer transmissions by minimizing the
number of times the command address needs to be
sent. The command address stored in the device generally increments after each data byte is written or read
(Table 4). Autoincrement only functions when doing a
multiburst read or write.
Applications Information
Reset from I2C
After a catastrophic event such as ESD discharge or
microcontroller reset, use bit D7 of the configuration register (0x01) as a software reset for the key switches. Use
bit D4 of the GPIO global configuration register (0x40) as
a software reset for the GPIOs.
Ghost-Key Elimination
Ghost keys are a phenomenon inherent with key-switch
matrices. When three switches located at the corners
of a matrix rectangle are pressed simultaneously, the
switch that is located at the last corner of the rectangle
(the ghost key) also appears to be pressed. This occurs
because the potentials at the two sides of the ghost-key
switch are identical due to the other three connections—
the switch is electrically shorted by the combination of
the other three switches (Figure 9). Because the key
appears to be pressed electrically, it is impossible to
detect which of the four keys is the ghost key.
The device employs a proprietary scheme that detects
any three-key combination that generates a fourth ghost
key, and does not report the third key that causes a
ghost-key event. This means that although ghost keys
are never reported, many combinations of three keys
are effectively ignored when pressed at the same time.
Applications requiring three-key combinations (such as
<Ctrl><Alt><Del>) must ensure that the three keys are
not wired in positions that define the vertices of a rectangle (Figure 10). There is no limit on the number of keys
that can be pressed simultaneously as long as the keys
do not generate ghost-key events and the FIFO is not full.
Low-EMI Operation
The device uses two techniques to minimize EMI radiating from the key-switch wiring. First, the voltage across
the switch matrix never exceeds 0.5V if not in sleep
mode, independent of supply voltage VCC. This reduces
the voltage swing at any node when a switch is pressed
to 0.5V (max). Second, the keys are not dynamically
scanned, which would cause the key-switch wiring to
continuously radiate interference. Instead, the keys are
monitored for current draw (only occurs when pressed),
and debounce circuitry only operates when one or more
keys are actually pressed.
with I2C Interface and High Level of ESD Protection
Switch On-Resistance
The device is designed to be insensitive to resistance,
either in the key switches, or the switch routing to and
from the appropriate COL_ and ROW_ up to 5kI (max).
These controllers are therefore compatible with low-cost
membrane and conductive carbon switches.
Hot Insertion
The INT, SCL, and AD0 inputs and SDA remain high
impedance with up to 5.5V asserted on them when the
device powers down (VCC = 0V). I/O ports remain high
impedance with up to 5.5V asserted on them when not
powered. Use the device in hot-swap applications.
Staggered PWM
The LED’s on-time in each PWM cycle is phase delayed by
45N into four evenly spaced start positions. Optimize phasing, when using fewer than four ports as constant-current
Table 5. ESD Test Levels
1A—CONTACT DISCHARGE1B—AIR DISCHARGE
LEVEL
1212
2424
3638
48415
XSpecialXSpecial
X = Open level. The level has to be specified in the dedicated
equipment specification. If higher voltages than those shown
are specified, special test equipment might be needed.
TEST VOLTAGE
(kV)
LEVEL
TEST
VOLTAGE (kV)
outputs, by allocating the ports with the most appropriate
start positions. For example, if using two constant-current
outputs, choose COL4 and COL6 because their PWM
start positions are evenly spaced. In general, choose
the ports that spread the current demand from the ports’
load supply.
Power-Supply Considerations
The device operates with a 1.62V to 3.6V power-supply
voltage. Bypass the power supply (VCC) to GND with a
0.1µF or higher ceramic capacitor as close as possible
to the device. Bypass the logic power supply (VLA) to
GND with a 0.1µF or higher ceramic capacitor as close
as possible to the device.
ESD Protection
All the device pins meet the ±2.5kV Human Body Model
ESD tolerances. Key-switch inputs and GPIOs meet IEC
61000-4-2 ESD protection. The IEC test stresses consist
of 10 consecutive ESD discharges per polarity at the
maximum specified level and below (per IEC 61000-4-2).
Test criteria include:
with I2C Interface and High Level of ESD Protection
Register Tables
Table 7. Keys FIFO Register Format (0x00)
SPECIAL FUNCTION
The key number indicated by
D[5:0] is a key event. D7 is
always for a keypress of key 62
and key 63. When D7 is 0, the
key read is the last data in the
FIFO. When D7 is 1, there is
more data in the FIFO. When D6
is 1, key data read from the FIFO
is a key release. When D6 is 0,
key data read from the FIFO is a
keypress.
FIFO is empty.00111111
FIFO is overflow. Continue to
read data in the FIFO.
Key 63 is pressed. Read one
more time to determine whether
there is more data in the FIFO.
Key 63 is released. Read one
more time to determine whether
there is more data in the FIFO.
D7D6D5D4D3D2D1D0
FIFO not-
empty flag
01111111
10111111
11111111
Key-
release
flag
KEYS FIFO REGISTER DATA
Key number/key event
Key repeat. Indicates the last
data in the FIFO.
Key repeat. Indicates more data
in the FIFO.
Key 62 is pressed. Read one
more time to determine whether
there is more data in the FIFO.
Key 62 is released. Read one
more time to determine whether
there is more data in the FIFO.
Key-switch operating mode. Key switches always remain active
when constant-current PWM is enabled (bit 4 of register 0x40 is
high), regardless of autosleep, autowake, or an I2C write to this bit.
Key-switch sleep
mode. The entire
chip is shut down.
Key-switch operating
mode.
INT cleared after host read. In this mode, I2C should read the
FIFO until interrupt condition is removed or further INT could be
lost.
When constant-current PWM is disabled
(bit 4 of register 0x40 is low), I2C write,
autosleep, and autowake all can change
this bit. This bit can be read back by I2C
any time for current status.
with I2C Interface and High Level of ESD Protection
Table 13. Key-Switch Array Size Register (0x30)
REGISTER DATA
REGISTER DESCRIPTION
No rows are key switches0000
ROW0 is a key switch0001
ROW0 to ROW1 are key switches0010
ROW0 to ROW2 are key switches0011
ROW0 to ROW3 are key switches0100
ROW0 to ROW4 are key switches0101
ROW0 to ROW5 are key switches0110
ROW0 to ROW6 are key switches0111
ROW0 to ROW7 are key switches1XXX
No columns are key switches
COL0 is a key switch0001
COL0 to COL1 are key switches0010
COL0 to COL2 are key switches0011
COL0 to COL3 are key switches0100
COL0 to COL4 are key switches0101
COL0 to COL5 are key switches0110
COL0 to COL6 are key switches0111
COL0 to COL7 are key switches1XXX
0GPIO function
1LED driver enable
0GPIO function
1LED driver enable
0GPIO function
1LED driver enable
0GPIO function
1LED driver enable
0
0
0
0
MAX7370
8 x 8 Key-Switch Controller and LED Driver/GPIOs
with I2C Interface and High Level of ESD Protection
Table 15. GPIO Direction 1 Register (0x34)
REGISTER BITDESCRIPTIONVALUEFUNCTIONDEFAULT VALUE
D7ROW7
D6ROW6
D5ROW5
D4ROW4
D3ROW3
D2ROW2
D1ROW1
D0ROW0
0Set as input pin
1Set as output pin
0Set as input pin
1Set as output pin
0Set as input pin
1Set as output pin
0Set as input pin
1Set as output pin
0Set as input pin
1Set as output pin
0Set as input pin
1Set as output pin
0Set as input pin
1Set as output pin
0Set as input pin
1Set as output pin
0
0
0
0
0
0
0
0
Table 16. GPIO Direction 2 Register (0x35)
REGISTER BITDESCRIPTIONVALUEFUNCTIONDEFAULT VALUE
D7COL7
D6COL6
D5COL5
D4COL4
D3COL3
D2COL2
D1COL1
D0COL0
0Set as input pin
1Set as output pin
0Set as input pin
1Set as output pin
0Set as input pin
1Set as output pin
0Set as input pin
1Set as output pin
0Set as input pin
1Set as output pin
0Set as input pin
1Set as output pin
0Set as input pin
1Set as output pin
0Set as input pin
1Set as output pin
with I2C Interface and High Level of ESD Protection
Table 17. GPO Output Mode 1 Register (0x36)
REGISTER BITDESCRIPTIONVALUEFUNCTIONDEFAULT VALUE
D7ROW7
D6ROW6
D5ROW5
D4ROW4
D3ROW3
D2ROW2
D1ROW1
D0ROW0
0Port is an open-drain output
1Port is a push-pull output
0Port is an open-drain output
1Port is a push-pull output
0Port is an open-drain output
1Port is a push-pull output
0Port is an open-drain output
1Port is a push-pull output
0Port is an open-drain output
1Port is a push-pull output
0Port is an open-drain output
1Port is a push-pull output
0Port is an open-drain output
1Port is a push-pull output
0Port is an open-drain output
1Port is a push-pull output
1
1
1
1
1
1
1
1
Table 18. GPO Output Mode 2 Register (0x37)
REGISTER BITDESCRIPTIONVALUEFUNCTIONDEFAULT VALUE
D7COL70Port is an open-drain output0
D6COL60Port is an open-drain output0
D5COL50Port is an open-drain output0
D4COL40Port is an open-drain output0
D3
D2COL2
D1COL1
D0COL0
Note: When programmed as GPO, COL7–COL4 are always open drain and bits D[7:4] are not writable.
COL3
0Port is an open-drain output
1Port is a push-pull output
0Port is an open-drain output
1Port is a push-pull output
0Port is an open-drain output
1Port is a push-pull output
0Port is an open-drain output
1Port is a push-pull output
with I2C Interface and High Level of ESD Protection
Table 19. GPIO Supply Voltage 1 Register (0x38)
REGISTER BITDESCRIPTIONVALUEFUNCTIONDEFAULT VALUE
D7ROW7
D6ROW6
D5ROW5
D4ROW4
D3ROW3
D2ROW2
D1ROW1
D0ROW0
0ROW7 supplied by V
1ROW7 supplied by V
0ROW6 supplied by V
1ROW6 supplied by V
0ROW5 supplied by V
1ROW5 supplied by V
0ROW4 supplied by V
1ROW4 supplied by V
0ROW3 supplied by V
1ROW3 supplied by V
0ROW2 supplied by V
1ROW2 supplied by V
0ROW1 supplied by V
1ROW1 supplied by V
0ROW0 supplied by V
1ROW0 supplied by V
CC
LA
CC
LA
CC
LA
CC
LA
CC
LA
CC
LA
CC
LA
CC
LA
0
0
0
0
0
0
0
0
Table 20. GPIO Supply Voltage 2 Register (0x39)
REGISTER BITDESCRIPTIONVALUEFUNCTIONDEFAULT VALUE
D7COL7
D6COL6
D5COL5
D4COL4
D3COL3
D2COL2
D1COL1
D0COL0
0COL7 supplied by V
1COL7 supplied by V
0COL6 supplied by V
1COL6 supplied by V
0COL5 supplied by V
1COL5 supplied by V
0COL4 supplied by V
1COL4 supplied by V
0COL3 supplied by V
1COL3 supplied by V
0COL2 supplied by V
1COL2 supplied by V
0COL1 supplied by V
1COL1 supplied by V
0COL0 supplied by V
1COL0 supplied by V
with I2C Interface and High Level of ESD Protection
Table 24. GPIO Global Configuration Register (0x40)
REGISTER BITDESCRIPTIONVALUEFUNCTIONDEFAULT VALUE
D[7:6]Reserved0—00
0Disabled
D5
D4GPIO enable
D3GPIO reset
D[2:0]Fade-in/out time
I2C timeout
interrupt enable
1
0
1
0Normal operation
1
000No fading
XXX
INT is asserted when I2C bus times out. INT is
deasserted when a read is performed on the I2C
timeout flag register (0x48).
PWM, constant-current circuits, and GPIs are
shut down. GPO values depend on their setting.
Register 0x31 to 0x5B values are stored and
cannot be changed. The entire part is shut down
if the key switches are in sleep mode
(D7 of register 0x01).
Normal GPIO operation. PWM, constant-current
circuits, and GPIOs are enabled regardless of
key-switch sleep-mode state (see Table 8).
Return all GPIO registers (registers 0x31 to 0x5B)
to their POR value. This bit is momentary and
resets itself to 0 after the write cycle.
PWM intensity ramps up (down) between the
common PWM value and 0% duty cycle in 16
steps over the following time period:
D[2:0] = 001 = 256ms
D[2:0] = 010 = 512ms
D[2:0] = 011 = 1024ms
D[2:0] = 100 = 2048ms
D[2:0] = 101 = 4096ms
D[2:0] = 110/111 = Undefined
with I2C Interface and High Level of ESD Protection
Table 26. LED Constant-Current Setting Register (0x43)
REGISTER BITDESCRIPTIONVALUEFUNCTIONDEFAULT VALUE
D[7:6]Reserved11Set always as 1111
D[5:1]Reserved00000—00000
D0
Constant-current
setting
Table 27. Common PWM Register (0x45)
REGISTER DESCRIPTION
Power-up default setting
Common PWM ratio is 0/256
Common PWM ratio is 1/25600000001
Common PWM ratio is 2/25600000010
Common PWM ratio is 3/25600000011
Common PWM ratio is 252/25611111100
Common PWM ratio is 253/25611111101
Common PWM ratio is 254/25611111110
Common PWM ratio is 256/256 (100% duty cycle)11111111
0Constant current is 20mA
1Constant current is 10mA
D7D6D5D4D3D2D1D0
00000000
⋮
0
REGISTER DATA
COMMON PWM
Table 28. I2C Timeout Flag Register (0x48) (Read Only)
No I2C timeout has occurred since last read or
POR.
I2C timeout has occurred since last read or POR.
This bit is reset to zero when a read is performed
on this register. I2C timeouts must be enabled for
this function to work (see Table 8).
0
MAX7370
8 x 8 Key-Switch Controller and LED Driver/GPIOs
with I2C Interface and High Level of ESD Protection
Table 29. COL4–COL7 Individual PWM Ratio Registers (0x50 to 0x53)
REGISTER DATA
REGISTER DESCRIPTION
Power-up default setting
PORT PWM ratio is 0/256
PORT PWM ratio is 1/25600000001
PORT PWM ratio is 2/25600000010
PORT PWM ratio is 3/25600000011
PORT PWM ratio is 252/25611111100
PORT PWM ratio is 253/25611111101
PORT PWM ratio is 254/25611111110
PORT PWM ratio is 256/256 (100% duty cycle)11111111
Table 30. COL4–COL7 LED Configuration Registers (0x54 to 0x57)
D7D6D5D4D3D2D1D0
PORT PWM
00000000
⋮
REGISTER BITDESCRIPTIONVALUEFUNCTIONDEFAULT VALUE
D[7:6]Don’t care00—00
Port uses individual PWM intensity register to set
the PWM ratio
Port uses common PWM intensity register to set
the PWM ratio
0
000
00
D5Common PWM
D[4:2]Blink period
D[1:0]Blink-on time
0
1
000Port does not blink
001Port blink period is 256ms
010Port blink period is 512ms
011Port blink period is 1024ms
100Port blink period is 2048ms
101Port blink period is 4096ms
110/111Undefined
00LED is on for 50% of the blink period
01LED is on for 25% of the blink period
10LED is on for 12.5% of the blink period
11LED is on for 6.25% of the blink period
with I2C Interface and High Level of ESD Protection
Table 31. Interrupt Mask 1 Register (0x58)
REGISTER BITDESCRIPTIONVALUEFUNCTIONDEFAULT VALUE
D7ROW7
D6ROW6
D5ROW5
D4ROW4
D3ROW3
D2ROW2
D1ROW1
D0ROW0
0Interrupt is not masked
1Interrupt is masked
0Interrupt is not masked
1Interrupt is masked
0Interrupt is not masked
1Interrupt is masked
0Interrupt is not masked
1Interrupt is masked
0Interrupt is not masked
1Interrupt is masked
0Interrupt is not masked
1Interrupt is masked
0Interrupt is not masked
1Interrupt is masked
0Interrupt is not masked
1Interrupt is masked
1
1
1
1
1
1
1
1
Table 32. Interrupt Mask 2 Register (0x59)
REGISTER BITDESCRIPTIONVALUEFUNCTIONDEFAULT VALUE
D7COL7
D6COL6
D5COL5
D4COL4
D3COL3
D2COL2
D1COL1
D0COL0
0Interrupt is not masked
1Interrupt is masked
0Interrupt is not masked
1Interrupt is masked
0Interrupt is not masked
1Interrupt is masked
0Interrupt is not masked
1Interrupt is masked
0Interrupt is not masked
1Interrupt is masked
0Interrupt is not masked
1Interrupt is masked
0Interrupt is not masked
1Interrupt is masked
0Interrupt is not masked
1Interrupt is masked
with I2C Interface and High Level of ESD Protection
Wafer-Level Packaging (WLP)
Applications Information
For the latest application details on WLP construction,
dimensions, tape-carrier information, PCB techniques,
bump-pad layout, and recommended reflow temperature profile, as well as the latest information on reliability testing results, refer to Application Note 1891:
Wafer-Level Packaging (WLP) and Its Applications,
available at www.maxim-ic.com.
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
24 TQFN-EPT243A3+1
25 WLPW252F2+1
PACKAGE
CODE
OUTLINE
NO.
21-018890-0122
21-0453
LAND
PATTERN NO.
Refer to
Application
Note 1891
Chip Information
PROCESS: BiCMOS
Ordering Information
PARTTEMP RANGEPIN-PACKAGE
MAX7370ETG+
MAX7370EWA+**
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed. pad.
**Future product—contact factory for availability.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical
Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 37