MAXIM MAX7370 Technical data

EVALUATION KIT AVAILABLE

19-5950; Rev 1; 3/12

MAX7370

8 x 8 Key-Switch Controller and LED Driver/GPIOs

with I2C Interface and High Level of ESD Protection

General Description

The MAX7370 I2C-interfaced peripheral provides microprocessors with management of up to 64 key switches, with optional GPIO and PWM-controlled LED drivers.

The key-switch drivers interface with metallic or resistive switches with on-resistances up to 5kI. Key inputs are monitored statically, not dynamically, to ensure low-EMI operation. The IC features autosleep and autowake modes to further minimize the power consumption of the device. The autosleep feature puts the device in a low-power state (1µA typ) after a timeout period. The autowake feature configures the device to return to normal operating mode from sleep upon a keypress.

The key controller debounces and maintains a FIFO buffer of keypress and release events (including autorepeat, if enabled). An interrupt (INT) output can be configured to alert keypresses, as they occur, or at the maximum rate.

The same index rows and columns in the device can be used as a direct logic-level translator.

If the device is not used for key-switch control, all keyboard pins can be used as GPIOs. Each GPIO can be programmed to one of the two externally applied logic voltage levels. Four column ports (COL7–COL4) can also be configured as LED drivers that feature constant-current and PWM intensity control. The maximum constant-current level for each open-drain LED port is 20mA. The intensity of the LED on each open-drain port can be individually adjusted through a 256-step PWM control.

The device is offered in a 24-pin (3.5mm x 3.5mm) TQFN package with an exposed pad, and small 25-bump (2.159mm x 2.159mm) wafer-level package (WLP) for cell phones, pocket PCs, and other portable consumer electronic applications.

The device operates over the -40°C to +85°C extended temperature range.

Applications

Cell Phones

Notebooks

PDAs

Handheld Games

Portable Consumer Electronics

For related parts and recommended products to use with this part, refer to www.maxim-ic.com/MAX7370.related.

Features

S Monitors Up to 64 Keys S Integrated High-ESD Protection

±8kV IEC 61000-4-2 Contact Discharge ±15kV IEC 61000-4-2 Air-Gap Discharge

S Keyscan Uses Static Matrix Monitoring for

Low-EMI Operation

S Four LED Driver Pins on COL7–COL4 S 5V Tolerant, Open-Drain I/O Ports Capable of

Constant-Current LED Drive

S 256-Step PWM Individual LED Intensity-Control

Accuracy

S Individual LED Blink Rates and Common LED

Fade In/Out Rates from 256ms to 4096ms

S FIFO Queues Up to 16 Debounced Key Events S User-Configurable Keypress and Release

Debounce Time (2ms to 32ms)

S Key-Switch Interrupt (INT) on Each Debounced

Event/FIFO Level, or End-of-Definable Time Period

S 1.62V to 3.6V Operating Supply Voltage S Individually Programmable GPIOs to Two Logic

Levels

S 8-Channel Individual Programmable Level

Translators

S Provides Optional GPIOs on all ROW� and COL�

Pins

S Supports Hot Insertion S 400kbps, 5.5V Tolerant I2C Serial Interface with

Selectable Bus Timeout

Ordering Information appears at end of data sheet.

Typical Operating Circuit

+5V

I/O I/O

8

4

32 KEYS

MCU

INT SDA SCL

AD0

+1.8V

V

CC

MAX7370

GND

+2.6V

V

LA

ROW[0:7]

COL[0:3]

COL4 COL5 COL6 COL7

�� Maxim Integrated Products 1

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

MAX7370

8 x 8 Key-Switch Controller and LED Driver/GPIOs

with I2C Interface and High Level of ESD Protection

ABSOLUTE MAXIMUM RATINGS

VCC, VLA to GND ....................................................-0.3V to +4V

COL3–COL0, ROW7–ROW0 to GND ....... -0.3V to (VCC + 0.3V)

COL7–COL4 to GND ............................................... -0.3V to +6V

SDA, SCL, AD0, INT to GND ..................................-0.3V to +6V

VLA to VCC ...........................................................-0.3V to +2.3V

DC Current on COL7–COL4 to GND .................................25mA

DC Current on COL3–COL0, ROW7–ROW0 to GND ...........7mA

VCC, VLA, GND Current .....................................................80mA

DC Current VCC, VLA to COL3–COL0, ROW7–ROW0 .........5mA

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

PACKAGE THERMAL CHARACTERISTICS (Note 1)

24 TQFN

Junction-to-Ambient Thermal Resistance (BJA) .........65.1°C/W

Junction-to-Case Thermal Resistance (BJC) ................5.4°C/W

Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-

layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.

Continuous Power Dissipation (TA = +70°C)

24-Pin TQFN (derate 15.4mW/°C above +70°C) ......1229mW

25-Bump WLP (derate 19.2mW/°C above +70°C) ......850mW

Operating Temperature Range .......................... -40°C to +85°C

Junction Temperature .....................................................+150°C

Storage Temperature Range ............................ -65°C to +150°C

Lead Temperature (TQFN) (soldering, 10s) ...................+300°C

Soldering Temperature (reflow) ......................................+260°C

25 WLP

Junction-to-Ambient Thermal Resistance (BJA) ...........52°C/W

ELECTRICAL CHARACTERISTICS

(VCC = 1.62V to 3.6V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = 3.3V, TA = +25NC.) (Notes 2, 3)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Operating Supply Voltage V Second Logic Supply V

Operating Supply Current I

Sleep-Mode Supply Current I

POR Threshold V

KEY-SWITCH SPECIFICATIONS

Key-Switch Source Current I Key-Switch Source Voltage V Key-Switch Resistance R Startup Time from Sleep t

GPIO SPECIFICATIONS

External Supply Voltage COL7–COL4 (LED Drivers)

LED Port-to-Port Sink Current Variation

START

V

CC

LA

CC

SL

POR

KEY

LED

All key switches open, oscillator running

N keys pressed

Not using GPO or LED configuration 1.8 3

(Note 4) 5

VCC = 3.3V, VOL = 1V, TA = +25NC, 10mA output mode

1.62 3.3 3.6 V V

CC

3.3 3.6 V

50 65

50 + 28 O N

1.2 V

28 40

0.45 0.5 V

2 2.7 ms

5 V

Q1.5 Q2.4

FA

kI

%

�� Maxim Integrated Products 2

MAX7370

8 x 8 Key-Switch Controller and LED Driver/GPIOs

with I2C Interface and High Level of ESD Protection

ELECTRICAL CHARACTERISTICS (continued)

(VCC = 1.62V to 3.6V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = 3.3V, TA = +25NC.) (Notes 2, 3)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

8.6 11.4

9.5

18.13 21.52

19.05

0.7 O V

S

0.3 O V

-2 +2

20 pF

VCC -

120

VCC -

250

0.7 O V

-1 +1

VCC -

40

VCC -

70

CC

0.3 O V

CC

mA

V

S

FA

mV

V

FA

10mA Port Sink Current COL7–COL4

20mA Port Sink Current COL7–COL4

Input High Voltage COL_, ROW_

Input Low Voltage COL_, ROW_

Input Leakage Current COL3–COL0, ROW_

Input Leakage Current COL7–COL4

Input Capacitance COL _, ROW_

Maximum Allowable Load Capacitance for Keyscan Function

Output Low Voltage COL_, ROW_

Output High Voltage COL3–COL0, ROW_

Output Logic-Low Voltage (INT)

PWM Frequency f

SERIAL-INTERFACE SPECIFICATIONS

Input High Voltage SDA, SCL, AD0

Input Low Voltage SDA, SCL, AD0

Input Leakage Current SDA, SCL, AD0

Output Logic-Low Voltage SDA

Input Capacitance SDA, SCL, AD0

I

LEAKAGE

I

LEAKAGE

I

LEAKAGE

I

OL

I

OL

V

IH

V

IL

C

IN

V

OL

V

OH

V

OL

PWM

V

IH

V

IL

V

OL

C

IN

VOL = 1V

VOL = 0.5V

VOL = 1V

VOL = 0.5V

VS = VCC or VLA depending on reference logic level setting

Input voltage = VCC or V

Input voltage = 5V -1 +1

N keys pressed simultaneously 500 pF

VCC = 1.62V and I VCC = 1.62V and I

VCC = 1.62V and I

I

= 6mA 0.6 V

SINK

Derived from oscillator clock 500 Hz

Input voltage = 5.5V or V

I

= 6mA 0.6 V

SINK

(Notes 4, 5) 10 pF

TA = +25NC VCC = 3.3V 9.04 10 10.96

VCC = 3.6V, TA = +25NC

TA = +25NC VCC = 3.3V 18.47 20 21.34

VCC = 3.6V, TA = +25NC

GND

= 2.5mA 50 100

SINK

= 5mA 80 250

SINK

SOURCE

= 2.5mA

= 5mA

GND

�� Maxim Integrated Products 3

MAX7370

8 x 8 Key-Switch Controller and LED Driver/GPIOs

with I2C Interface and High Level of ESD Protection

ELECTRICAL CHARACTERISTICS (continued)

(VCC = 1.62V to 3.6V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = 3.3V, TA = +25NC.) (Notes 2, 3)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

I2C TIMING SPECIFICATIONS

SCL Serial-Clock Frequency f

Bus Free Time Between a STOP and START Condition

Hold Time (Repeated) START Condition t Repeated START Condition Setup Time t STOP Condition Setup Time t Data Hold Time t Data Setup Time t SCL Clock Low Period t SCL Clock High Period t

Rise Time of Both SDA and SCL Signals, Receiving

Fall Time of Both SDA and SCL Signals, Receiving

Fall Time of SDA Signal, Transmitting t

Pulse Width of Spike Suppressed t Capacitive Load for Each Bus Line C Bus Time Out t

ESD PROTECTION

t

HD, STA

SU, STA

SU, STO

HD, DAT

SU, DAT

LOW

HIGH

F, TX

TIMEOUT

SCL

BUF

t

SP

Bus timeout enabled 0.05 400 Bus timeout disabled 0 400

1.3

0.6

(Note 6) 0.9

100 ns

1.3

0.7

(Notes 4, 5)

R

(Notes 4, 5)

F

(Notes 4, 7)

(Notes 4, 8) 50 ns (Note 4) 400 pF

B

14 19 27 ms

20 +

0.1C

20 +

0.1C

20 +

0.1C

B

kHz

Fs

Fs Fs Fs Fs

Fs Fs

300 ns

250 ns

IEC 61000-4-2 Air-Gap Discharge

ROW7–ROW0, COL7–COL0

IEC 61000-4-2 Contact Discharge

All Other Pins Human Body Model

Note 2: All parameters are tested at TA = +25°C. Specifications over temperature are guaranteed by design. Note 3: All digital inputs at VCC or GND. Note 4: Guaranteed by design. Note 5: CB = total capacitance of one bus line in pF. tR and tF measured between 0.8V and 2.1V. Note 6: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) to bridge

the undefined region of SCL’s falling edge.

Note 7: I Note 8: Input filters on the SDA, SCL, and AD0 inputs suppress noise spikes less than 50ns.

= 6mA. CB = total capacitance of one bus line in pF. tR and tF measured between 0.8V and 2.1V.

SINK

�� Maxim Integrated Products 4

Q15

Q8

Q2.5

kV

MAX7370

8 x 8 Key-Switch Controller and LED Driver/GPIOs

with I2C Interface and High Level of ESD Protection

Typical Operating Characteristics

(VCC = 2.5V, VLA = 2.5V, TA = +25NC, unless otherwise noted.)

GPO OUTPUT LOW VOLTAGE

vs. SINK CURRENT (COL7–COL4)

120

VCC = 2.4V

100

80

60

40

GPO OUTPUT LOW VOLTAGE (mV)

20

0

0 20

TA = +25°C

SINK CURRENT (mA)

TA = +85°C

TA = -40°C

SUPPLY CURRENT vs. SUPPLY VOLTAGE

60

AUTOSLEEP = OFF

55

50

45

40

SUPPLY CURRENT (µA)

35

30

1.6 3.6

TA = +25°C

SUPPLY VOLTAGE (V)

TA = +85°C

TA = -40°C

GPO OUTPUT LOW VOLTAGE

vs. SINK CURRENT (COL7–COL4)

120

VCC = 3.0V

100

MAX7370 toc01

80

60

40

GPO OUTPUT LOW VOLTAGE (mV)

20

18161412108642

0

0 20

TA = +25°C

SINK CURRENT (mA)

TA = +85°C

TA = -40°C

18161412108642

120

100

MAX7370 toc02

GPO OUTPUT LOW VOLTAGE (mV)

KEY-SWITCH SOURCE CURRENT

vs. SUPPLY VOLTAGE

27.0 V

= 0V

COL0

26.5

MAX7370 toc04

26.0

25.5

25.0

24.5

KEY-SWITCH SOURCE CURRENT (µA)

3.43.23.02.82.62.42.22.01.8

24.0

1.6 3.6

TA = +85°C

TA = +25°C

TA = -40°C

3.43.23.02.82.62.42.22.01.8

SUPPLY VOLTAGE (V)

1.8

1.6

MAX7370 toc05

1.4

1.2

1.0

0.8

0.6

0.4

SLEEP-MODE SUPPLY CURRENT (µA)

0.2

GPO OUTPUT LOW VOLTAGE

vs. SINK CURRENT (COL7–COL4)

VCC = 3.6V

TA = +85°C

80

60

40

20

0

0 20

TA = +25°C

TA = -40°C

SINK CURRENT (mA)

SLEEP-MODE SUPPLY CURRENT

vs. SUPPLY VOLTAGE

TA = +85°C

TA = +25°C

TA = -40°C

0

SUPPLY VOLTAGE (V)

MAX7370 toc03

18161412108642

MAX7370 toc06

3.43.23.02.82.62.42.22.01.81.6 3.6

CONSTANT-CURRENT GPIO OUTPUT SINK

CURRENT vs. OUTPUT VOLTAGE (COL7–COL4)

25

VCC = 2.4V

20

15

10

5

0

0 3.0

CONSTANT-CURRENT GPIO OUTPUT SINK CURRENT (mA)

TA = +85°C

TA = +25°C

TA = -40°C

2.52.01.51.00.5

OUTPUT VOLTAGE (V)

�� Maxim Integrated Products 5

CONSTANT-CURRENT GPIO OUTPUT SINK

CURRENT vs. OUTPUT VOLTAGE (COL7–COL4)

25

VCC = 3.0V

MAX7370 toc07

20

15

10

5

0

0 3.0

CONSTANT-CURRENT GPIO OUTPUT SINK CURRENT (mA)

TA = +85°C

TA = -40°C

OUTPUT VOLTAGE (V)

TA = +25°C

CONSTANT-CURRENT GPIO OUTPUT SINK

CURRENT vs. OUTPUT VOLTAGE (COL7–COL4)

25

VCC = 3.6V

MAX7370 toc08

2.52.01.51.00.5

20

15

10

5

0

0 3.0

CONSTANT-CURRENT GPIO OUTPUT SINK CURRENT (mA)

TA = +85°C

MAX7370 toc09

TA = +25°C

TA = -40°C

2.52.01.51.00.5

OUTPUT VOLTAGE (V)

MAX7370

8 x 8 Key-Switch Controller and LED Driver/GPIOs

with I2C Interface and High Level of ESD Protection

Pin/Bump Configurations

TOP VIEW

(BUMP SIDE DOWN)

MAX7370

TOP VIEW

ROW0

ROW1

ROW2

ROW3

GND

ROW4

CC

INT

V

18 17 16 15 14 13

19

20

21

22

23

24

1+23456

ROW5

SCL

MAX7370

ROW6

ROW7

COL7

SDA

AD0

EP*

COL6

LA

V

COL5

12

COL0

11

COL1

10

COL2

COL3

9

GND

8

COL4

7

TQFN

*CONNECT EP TO GROUND.

PIN BUMP

TQFN WLP

NAME FUNCTION

1 A2 ROW5 Row 5 Input from Key Matrix or GPIO Port 2 B2 ROW6 Row 6 Input from Key Matrix or GPIO Port 3 A3 ROW7 Row 7 Input from Key Matrix or GPIO Port

4 B3 COL7

5 A4 COL6

6 A5 COL5

7 B4 COL4

8, 23

B1, B5,

C3

GND Ground

Column 7 Output from Key Matrix or Open-Drain GPIO Port. COL7 can be configured as a constant-current sink.

Column 6 Output from Key Matrix or Open-Drain GPIO Port. COL6 can be configured as a constant-current sink.

Column 5 Output from Key Matrix or Open-Drain GPIO Port. COL5 can be configured as a constant-current sink.

Column 4 Output from Key Matrix or Open-Drain GPIO Port. COL4 can be configured as a constant-current sink.

9 C5 COL3 Column 3 Output from Key Matrix or GPIO Port 10 C4 COL2 Column 2 Output from Key Matrix or GPIO Port 11 D5 COL1 Column 1 Output from Key Matrix or GPIO Port 12 E5 COL0 Column 0 Output from Key Matrix or GPIO Port

1234

+

A

ROW4

B

GND

C

ROW3

D

ROW1

E

ROW0

ROW5 ROW7 COL6 COL5

ROW6 COL7 COL4 GND

ROW2 GND COL2 COL3

V

CC

INT

SDA V

SCL AD0 COL0

WLP

Pin/Bump Description

5

COL1

LA

�� Maxim Integrated Products 6

MAX7370

8 x 8 Key-Switch Controller and LED Driver/GPIOs

with I2C Interface and High Level of ESD Protection

Pin Description (continued)

TQFN WLP

13 D4 V

NAME FUNCTION

Second Logic Level for GPIO Level Shifting (where VCC P VLA P 3.6V)

LA

14 E4 AD0 Address Input. Selects up to four device slave addresses (Table 3). 15 D3 SDA I2C-Compatible, Serial-Data I/O 16 E3 SCL I2C-Compatible, Serial-Clock Input 17 E2 18 D2 V

INT Active-Low Key-Switch Interrupt Output. INT is open-drain and requires a pullup resistor.

Positive Supply Voltage. Bypass to GND with a 0.1FF capacitor as close as possible to the device.

CC

19 E1 ROW0 Row 0 Input from Key Matrix or GPIO Port 20 D1 ROW1 Row 1 Input from Key Matrix or GPIO Port 21 C2 ROW2 Row 2 Input from Key Matrix or GPIO Port 22 C1 ROW3 Row 3 Input from Key Matrix or GPIO Port 24 A1 ROW4 Row 4 Input from Key Matrix or GPIO Port

— — EP

Exposed Pad (TQFN Only). Internally connected to GND. Connect to a large ground plane to maximize thermal performance. Not intended as an electrical connection point.

Functional Block Diagram

V

CC

I/O SUPPLY CONTROL

PWM

MAX7370

GPIO

LOGIC

LED ENABLE

PWM SIGNAL

V

LA

INT

SDA

SCL

AD0

COL0

COL1

COL2

COL3

COL4

COL5

COL6

COL7

ROW0

ROW1

ROW2

ROW3

ROW4

ROW5

ROW6

ROW7

128kHz

OSCILLATOR

2

C

I

INTERFACE

BUS TIMEOUT POR

CONTROL

REGISTERS FIFO

KEY-SCAN

LOGIC

COLUMN ENABLE

CURRENT DETECT

GPIO ENABLE

GPIO INPUT

ROW ENABLE

ROW DETECT

GPIO ENABLE

GPIO INPUT

CURRENT

SOURCE

COLUMN

DRIVES/

PUSH-

PULL GPIO/

LED DRIVERS

ROW

DRIVES/

PUSH-

PULL GPIO

�� Maxim Integrated Products 7

MAX7370

8 x 8 Key-Switch Controller and LED Driver/GPIOs

with I2C Interface and High Level of ESD Protection

Detailed Description

autowake are enabled/disabled by programming the

configuration register (0x01). The MAX7370 is a microprocessor peripheral low-noise key-switch controller that monitors up to 64 key switches with optional autorepeat, and key events that are presented in a 16-byte FIFO. Key-switch functionality can be traded to provide up to 16 logic inputs. The device also features 12 push-pull GPOs configured for digital I/O and four open-drain GPOs configurable as constantcurrent outputs for LED applications up to 5V. The device supports a second 1.62V to 3.6V power supply for level translation. The second logic supply voltage (VLA) must be set equal to or higher than VCC.

The device features an automatic sleep mode and automatic wakeup that further reduce supply current consumption. The device can be configured to enter sleep mode after a programmable time following a key event.

To prevent overloading the microprocessor with too

many interrupts, interrupt requests can be triggered

after a programmable number of FIFO entries have been

exceeded, and/or after a set period of time (0x05). The

key-switch status is checked by reading the key-switch

FIFO. A 1-byte read access returns both the next key

event in the FIFO (if there is one) and the FIFO status.

Up to four of the key-switch outputs function as open-

drain GPOs capable of driving additional LEDs when the

application requires fewer keys to be scanned. For each

key-switch output used as a GPO, the number of moni-

tored key switches reduces by eight.

The device meets ESD requirements for ±8kV contact dis-

charge and 15kV Air-Gap Discharge on all key-switch pins.

The FIFO content is maintained and can be read in sleep mode. The device does not enter autosleep when a key is held down. The autowake feature takes the device

On power-up, all control registers are set to power-up

values (Table 1) and the device is in sleep mode. out of sleep mode following a keypress. Autosleep and

Table 1. Register Address Map and Power-Up Conditions

Initial Power-Up

ADDRESS

CODE (hex)

0x00 Read only 0x3F Keys FIFO Read FIFO keyscan data out

0x01

0x02 0x03 0x05 0x06 0x30

0x31

0x34

0x35

0x36

0x37

READ/WRITE

R/W

R/W R/W R/W R/W R/W

R/W

�� Maxim Integrated Products 8

POWER-UP

VALUE (hex)

0x0B Configuration

0xFF Debounce Key debounce time setting 0x00 Interrupt 0x00 Key repeat Delay and frequency for key repeat 0x07 Sleep Idle time to autosleep 0xFF Key-switch size Keyscan switch array size

0x00

0xFF

0x0F

REGISTER FUNCTION

LED driver

enable

GPIO

direction 1

GPIO

direction 2

GPO output

mode 1

GPO output

mode 2

Power-down, key-release enable, autowake, and I2C timeout enable

Key-switch interrupt and INT frequency setting

LED driver enable register

GPIO input/output control register 1 for ROW7–ROW0

GPIO input/output control register 2 for COL7–COL0

GPO open-drain/push-pull output setting for ROW7–ROW0

GPO open-drain/push-pull output setting for COL7–COL0

DESCRIPTION

MAX7370

8 x 8 Key-Switch Controller and LED Driver/GPIOs

with I2C Interface and High Level of ESD Protection

Table 1. Register Address Map and Power-Up Conditions (continued)

ADDRESS

CODE (hex)

0x38

0x39

0x3A 0x3B

0x3C

0x40

0x42

0x43

0x45 0x48 Read only 0x00 I2C timeout flag I2C timeout since last POR

0x50

0x51

0x52

0x53

0x54

0x55

0x56

0x57

0x58

0x59

0x5A

0x5B

READ/WRITE

R/W

R/W R/W

R/W

POWER-UP

VALUE (hex)

0x00

0xFF GPIO values 1 Debounced input or output values of ROW7–ROW0 0xFF GPIO values 2 Debounced input or output values of COL7–COL0

0x00

0x00 GPIO debounce ROW7–ROW0 debounce time setting

0xC0

0x00 Common PWM Common PWM duty-cycle setting

0x00

0xFF

0x00

REGISTER

FUNCTION

GPIO supply

voltage 1

GPIO supply

voltage 2

GPIO level-

shifter enable

GPIO global

configuration

LED constant-

current setting

COL4 PWM

ratio

COL5 PWM

ratio

COL6 PWM

ratio

COL7 PWM

ratio

COL4 LED

configuration

COL5 LED

configuration

COL6 LED

configuration

COL7 LED

configuration

Interrupt

mask 1

Interrupt

mask 2

GPI trigger

mode 1

GPI trigger

mode 2

GPIO voltages supplied by VCC or VLA for ROW7–ROW0

GPIO voltages supplied by VCC or VLA for COL7–COL0

GPIO direct level-shifter pair enable

GPIO global enable, GPIO reset, LED fade enable

COL7–COL4 constant-current output setting

COL4 individual duty-cycle setting

COL5 individual duty-cycle setting

COL6 individual duty-cycle setting

COL7 individual duty-cycle setting

COL4 interrupt, PWM mode control, and blinkperiod settings

COL5 interrupt, PWM mode control, and blinkperiod settings

COL6 interrupt, PWM mode control, and blinkperiod settings

COL7 interrupt, PWM mode control, and blinkperiod settings

Interrupt mask for ROW7–ROW0

Interrupt mask for COL7–COL0

GPI edge-triggered detection setting for ROW7–ROW0

GPI edge-triggered detection setting for COL7–COL0

DESCRIPTION

�� Maxim Integrated Products 9

MAX7370

8 x 8 Key-Switch Controller and LED Driver/GPIOs

with I2C Interface and High Level of ESD Protection

Keyscan Controller

Key inputs are scanned statically, not dynamically, to ensure low-EMI operation. Since inputs only toggle in response to switch changes, the key matrix can be routed closer to sensitive circuit nodes.

The keyscan controller debounces and maintains a FIFO buffer of keypress and release events (including autorepeated keypresses, if autorepeat is enabled). Table 2 shows the key-switch order. The user-programmable keyswitch debounce time and autosleep timer are derived from the 64kHz clock, which in turn is derived from the 128kHz oscillator. Time delay for autorepeat and keyswitch interrupt is based on the key-switch debounce time. There is no limitation for the number of keys pressed simultaneously as long as no ghost keys are generated. If the application requires fewer keys to be scanned, the unused key-switch ports can be configured as GPIOs.

Keys FIFO Register (0x00)

The Keys FIFO register contains the information pertaining to the status of the keys FIFO, as well as the key events that have been debounced. See Table 7. Bits D[5:0] denote which of the 64 keys have been debounced and the keys are numbered as shown in Table 2.

Bit D7 indicates if there is more data in the FIFO, except when D[5:0] indicate key 63 or key 62. When D[5:0] indicate key 63 or key 62, the host should read the FIFO one more time to determine whether there is more data in the FIFO. Use key 62 and key 63 for rarely used keys. D6 indicates if it is a keypress or release event, except when D[5:0] indicate key 63 or key 62.

Reading the keyscan FIFO clears the interrupt (INT), depending on the setting of bit D5 in the configuration register (0x01).

Configuration Register (0x01)

The Configuration register controls the I2C bus time-

out feature, enables key-release detection, enables

autowake, and determines how INT is deasserted. Write

to bit D7 to put the device into sleep mode or operating

mode. Autosleep and autowake, when enabled, also

change the status of D7. See Table 8.

Debounce Register (0x02)

The Debounce register sets the keypress and key-

release time for each debounce cycle. Bits D[3:0] set the

debounce time for keypresses, while bits D[7:4] set the

debounce time for key releases. Both debounce times

are configured in increments of 2ms starting at 2ms and

ending at 32ms. See Table 9.

Interrupt Register (0x03)

The Interrupt register contains information related to the

settings of the interrupt request function, as well as the sta-

tus of the INT output. If bits D[7:0] are set to 0x00, the INT

is disabled. There are two types of interrupts, the FIFO-

based interrupt and time-based interrupt. Set bits D[4:0]

to assert interrupts at the end of the selected number of

debounce cycles following a key event. See Table 10.

This number ranges from 1–31 debounce cycles. Setting

bits D[5:7] set the FIFO-based interrupt when there are

2–14 key events stored in the FIFO. Both interrupts can be

configured simultaneously and INT asserts depending on

which condition is met first. INT deasserts depending on

the status of bit D5 in the configuration register.

Autorepeat Register (0x05)

The device autorepeat feature notifies the host that at

least one key has been pressed for a continuous period.

The Autorepeat register enables or disables this feature,

sets the time delay after the last key event before the key-

repeat code (0x7E) is entered into the FIFO, and sets

Table 2. Key-Switch Mapping

PIN COL0 COL1 COL2 COL3 COL4 COL5 COL6 COL7 ROW0 ROW1 ROW2 ROW3 ROW4 ROW5 ROW6 ROW7

KEY 0 KEY 8 KEY 16 KEY 24 KEY 32 KEY 40 KEY 48 KEY 56 KEY 1 KEY 9 KEY 17 KEY 25 KEY 33 KEY 41 KEY 49 KEY 57 KEY 2 KEY 10 KEY 18 KEY 26 KEY 34 KEY 42 KEY 50 KEY 58 KEY 3 KEY 11 KEY 19 KEY 27 KEY 35 KEY 43 KEY 51 KEY 59 KEY 4 KEY 12 KEY 20 KEY 28 KEY 36 KEY 44 KEY 52 KEY 60 KEY 5 KEY 13 KEY 21 KEY 29 KEY 37 KEY 45 KEY 53 KEY 61 KEY 6 KEY 14 KEY 22 KEY 30 KEY 38 KEY 46 KEY 54 KEY 62 KEY 7 KEY 15 KEY 23 KEY 31 KEY 39 KEY 47 KEY 55 KEY 63

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MAX7370

8 x 8 Key-Switch Controller and LED Driver/GPIOs

with I2C Interface and High Level of ESD Protection

the frequency at which the key-repeat code is entered into the FIFO thereafter. The key being pressed is not entered again into the FIFO. Bit D7 specifies whether the autorepeat function is enabled with 0, denoting autorepeat disabled, and 1, denoting autorepeat enabled. Bits D[3:0] specify the autorepeat delay in terms of debounce cycles, ranging from eight debounce cycles to 128 debounce cycles. See Table 11. Bits D[6:4] specify the autorepeat rate or frequency ranging from 4–32 debounce cycles.

Only one autorepeat code is entered into the FIFO, regardless of the number of keys pressed. The autorepeat code continues to be entered in the FIFO at the frequency set by bits D[3:0] until another key event is recorded. Following the key-release event, if any keys are still pressed, the device restarts the autorepeat sequence.

Autosleep Register (0x06)

Autosleep puts the device in sleep mode to draw minimal current. When enabled, the device enters sleep mode if no keys are pressed for the autoshutdown time. See

Table 12.

Key-Switch Array Size Register (0x30)

Bits D[7:4] set the row size of the key-switch array, and bits D[3:0] set the column size of the key-switch array. See Table 13. Set the bits to 0 if no key switches are used. The key-switch array should be connected beginning at ROW0 and COL0. If not used as a key-switch matrix pin, then the pin can function as a GPIO port.

Key-Switch Sleep Mode

In sleep mode, the device draws minimal current. Switchmatrix current sources are turned off and pulled up to VCC. When autosleep is enabled, key-switch inactivity for a period longer than the autosleep time puts the part into sleep mode (FIFO data is maintained). Writing a 1 to D7 or a keypress can take the device out of sleep mode. Bit D7 in the configuration register gives the sleep-mode status and can be read any time.

Autowake

Keypresses initiate autowake and the device goes into operating mode. Keypresses that autowake the device are not lost. When a key is pressed while the device is in sleep mode, all analog circuitry, including switch-matrix

current sources, turn on in 2ms. The initial key needs to be pressed for 2ms plus the debounce time to be stored in the FIFO. Write a 0 to bit D1 in the configuration register (0x01) to disable autowake.

FIFO Overflow

The FIFO overflow status occurs when the FIFO is full (16 bytes) and additional events occur. If key release is disabled, then the FIFO overflow status occurs when the FIFO is full and not upon additional key events. When the FIFO is overflowed, the first byte read from the FIFO buffer is the overflow byte (0x7F). The order of the original 16 bytes of event data is preserved, but further events could be lost. When the FIFO is full, if the 18th key event is a key release, then the FIFO overflow status is removed.

GPIOs

The device has 16 GPIO ports, four of which have LED control functions. The ports can be used as logic inputs or logic outputs. COL7–COL4 are also configurable as constant-current PWM LED drivers. Each port’s logic level is referenced to VCC or VLA. The GPIO ports’ inputs can also be debounced. When in PWM mode, the ports are set up to start their PWM cycle in 45N phase increments. This prevents large current spikes on the LED supply voltage when driving multiple LEDs.

LED Driver Enable Register (0x31)

Bits D[3:0] correspond to COL7–COL4 on the device. Set the corresponding bit to 1 for enabling the LED driver circuitry and 0 for normal GPIO function. See Table 14.

GPIO Direction 1 and 2 Registers (0x34, 0x35)

These registers configure the pins as an input or an output port. GPIO Direction 1 register bits D[7:0] correspond with ROW7–ROW0. See Table 15. GPIO Direction 2 register bits D[7:0] correspond with COL7–COL0. See Table 16. Set the corresponding bit to 0 to configure as input and 1 to configure as output.

When the port is initially programmed as an input, there is a delay of one debounce period prior to detecting a transition on the input port. This is to prevent a false interrupt from occurring when changing a port from an output to an input.

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MAX7370

8 x 8 Key-Switch Controller and LED Driver/GPIOs

with I2C Interface and High Level of ESD Protection

GPO Output Mode 1 and 2 Registers (0x36, 0x37)

These registers configure the pin as an open-drain or push-pull output. GPO Output Mode 1 register bits D[7:0] correspond with ROW7–ROW0. See Table 17. GPO Output Mode 2 register bits D[7:0] correspond with COL7–COL0. See Table 18. Set the corresponding bit to 0 to configure the output mode as open-drain and 1 to configure the output mode as push-pull.

GPIO Supply Voltage 1 and 2

Registers (0x38, 0x39)

These registers configure input and output voltages to be referenced to VCC or VLA. GPIO Supply Voltage 1 register bits D[7:0] correspond with ROW7–ROW0. See

Table 19. GPIO Supply Voltage 2 register bits D[7:0] cor-

respond with COL7–COL0. See Table 20. Set the bit to 0 for input/output voltages referenced to VCC or set the bit to 1 for the input/output voltage referenced to VLA.

GPIO Values 1 and 2 Registers (0x3A, 0x3B)

The GPIO Values 1 and 2 registers contain the debounced input data for all the GPIOs for ROW7–ROW0 and COL7– COL0, respectively. See Tables 21 and 22. There is one debounce period delay prior to detecting a transition on the input port. This prevents a false interrupt from occurring when changing a port from an output to an input. The GPIO Values 1 and 2 registers report the state of all input ports regardless of any interrupt mask settings.

When writing to the GPIO Values 1 and 2 registers, the corresponding port voltage is set high when written 1 or cleared when written 0. Reading the port when configured as an output always returns the value 0 for the corresponding port regardless of the output value.

GPIO Level-Shifter Enable Register (0x3C)

Enabling bit D_ in this register enables the direct level shifter between GPIO pins COL_ and ROW_. See

Table 23. As an example, setting D5 to logic-high

enables level shifting between COL5 and ROW5. The direction of the level shifter is controlled by the GPIO Direction 2 register (0x35). When setting the corresponding bit in the GPIO Direction 2 register to 0, COL_ are inputs, and ROW_ are outputs. When setting the bit to 1, ROW_ become inputs and COL_ become outputs.

GPIO Global Configuration Register (0x40)

The GPIO Global Configuration register controls the main settings for the GPIO ports. See Table 24. Bit D5 enables

interrupt generation for I2C timeouts. D4 is the main enable/shutdown bit for the GPIOs. Bit D3 functions as a software reset for the GPIO registers (0x31 to 0x5B). Bits D[2:0] set the fade-in/out time for the LED drivers.

GPIO Debounce Configuration Register (0x42)

The GPIO Debounce Configuration Register sets the amount of time a GPIO must be held in order for the device to register a logic transition. See Table 25. The GPIO debounce setting is independent of the key-switch debounce setting. Five bits (D[4:0]) set 32 possible debounce times from 9ms up to 40ms.

LED Constant-Current Setting Register (0x43)

The LED Constant-Current Setting register sets the global constant-current amount. See Table 26. Bit D0 selects the global current values between 10mA and 20mA. This setting only applies to the LED driver-enabled pins, COL7–COL4.

Common PWM Ratio Register (0x45)

The Common PWM Ratio register stores the common constant-current output PWM duty cycle. See Table 27. The values stored in this register translate over to a PWM ratio in the same manner as the individual PWM ratio registers (0x50 to 0x53). Ports can use their own individual PWM value or the common PWM value. Write to this register to change the PWM ratio of several ports at once.

I2C Timeout Flag Register (0x48) (Read Only)

The I2C Timeout Flag register contains a single bit (D0) that indicates if an I2C timeout has occurred. See

Table 28. Read this register to clear an I2C timeout-

initiated interrupt.

COL4–COL7 Individual PWM Ratio

Registers (0x50 to 0x53)

Each LED driver port has an individual PWM ratio register, 0x50 to 0x53. See Table 29. Use values 0x00 to 0xFE in these registers to configure the number of cycles out of 256 the output sinks current (LED is on), from 0 cycles to 254 cycles. Use 0xFF to have an output continuously sink current (always on). For applications requiring multiple ports to have the same intensity, program a particular port’s configuration register (0x54 to 0x57) to use the Common PWM Ratio register (0x45). New PWM settings take place at the beginning of a PWM cycle, to allow changes from common intensity to individual intensity with no interruption in the PWM cycle.

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