The MAX7365 is an I2C-interfaced peripheral that provides microprocessors with management of up to 56 key
switches.
Key codes generated for each keypress and release
enable easier implementation of multiple key entries. Key
inputs monitored statically, not dynamically, ensure lowEMI operation. The switches can be metallic or resistive
(carbon) with up to 5kI of resistance.
The device features autosleep and autowake to further
minimize the power consumption of the device. The
autosleep feature puts the device in a low-power state
(1FA typ) after a programmable sleep timeout period.
The autowake feature configures the device to return to
normal operating mode from sleep upon a keypress.
The key controller debounces and maintains a FIFO of keypress and release events (including autorepeat, if enabled).
An interrupt (INT) output can be configured to alert key-
presses either as they occur or at the maximum rate.
Unused key switches can be used as GPI. In addition,
there are five additional general-purpose input/output
(GPIO) ports. GPOs can be programmed as push-pull
or open-drain to high- or low-side output drivers. When
programmed as open drain, an optional on-chip 100kI
pullup/pulldown resister can be enabled.
The device is available in a small (2mm x 2mm) 25-bump
wafer-level package (WLP) for cell phones, pocket PCs,
and other portable consumer electronic applications.
The device operates over the -40NC to +85NC extended
temperature range.
Benefits and Features
S Reduce Processor Load
Monitor Up to 56 Keys
FIFO Queues Up to 16 Debounced Key Events
Hardware Interrupt at the FIFO Level or at the
End-of-Definable Time Period
S Increased Battery Life
Autosleep and Autowake Minimize Current
Consumption
Less Than 1µA Sleep Current
S Save Board Space
Small (2mm x 2mm) and Low-Profile 25-Bump
WLP
S Flexible Design Requirements
1.62V to 3.6V Operation
Proprietary Ghost-Key Detection and Removal
Key Debounce Time User Configurable from
1ms to 31ms
Low-EMI Design Uses Static Matrix Monitoring
Five Additional GPIO Ports
All Key Switches Can Be Used as GPIs
1Mbps, 5.5V Tolerant, Two-Wire Serial Interface
Selectable Two-Wire, Serial-Bus Timeout
Typical Operating Circuit
+1.8V
V
MAX7365
INT
SDA
SCL
DD
GND
GPIO[0:4]
ROW[0:7]
COL[0:6]
5
I/O
8
7
56 KEYS
Applications
Netbooks
Cell Phones
PDAs
Handheld Games
Portable Consumer Electronics
Ordering Information appears at end of data sheet.
For related parts and recommended products to use with this part,
refer to www.maxim-ic.com/MAX7365.related.
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX7365
2
1MHz I
C-Interfaced 8 x 7
Key-Switch Controller with GPIO Ports
ABSOLUTE MAXIMUM RATINGS
VDD to GND ............................................................ -0.3V to 4.0V
ROW7–ROW0, COL6–COL0,
GPIO4–GPIO0 to GND
SDA, SCL, INT to GND
DC Current on ROW7–ROW0, COL6–COL0 to GND
DC Current on GPIO4–GPIO0 to GND
GND Current
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
(VDD = 1.62V to 3.6V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VDD = 3.3V, TA = +25NC.) (Notes 2, 3)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
-
V
Output High Voltage
GPIO_
2
C TIMING SPECIFICATIONS
I
Input Capacitance SCL, SDAC
SCL Serial-Clock Frequencyf
Bus Free Time Between a STOP
and START Condition
Hold Time (Repeated) START
Condition
Repeated START Condition
Setup Time
STOP Condition Setup Timet
Data Hold Timet
Data Setup Timet
SCL Clock Low Periodt
SCL Clock High Periodt
Rise Time of Both SDA and SCL
Signals, Receiving
Fall Time of Both SDA and SCL
Signals, Receiving
Fall Time of SDA Signal,
Transmitting
Pulse Width of Spike Suppressedt
Capacitive Load for Each Bus
Line
Bus Timeoutt
Note 2: All parameters are tested at TA = +25NC. Specifications over temperature are guaranteed by design.
Note 3:
All digital inputs at VDD or V
Note 4: Guaranteed by design.
Note 5: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) to bridge
the undefined region of SCL’s falling edge.
Note 6:
CB = total capacitance of one bus line in pF. tR and tF measured between 0.8V and 2.1V.
Note 7:
I
= 6mA. CB = total capacitance of one bus line in pF. tR and tF measured between 0.8V and 2.1V.
Note 8: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
the device cannot enter autosleep. The autowake feature
takes the device out of sleep mode following a keypress
The MAX7365 is a microprocessor peripheral low-noise,
key-switch controller that monitors up to 56 key switches
with optional autorepeat. Key events are presented in a
16-byte FIFO. Key-switch functionality can be traded to
provide up to 16 logic inputs. The device features an additional five GPIOs. Outputs configured as open drain feature an optional on-chip 100kI pullup/pulldown resistor.
The device features an automatic sleep mode and automatic wakeup that further reduce supply current con-
event. Autosleep and autowake can be disabled.
Interrupt requests can be configured to be issued on a
programmable number of FIFO entries or can be set to
a period of time to prevent overloading the microproces-
sor with too many interrupts. The key-switch status can
be checked at any time by reading the key-switch FIFO.
A 1-byte read access returns both the next key-event in
the FIFO, if there is one, and the FIFO status. Interrupts
are configurable per each input port with edge detection.
sumption. The device can be configured to enter sleep
mode after a programmable time following a key event.
The FIFO content is maintained during sleep mode and
can be read in sleep mode. When a key is held down,
On power-up, all control registers are set to power-up
values (Table 1), and the device is in sleep mode.
Table 1. Register Address Map and Power-Up Condition
ADDRESS
CODE (hex)
0x00Read only0x3FKeys FIFORead FIFO keyscan data out
0x01
0x02
0x03
0x05
0x06
0x30
0x31
0x32
0x33Read only0xFFGPIs LSB ValueGPI[7:0] (ROW0, COL[6:0]) port input values
0x34Read only0x7FGPIs MSB ValueGPI[14:8] (ROW[7:1]) port input values
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
READ/
WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POWER-UP
VALUE (hex)
0x0BConfiguration
0xFFKey-Switch Debounce Key debounce time setting
0x00Key-Switch Interrupt
0x00Key-Switch Autorepeat Delay and frequency for key repeat
Table 1. Register Address Map and Power-Up Condition (continued)
MAX7365
ADDRESS
CODE (hex)
0x3D
0x40
0x42
0x48
READ/
WRITE
R/W
R/W
R/W
R/W
POWER-UP
VALUE (hex)
0x00
0x00
0x00GPI Debounce Setting GPIO port inputs debounce time setting
0x00I
REGISTER FUNCTIONDESCRIPTION
GPO Pullup/Pulldown
Resistor Enable
GPIO Global
Configuration
2
C Timeout FlagI2C timeout since last POR
GPIO port open-drain output mode pullup/pulldown resistor
setting
2
GPI autowake enable, I
mode
C timeout interrupt enable, operating
Table 2. Key-Switch Mapping
PINCOL0COL1COL2COL3COL4COL5COL6
ROW0
ROW1
ROW2
ROW3
ROW4
ROW5
ROW6
ROW7
KEY 0KEY 8KEY 16KEY 24KEY 32KEY 40KEY 48
KEY 1KEY 9KEY 17KEY 25KEY 33KEY 41KEY 49
KEY 2KEY 10KEY 18KEY 26KEY 34KEY 42KEY 50
KEY 3KEY 11KEY 19KEY 27KEY 35KEY 43KEY 51
KEY 4KEY 12KEY 20KEY 28KEY 36KEY 44KEY 52
KEY 5KEY 13KEY 21KEY 29KEY 37KEY 45KEY 53
KEY 6KEY 14KEY 22KEY 30KEY 38KEY 46KEY 54
KEY 7KEY 15KEY 23KEY 31KEY 39KEY 47KEY 55
Keyscan Controller
Key inputs are scanned statically, not dynamically, to
ensure low-EMI operation. Since inputs only toggle in
response to switch changes, the key matrix can be
routed closer to sensitive circuit nodes.
The keyscan controller debounces and maintains a FIFO
buffer of keypress and release events (including autorepeated keypresses, if autorepeat is enabled). Table 2
shows the key-switch order. The user-programmable
key-switch debounce time and autosleep timer are
derived from the clock, which in turn is derived from the
internal oscillator. Time delay for autorepeat and keyswitch interrupt is based on the key-switch debounce
time. There is no limitation for the number of keys pressed
simultaneously as long as no ghost keys are generated.
If the application requires fewer keys to be scanned, the
unused key-switch ports can be configured as GPIs.
The Keys FIFO register contains the information pertain-
ing to the status of the keys FIFO, as well as the key
events that have been debounced (Table 6). Bits D[5:0]
denote which of the 56 keys have been debounced, and
the keys are numbered as shown in Table 2.
Special codes are key repeat (0x1E/0x3E), FIFO empty
(0x3F), and FIFO overflow (0x7F). Bit D7 indicates if there
is more data in the FIFO, except when a special key code
occurs. D6 indicates if a keypress or release event has
occurred.
Reading the keyscan FIFO clears the interrupt (INT),
depending on the setting of bit D5 in the configuration
register (0x01).
MAX7365
2
1MHz I
C-Interfaced 8 x 7
Key-Switch Controller with GPIO Ports
Configuration Register (0x01)
The Configuration register controls the I
out feature, enables the key-release indicator, enables
autowake, and determines how INT is deasserted. Write
to bit D7 to put the device into sleep or operating mode.
Autosleep and autowake, when enabled, also change the
status of D7 (Table 7).
Key-Switch Debounce Register (0x02)
The Key-Switch Debounce register sets the keypress and
key-release time for each debounce cycle. Bits D[3:0]
set the debounce time for keypresses, while bits D[7:4]
set the debounce time for key releases. Both debounce
times are configured in increments of 2ms starting at 1ms
and ending at 31ms (Table 8).
Key-Switch Interrupt Register (0x03)
The Key-Switch Interrupt register contains information
related to the settings of the interrupt request function,
as well as the status of the INT output. If bits D[7:0]
are set to 0x00, INT is disabled. There are two types of
interrupts, the FIFO-based interrupt and the time-based
interrupt. Set bits D[4:0] to assert interrupts at the end
of the selected number of debounce cycles following
a key event (Table 9). This number ranges from 1–31
debounce cycles. Setting bits D[7:5] sets the FIFObased interrupt when there are 2–14 key events stored
in the FIFO. Both interrupts can be configured simultaneously, and INT asserts depending on which condition is
met first. INT deasserts depending on the status of bit D5
in the Configuration register.
Key-Switch Autorepeat Register (0x05)
The device’s autorepeat feature notifies the host that at
least one key has been pressed for a continuous period.
The Autorepeat register enables or disables this feature,
sets the time delay after the last key event before the key
repeat code (0x7E) is entered into the FIFO, and sets
the frequency at which the key-repeat code is entered
into the FIFO thereafter. The autorepeat code continues
to be entered in the FIFO at the frequency set by bits
D[3:0] until another key event is recorded. The key being
pressed is not entered again into the FIFO. Following
the key-release event, if any keys are still pressed, the
device restarts the autorepeat sequence. Bit D7 specifies whether the autorepeat function is enabled with 0
denoting autorepeat disabled, and 1 denoting autorepeat enabled. Bits D[3:0] specify the autorepeat delay in
2
C bus time-
terms of debounce cycles, ranging from 8–128 debounce
cycles (Table 10). Bits D[6:4] specify the autorepeat rate
or frequency ranging from 4–32 debounce cycles.
Autosleep Register (0x06)
Autosleep puts the device in sleep mode to draw
minimal current. When enabled, the device enters sleep
mode if no keys are pressed for the autoshutdown time
(Table 11).
Key-Switch Array Size Register (0x30)
Bits D[7:4] set the row size of the key-switch array, and
bits D[3:0] set the column size of the key-switch array
(see Table 12). Set the bits to 0 if no key switches are
used. The key-switch array should be connected begin-
ning at ROW0 and COL0. If not used as a key-switch-
matrix pin, the pin can function as a GPI port, if enabled.
Key-Switch Autosleep Mode
In sleep mode, the device draws minimal current. Switch-
matrix current sources are turned off and become high.
When autosleep is enabled, key-switch inactivity for a
period longer than the autosleep time puts the part into
sleep mode (FIFO data is maintained). Writing a 1 to
D7 in the Configuration register (0x01) or a keypress
can take the device out of sleep mode. Bit D7 in the
Configuration register gives the sleep-mode status and
can be read at any time.
To place the device in sleep mode, clear bit D7 in the
Configuration register. The device is in sleep mode
after power-on reset (POR). In sleep mode, the keyscan
controller is disabled and the device draws minimal cur-
rent. No additional supply current is drawn if no keys are
pressed. All switch-matrix current sources are turned
off, and the row outputs (ROW7–ROW0) are low and the
column outputs (COL6–COL0) become high.
To take the device out of sleep mode and into operating
mode, cause a low-to-high transition in bit D7 by setting it
to a 1 in the Configuration register. The keyscan control-
ler FIFO buffers are cleared and key monitoring starts.
Note that rewriting the Configuration register bit D7 to a
1, when bit D7 is already a 1, does not clear the FIFOs.
The FIFOs are only cleared when the device is changing
state from shutdown to operating mode.
In sleep mode, the internal oscillator is disabled and the
Keypresses initiate autowake and the device goes into
operating mode. Keypresses that autowake the device
are not lost. When a key is pressed while the device is in
sleep mode, all analog circuitry, including switch-matrix
current sources, turn on in 2ms. The initial key needs to
be pressed for 2ms plus the debounce time to be stored
in the FIFO. Write a 0 to bit D1 in the Configuration register (0x01) to disable autowake.
FIFO Overflow
The FIFO overflow status occurs when the FIFO is full
(16 bytes) and additional events occur. If key release is
disabled, then the FIFO overflow status occurs when the
FIFO is full and not upon additional key events. When the
FIFO is overflowed, the first byte read from the FIFO buffer is the overflow byte (0x7F). The order of the original 16
bytes of event data is preserved, but further events could
be lost. When the FIFO is full, if the 18th key event is a key
release, then the FIFO overflow status is removed.
GPIO Ports
The device has five GPIO ports. The ports can be used
as logic inputs or logic outputs. Each GPIO port features
pullup/pulldown resistors when configured as open-drain
outputs. Also, the port is configurable with a high-side
open-drain output.
The COLs (GPI[6:0]) and ROWs (GPI[14:7]) are also
configurable as GPIs when not used for the key-switch
matrix. When the device is configured with C columns
and R rows for the key-switch matrix, assuming N is the
larger number between R and C, then COL[6:N+1] and
ROW[7:N+1] are configured as GPI ports. As an example, for a 4 x 4 matrix, COL6/COL5 and ROW7, ROW6,
and ROW5 are configured as GPIs, as shown in Table 3.
Unused GPIs and pins configured neither as key-switch
nor GPI should be connected to GND. Table 4, config-
ured as a 3 x 4 matrix, shows ROW4 and ROW3 con-
nected to GND, since they cannot be configured as GPI.
GPIO Direction Register (0x31)
This register configures the pins as an input or an output
port. GPIO Direction register bits D[4:0] correspond with
GPIO4–GPIO0 (Table 13). Set the corresponding bit to
0 to configure it as an input and 1 to configure it as an
output.
When the port is initially programmed as an input, there
is a delay of one debounce period prior to detecting
a transition on the input port. This is to prevent a false
interrupt from occurring when changing a port from an
output to an input.
GPO Output Mode Register (0x32)
This register configures the pin as an open-drain or