MAXIM MAX7365 Technical data

19-6036; Rev 0; 9/11
MAX7365
2
1MHz I
C-Interfaced 8 x 7
Key-Switch Controller with GPIO Ports

General Description

The MAX7365 is an I2C-interfaced peripheral that pro­vides microprocessors with management of up to 56 key switches.
Key codes generated for each keypress and release enable easier implementation of multiple key entries. Key inputs monitored statically, not dynamically, ensure low­EMI operation. The switches can be metallic or resistive (carbon) with up to 5kI of resistance.
The device features autosleep and autowake to further minimize the power consumption of the device. The autosleep feature puts the device in a low-power state (1FA typ) after a programmable sleep timeout period. The autowake feature configures the device to return to normal operating mode from sleep upon a keypress.
The key controller debounces and maintains a FIFO of key­press and release events (including autorepeat, if enabled). An interrupt (INT) output can be configured to alert key- presses either as they occur or at the maximum rate.
Unused key switches can be used as GPI. In addition, there are five additional general-purpose input/output (GPIO) ports. GPOs can be programmed as push-pull or open-drain to high- or low-side output drivers. When programmed as open drain, an optional on-chip 100kI pullup/pulldown resister can be enabled.
The device is available in a small (2mm x 2mm) 25-bump wafer-level package (WLP) for cell phones, pocket PCs, and other portable consumer electronic applications. The device operates over the -40NC to +85NC extended temperature range.

Benefits and Features

S Reduce Processor Load
Monitor Up to 56 Keys
FIFO Queues Up to 16 Debounced Key Events
Hardware Interrupt at the FIFO Level or at the
End-of-Definable Time Period
S Increased Battery Life
Autosleep and Autowake Minimize Current
Consumption
Less Than 1µA Sleep Current
S Save Board Space
Small (2mm x 2mm) and Low-Profile 25-Bump
WLP
S Flexible Design Requirements
1.62V to 3.6V Operation
Proprietary Ghost-Key Detection and Removal
Key Debounce Time User Configurable from
1ms to 31ms
Low-EMI Design Uses Static Matrix Monitoring
Five Additional GPIO Ports
All Key Switches Can Be Used as GPIs
1Mbps, 5.5V Tolerant, Two-Wire Serial Interface
Selectable Two-Wire, Serial-Bus Timeout

Typical Operating Circuit

+1.8V
V
MAX7365
INT
SDA SCL
DD
GND
GPIO[0:4]
ROW[0:7]
COL[0:6]
5
I/O
8
7
56 KEYS

Applications

Netbooks
Cell Phones
PDAs
Handheld Games
Portable Consumer Electronics
For related parts and recommended products to use with this part, refer to www.maxim-ic.com/MAX7365.related.
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MCU
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
MAX7365
2
1MHz I
C-Interfaced 8 x 7
Key-Switch Controller with GPIO Ports

ABSOLUTE MAXIMUM RATINGS

VDD to GND ............................................................ -0.3V to 4.0V
ROW7–ROW0, COL6–COL0,
GPIO4–GPIO0 to GND
SDA, SCL, INT to GND DC Current on ROW7–ROW0, COL6–COL0 to GND DC Current on GPIO4–GPIO0 to GND GND Current
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera­tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
......................................................................12mA
......................... -0.3V to (VDD + 0.3V)
.............................................. -0.3V to 6V
...........1mA
..............................12mA
PACKAGE THERMAL CHARACTERISTICS (Note 1)
Junction-to-Ambient Thermal Resistance (θ
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
) ..............52NC/W
JA

ELECTRICAL CHARACTERISTICS

(VDD = 1.62V to 3.6V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VDD = 3.3V, TA = +25NC.) (Notes 2, 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Operating Supply Voltage V
Operating Supply Current I
Sleep-Mode Supply Current I
Key-Switch Source Current I
Key-Switch Source Voltage V
Key-Switch Resistance R
Startup Time from Shutdown t
Keyscan Frequency f
Maximum Allowable Load Capacitance for Keyscan Function
GPIO SPECIFICATIONS
Input High Voltage GPIO_, ROW_, COL_, SDA, SCL
Input Low Voltage GPIO_, ROW_, COL_, SDA, SCL
Input Leakage Current GPIO_, ROW_, COL_, SDA, SCL
Output Logic Low Voltage INT, SDA
Output Low Voltage GPIO_
DD
DD
SL
KEY
KEY
KEY
START
KEY
V
IH
V
IL
I
IN
V
OL
N keys pressed; GPI static 34 + (25 x N)
All 56 key switches open 60 85
(Note 4) 5
N keys pressed simultaneously (Note 4) 500 pF
Input voltage = VDD or V
I
= 6mA 0.5 V
SINK
VDD = 1.8V and I
V
= 1.8V and I
DD
Continuous Power Dissipation (T
WLP (derate 19.2mW/NC above +70NC)....................1536mW
Operating Temperature Range Junction Temperature Storage Temperature Range Soldering Temperature (reflow)
GND
= 5mA 40 100
SINK
= 10mA 80 200
SINK
.....................................................+150NC
= +70NC)
A
.......................... -40NC to +85NC
............................ -65NC to +150NC
.................................... +260NC
1.62 3.3 3.6 V
0.8 5
20 36
0.42 0.55 V
2 2.4 ms
51 64 82 kHz
0.7 x V
DD
0.3 x V
DD
-2 -2
FA
FA
FA
FA
kI
V
V
FA
V
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MAX7365
2
1MHz I
C-Interfaced 8 x 7
Key-Switch Controller with GPIO Ports
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 1.62V to 3.6V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VDD = 3.3V, TA = +25NC.) (Notes 2, 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
-
V
Output High Voltage GPIO_
2
C TIMING SPECIFICATIONS
I
Input Capacitance SCL, SDA C
SCL Serial-Clock Frequency f
Bus Free Time Between a STOP and START Condition
Hold Time (Repeated) START Condition
Repeated START Condition Setup Time
STOP Condition Setup Time t
Data Hold Time t
Data Setup Time t
SCL Clock Low Period t
SCL Clock High Period t
Rise Time of Both SDA and SCL Signals, Receiving
Fall Time of Both SDA and SCL Signals, Receiving
Fall Time of SDA Signal, Transmitting
Pulse Width of Spike Suppressed t
Capacitive Load for Each Bus Line
Bus Timeout t
Note 2: All parameters are tested at TA = +25NC. Specifications over temperature are guaranteed by design. Note 3:
All digital inputs at VDD or V
Note 4: Guaranteed by design. Note 5: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) to bridge
the undefined region of SCL’s falling edge.
Note 6:
CB = total capacitance of one bus line in pF. tR and tF measured between 0.8V and 2.1V.
Note 7:
I
= 6mA. CB = total capacitance of one bus line in pF. tR and tF measured between 0.8V and 2.1V.
Note 8: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
SINK
V
SCL
t
BUF
t
HD, STA
t
SU, STA
SU, STO
HD, DAT
SU, DAT
LOW
HIGH
t
t
F, TX
C
TIMEOUT
GND
VDD = 1.8V and I
OH
V
= 1.8V and I
DD
(Notes 3, 4) 10 pF
IN
Bus timeout enabled 0.05 1000
Bus timeout disabled 0 1000
(Note 5) 0.9
(Notes 4, 6) 120 ns
R
t
(Notes 4, 6) 120 ns
F
(Notes 4, 7)
(Notes 4, 8) 50 ns
SP
(Notes 3, 4) 550 pF
B
.
SOURCE
SOURCE
= 5mA
= 10mA
DD
0.1
V
DD
0.2
0.5
0.26
0.26
0.26
0.5
0.26
20 +
0.1C
VDD -
0.05
-
VDD -
0.1
50 ns
B
20 40 ms
120 ns
V
kHz
Fs
Fs
Fs
Fs
Fs
Fs
Fs
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Key-Switch Controller with GPIO Ports
(VDD = +2.5V, TA = +25NC, unless otherwise noted.)
MAX7365
2
1MHz I

Typical Operating Characteristics

C-Interfaced 8 x 7
GPO OUTPUT LOW VOLTAGE
vs. SINK CURRENT (GPIO4–GPIO0)
40
VDD = 2.4V
35
LOW-SIDE OPEN-DRAIN MODE
30
25
20
15
10
GPO OUTPUT LOW VOLTAGE (mV)
5
0
TA = +85°C
TA = +25°C
TA = -40°C
0 5
SINK CURRENT (mA)
GPO OUTPUT LOW VOLTAGE
vs. SINK CURRENT (GPIO4–GPIO0)
40
VDD = 3.6V
35
LOW-SIDE OPEN-DRAIN MODE
30
25
20
15
10
GPO OUTPUT LOW VOLTAGE (mV)
5
0
TA = +85°C
TA = +25°C
TA = -40°C
0 5
SINK CURRENT (mA)
KEY-SWITCH SOURCE CURRENT
vs. SUPPLY VOLTAGE
28.0 COL0 = V
27.8
27.6
27.4
27.2
27.0
26.8
KEY-SWITCH SOURCE CURRENT (µA)
26.6
26.4
1.6 3.6
GND
TA = +25°C
TA = -40°C
TA = +85°C
SUPPLY VOLTAGE (V)
GPO OUTPUT LOW VOLTAGE
vs. SINK CURRENT (GPIO4–GPIO0)
40
VDD = 3.0V
35
MAX7365 toc01
431 2
LOW-SIDE OPEN-DRAIN MODE
30
25
20
15
10
GPO OUTPUT LOW VOLTAGE (mV)
5
0
TA = +85°C
TA = -40°C
0 5
SINK CURRENT (mA)
MAX7365 toc02
TA = +25°C
431 2
SUPPLY CURRENT vs. SUPPLY VOLTAGE
60
AUTOSLEEP = OFF GPI = STANDBY MODE
MAX7365 toc03
431 2
55
50
45
40
SUPPLY CURRENT (µA)
35
30
1.6 3.6
TA = +85°C
TA = +25°C
TA = -40°C
SUPPLY VOLTAGE (V)
3.12.62.1
MAX7365 toc04
SLEEP MODE SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.8
MAX7365 toc05
3.12.62.1
1.6
1.4
TA = +85°C
1.2
1.0
0.8
0.6
0.4
SLEEP MODE SUPPLY CURRENT (µA)
0.2
0
1.6 3.6
TA = +25°C
TA = -40°C
SUPPLY VOLTAGE (V)
3.12.62.1
MAX7365 toc06
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MAX7365
2
1MHz I
C-Interfaced 8 x 7
Key-Switch Controller with GPIO Ports

Pin Configuration

TOP VIEW
(BUMP SIDE DOWN)
MAX7365
1 2 3 4
+
A
ROW6
B
ROW4
C
ROW2
D
ROW1
E
ROW0
BUMP NAME FUNCTION
A1 ROW6 Row 6 Input from Key Matrix or General-Purpose Input
A2 ROW7 Row 7 Input from Key Matrix or General-Purpose Input
A3 COL2 Column 2 Input from Key Matrix or General-Purpose Input
A4 COL3 Column 3 Input from Key Matrix or General-Purpose Input
A5 COL4 Column 4 Input from Key Matrix or General-Purpose Input
B1 ROW4 Row 4 Input from Key Matrix or General-Purpose Input
B2 ROW5 Row 5 Input from Key Matrix or General-Purpose Input
B3 COL1 Column 1 Input from Key Matrix or General-Purpose Input
B4 COL6 Column 6 Input from Key Matrix or General-Purpose Input
B5 COL5 Column 5 Input from Key Matrix or General-Purpose Input
C1 ROW2 Row 2 Input from Key Matrix or General-Purpose Input
C2 ROW3 Row 3 Input from Key Matrix or General-Purpose Input
C3 COL0 Column 0 Input from Key Matrix or General-Purpose Input
C4 GPIO0 General-Purpose Input/Output Port 0
ROW7 COL2 COL3 COL4
ROW5 COL1 COL6 COL5
ROW3 COL0 GPIO0 GND
V
DD
INT SCL GPIO3 GPIO2
SDA GPIO4 GPIO1
WLP
5

Pin Description

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2
1MHz I
C-Interfaced 8 x 7
Key-Switch Controller with GPIO Ports
Pin Description (continued)
BUMP NAME FUNCTION
C5 GND Ground
D1 ROW1 Row 1 Input from Key Matrix or General-Purpose Input
D2 V
DD
D3 SDA I
D4 GPIO4 General-Purpose Input/Output Port 4
D5 GPIO1 General-Purpose Input/Output Port 1
E1 ROW0 Row 0 Input from Key Matrix or General-Purpose Input
E2
INT Active-Low Key-Switch Interrupt Output. INT is open drain and requires a pullup resistor.
E3 SCL I
E4 GPIO3 General-Purpose Input/Output Port 3
E5 GPIO2 General-Purpose Input/Output Port 2
Positive Supply Voltage. Bypass to GND with a 0.1FF capacitor as close as possible to the device.
2
C-Compatible Serial-Data Input/Output
2
C-Compatible Serial-Clock Input
MAX7365
INT
SDA
SCL
MAX7365
I2C
INTERFACE
BUS
TIMEOUT
OSCILLATOR
CONTROL
REGISTERS FIFO
POR
GPIO
LOGIC
KEY-
SCAN
LOGIC
COLUMN ENABLE
CURRENT DETECT
GPI ENABLE
GPI INPUT
ROW ENABLE
ROW DETECT
GPI ENABLE
GPI INPUT
CURRENT
SOURCE
COLUMN
DRIVES/
GPI
ROW
DRIVES/
GPI

Functional Diagram

GPIO0 GPIO1 GPIO2 GPIO3 GPIO4
COL0 COL1 COL2 COL3 COL4 COL5 COL6
ROW0 ROW1 ROW2 ROW3 ROW4 ROW5 ROW6 ROW7
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MAX7365
2
1MHz I
C-Interfaced 8 x 7
Key-Switch Controller with GPIO Ports

Detailed Description

the device cannot enter autosleep. The autowake feature
takes the device out of sleep mode following a keypress The MAX7365 is a microprocessor peripheral low-noise, key-switch controller that monitors up to 56 key switches with optional autorepeat. Key events are presented in a 16-byte FIFO. Key-switch functionality can be traded to provide up to 16 logic inputs. The device features an addi­tional five GPIOs. Outputs configured as open drain fea­ture an optional on-chip 100kI pullup/pulldown resistor.
The device features an automatic sleep mode and auto­matic wakeup that further reduce supply current con-
event. Autosleep and autowake can be disabled.
Interrupt requests can be configured to be issued on a
programmable number of FIFO entries or can be set to
a period of time to prevent overloading the microproces-
sor with too many interrupts. The key-switch status can
be checked at any time by reading the key-switch FIFO.
A 1-byte read access returns both the next key-event in
the FIFO, if there is one, and the FIFO status. Interrupts
are configurable per each input port with edge detection. sumption. The device can be configured to enter sleep mode after a programmable time following a key event. The FIFO content is maintained during sleep mode and can be read in sleep mode. When a key is held down,
On power-up, all control registers are set to power-up
values (Table 1), and the device is in sleep mode.
Table 1. Register Address Map and Power-Up Condition
ADDRESS
CODE (hex)
0x00 Read only 0x3F Keys FIFO Read FIFO keyscan data out
0x01
0x02
0x03
0x05
0x06
0x30
0x31
0x32
0x33 Read only 0xFF GPIs LSB Value GPI[7:0] (ROW0, COL[6:0]) port input values
0x34 Read only 0x7F GPIs MSB Value GPI[14:8] (ROW[7:1]) port input values
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
READ/ WRITE
R/W
R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W
R/W
R/W
R/W
POWER-UP
VALUE (hex)
0x0B Configuration
0xFF Key-Switch Debounce Key debounce time setting
0x00 Key-Switch Interrupt
0x00 Key-Switch Autorepeat Delay and frequency for key repeat
0x07 Autosleep Idle time to autosleep
0xF7 Key-Switch Array Size Keyscan switch array size
0x00 GPIO Direction Select GPIO port as input mode or output mode
0x00 GPO Output Mode GPO open-drain/push-pull output setting for GPIO port
0x1F GPIO Value Debounced input or output values for GPIO port
0x1F GPIs Interrupt Mask GPIO port interrupt mask for inputs
0xFF GPIs LSB Interrupt Mask GPI[7:0] (ROW0, COL[6:0]) port interrupt mask for inputs
0x7F GPIs MSB Interrupt Mask GPI[14:8] (ROW[7:1]) port interrupt mask for inputs
0x00 GPIs Interrupt Trigger GPIO edge-triggered interrupt setting
0x00
0x00
0x00
REGISTER FUNCTION
GPIs LSB Interrupt
Trigger Mode
GPIs MSB Interrupt
Trigger Mode
GPO High-Side
Open-Drain Enable
DESCRIPTION
Power-down, interrupt clearing mode, key-release enable, autowake, and I
Key-switch interrupt and INT frequency setting
GPI[7:0] (ROW0, COL[6:0]) edge-triggered interrupt setting
GPI[14:8] (ROW[7:1]) edge-triggered interrupt setting
GPIO port output mode high-side open-drain setting
2
C timeout enable

Register Description

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2
1MHz I
C-Interfaced 8 x 7
Key-Switch Controller with GPIO Ports
Table 1. Register Address Map and Power-Up Condition (continued)
MAX7365
ADDRESS
CODE (hex)
0x3D
0x40
0x42
0x48
READ/ WRITE
R/W
R/W
R/W R/W
POWER-UP
VALUE (hex)
0x00
0x00
0x00 GPI Debounce Setting GPIO port inputs debounce time setting
0x00 I
REGISTER FUNCTION DESCRIPTION
GPO Pullup/Pulldown
Resistor Enable
GPIO Global
Configuration
2
C Timeout Flag I2C timeout since last POR
GPIO port open-drain output mode pullup/pulldown resistor setting
2
GPI autowake enable, I mode
C timeout interrupt enable, operating

Table 2. Key-Switch Mapping

PIN COL0 COL1 COL2 COL3 COL4 COL5 COL6
ROW0
ROW1
ROW2
ROW3
ROW4
ROW5
ROW6
ROW7
KEY 0 KEY 8 KEY 16 KEY 24 KEY 32 KEY 40 KEY 48
KEY 1 KEY 9 KEY 17 KEY 25 KEY 33 KEY 41 KEY 49
KEY 2 KEY 10 KEY 18 KEY 26 KEY 34 KEY 42 KEY 50
KEY 3 KEY 11 KEY 19 KEY 27 KEY 35 KEY 43 KEY 51
KEY 4 KEY 12 KEY 20 KEY 28 KEY 36 KEY 44 KEY 52
KEY 5 KEY 13 KEY 21 KEY 29 KEY 37 KEY 45 KEY 53
KEY 6 KEY 14 KEY 22 KEY 30 KEY 38 KEY 46 KEY 54
KEY 7 KEY 15 KEY 23 KEY 31 KEY 39 KEY 47 KEY 55

Keyscan Controller

Key inputs are scanned statically, not dynamically, to ensure low-EMI operation. Since inputs only toggle in response to switch changes, the key matrix can be routed closer to sensitive circuit nodes.
The keyscan controller debounces and maintains a FIFO buffer of keypress and release events (including auto­repeated keypresses, if autorepeat is enabled). Table 2 shows the key-switch order. The user-programmable key-switch debounce time and autosleep timer are derived from the clock, which in turn is derived from the internal oscillator. Time delay for autorepeat and key­switch interrupt is based on the key-switch debounce time. There is no limitation for the number of keys pressed simultaneously as long as no ghost keys are generated. If the application requires fewer keys to be scanned, the unused key-switch ports can be configured as GPIs.
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Keys FIFO Register (0x00)

The Keys FIFO register contains the information pertain-
ing to the status of the keys FIFO, as well as the key
events that have been debounced (Table 6). Bits D[5:0]
denote which of the 56 keys have been debounced, and
the keys are numbered as shown in Table 2.
Special codes are key repeat (0x1E/0x3E), FIFO empty
(0x3F), and FIFO overflow (0x7F). Bit D7 indicates if there
is more data in the FIFO, except when a special key code
occurs. D6 indicates if a keypress or release event has
occurred.
Reading the keyscan FIFO clears the interrupt (INT),
depending on the setting of bit D5 in the configuration
register (0x01).
MAX7365
2
1MHz I
C-Interfaced 8 x 7
Key-Switch Controller with GPIO Ports

Configuration Register (0x01)

The Configuration register controls the I out feature, enables the key-release indicator, enables autowake, and determines how INT is deasserted. Write to bit D7 to put the device into sleep or operating mode. Autosleep and autowake, when enabled, also change the status of D7 (Table 7).

Key-Switch Debounce Register (0x02)

The Key-Switch Debounce register sets the keypress and key-release time for each debounce cycle. Bits D[3:0] set the debounce time for keypresses, while bits D[7:4] set the debounce time for key releases. Both debounce times are configured in increments of 2ms starting at 1ms and ending at 31ms (Table 8).

Key-Switch Interrupt Register (0x03)

The Key-Switch Interrupt register contains information related to the settings of the interrupt request function, as well as the status of the INT output. If bits D[7:0] are set to 0x00, INT is disabled. There are two types of interrupts, the FIFO-based interrupt and the time-based interrupt. Set bits D[4:0] to assert interrupts at the end of the selected number of debounce cycles following a key event (Table 9). This number ranges from 1–31 debounce cycles. Setting bits D[7:5] sets the FIFO­based interrupt when there are 2–14 key events stored in the FIFO. Both interrupts can be configured simultane­ously, and INT asserts depending on which condition is met first. INT deasserts depending on the status of bit D5 in the Configuration register.

Key-Switch Autorepeat Register (0x05)

The device’s autorepeat feature notifies the host that at least one key has been pressed for a continuous period. The Autorepeat register enables or disables this feature, sets the time delay after the last key event before the key repeat code (0x7E) is entered into the FIFO, and sets the frequency at which the key-repeat code is entered into the FIFO thereafter. The autorepeat code continues to be entered in the FIFO at the frequency set by bits D[3:0] until another key event is recorded. The key being pressed is not entered again into the FIFO. Following the key-release event, if any keys are still pressed, the device restarts the autorepeat sequence. Bit D7 speci­fies whether the autorepeat function is enabled with 0 denoting autorepeat disabled, and 1 denoting autore­peat enabled. Bits D[3:0] specify the autorepeat delay in
2
C bus time-
terms of debounce cycles, ranging from 8–128 debounce
cycles (Table 10). Bits D[6:4] specify the autorepeat rate
or frequency ranging from 4–32 debounce cycles.

Autosleep Register (0x06)

Autosleep puts the device in sleep mode to draw
minimal current. When enabled, the device enters sleep
mode if no keys are pressed for the autoshutdown time
(Table 11).

Key-Switch Array Size Register (0x30)

Bits D[7:4] set the row size of the key-switch array, and
bits D[3:0] set the column size of the key-switch array
(see Table 12). Set the bits to 0 if no key switches are
used. The key-switch array should be connected begin-
ning at ROW0 and COL0. If not used as a key-switch-
matrix pin, the pin can function as a GPI port, if enabled.

Key-Switch Autosleep Mode

In sleep mode, the device draws minimal current. Switch-
matrix current sources are turned off and become high.
When autosleep is enabled, key-switch inactivity for a
period longer than the autosleep time puts the part into
sleep mode (FIFO data is maintained). Writing a 1 to
D7 in the Configuration register (0x01) or a keypress
can take the device out of sleep mode. Bit D7 in the
Configuration register gives the sleep-mode status and
can be read at any time.
To place the device in sleep mode, clear bit D7 in the
Configuration register. The device is in sleep mode
after power-on reset (POR). In sleep mode, the keyscan
controller is disabled and the device draws minimal cur-
rent. No additional supply current is drawn if no keys are
pressed. All switch-matrix current sources are turned
off, and the row outputs (ROW7–ROW0) are low and the
column outputs (COL6–COL0) become high.
To take the device out of sleep mode and into operating
mode, cause a low-to-high transition in bit D7 by setting it
to a 1 in the Configuration register. The keyscan control-
ler FIFO buffers are cleared and key monitoring starts.
Note that rewriting the Configuration register bit D7 to a
1, when bit D7 is already a 1, does not clear the FIFOs.
The FIFOs are only cleared when the device is changing
state from shutdown to operating mode.
In sleep mode, the internal oscillator is disabled and the
2
C timeout features are disabled.
I
����������������������������������������������������������������� Maxim Integrated Products 9
MAX7365
2
1MHz I
C-Interfaced 8 x 7
Key-Switch Controller with GPIO Ports

Key-Switch Autowake

Keypresses initiate autowake and the device goes into operating mode. Keypresses that autowake the device are not lost. When a key is pressed while the device is in sleep mode, all analog circuitry, including switch-matrix current sources, turn on in 2ms. The initial key needs to be pressed for 2ms plus the debounce time to be stored in the FIFO. Write a 0 to bit D1 in the Configuration regis­ter (0x01) to disable autowake.

FIFO Overflow

The FIFO overflow status occurs when the FIFO is full (16 bytes) and additional events occur. If key release is disabled, then the FIFO overflow status occurs when the FIFO is full and not upon additional key events. When the FIFO is overflowed, the first byte read from the FIFO buf­fer is the overflow byte (0x7F). The order of the original 16 bytes of event data is preserved, but further events could be lost. When the FIFO is full, if the 18th key event is a key release, then the FIFO overflow status is removed.

GPIO Ports

The device has five GPIO ports. The ports can be used as logic inputs or logic outputs. Each GPIO port features pullup/pulldown resistors when configured as open-drain outputs. Also, the port is configurable with a high-side open-drain output.
The COLs (GPI[6:0]) and ROWs (GPI[14:7]) are also configurable as GPIs when not used for the key-switch matrix. When the device is configured with C columns and R rows for the key-switch matrix, assuming N is the larger number between R and C, then COL[6:N+1] and ROW[7:N+1] are configured as GPI ports. As an exam­ple, for a 4 x 4 matrix, COL6/COL5 and ROW7, ROW6,
and ROW5 are configured as GPIs, as shown in Table 3.
Unused GPIs and pins configured neither as key-switch
nor GPI should be connected to GND. Table 4, config-
ured as a 3 x 4 matrix, shows ROW4 and ROW3 con-
nected to GND, since they cannot be configured as GPI.

GPIO Direction Register (0x31)

This register configures the pins as an input or an output
port. GPIO Direction register bits D[4:0] correspond with
GPIO4–GPIO0 (Table 13). Set the corresponding bit to
0 to configure it as an input and 1 to configure it as an
output.
When the port is initially programmed as an input, there
is a delay of one debounce period prior to detecting
a transition on the input port. This is to prevent a false
interrupt from occurring when changing a port from an
output to an input.

GPO Output Mode Register (0x32)

This register configures the pin as an open-drain or
push-pull output. GPO Output Mode register bits D[4:0]
correspond with GPIO4–GPIO0 (Table 14). Set the cor-
responding bit to 0 to configure the output mode as open
drain and 1 to configure the output mode as push-pull.
GPIs LSB, MSB Port Value Registers
(0x33, 0x34) (Read Only)
The GPIs LSB and MSB Port Value registers contain the
debounced input data for all the GPIOs for GPI[7:0] and
GPI[14:8], respectively (Table 15 and Table 16). There is
one debounce period delay prior to detecting a transi-
tion on the input port. This prevents a false interrupt from
occurring when changing a port from an output to an
input. These registers report the state of all input ports,
regardless of any interrupt mask settings.
Table 3. 4 x 4 Keyboard Matrix Configuration with GPI
ROWS
0
1
2
3
4
5
6
7
0 1 2 3 4 5 6
4 x 4 keyboard
matrix
GND
GPI
GPI
GPI
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COLUMNS
GND GPI GPI
Table 4. 3 x 4 Keyboard Matrix
Configuration with GPI
ROWS
0
1
2
3
4
5
6
7
0 1 2 3 4 5 6
3 x 4 keyboard
matrix
GND
GND
GPI
GPI
GPI
COLUMNS
GND GPI GPI
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