The MAX7360 I2C-interfaced peripheral provides microprocessors with management of up to 64 key switches,
with an additional eight LED drivers/GPIOs that feature
constant-current, PWM intensity control, and rotary
switch control options.
The key-switch drivers interface with metallic or resistive switches with on-resistances up to 5kI. Key inputs
are monitored statically, not dynamically, to ensure
low-EMI operation. The MAX7360 features autosleep
and autowake modes to further minimize the power
consumption of the device. The autosleep feature puts
the device in a low-power state (1FA typ) after a sleep
timeout period. The autowake feature configures the
MAX7360 to return to normal operating mode from sleep
upon a keypress.
The key controller debounces and maintains a FIFO of
keypress and release events (including autorepeat, if
enabled). An interrupt (INTK) output can be configured
to alert keypresses, as they occur, or at maximum rate.
There are eight open-drain I/O ports, which can be used
to drive LEDs. The maximum constant-current level for
each open-drain port is 20mA. The intensity of the LED
on each open-drain port can be individually adjusted
through a 256-step PWM control. An input port pair
(PORT6, PORT7) can be configured to accept 2-bit gray
code inputs from a rotary switch. In addition, if not used
for key-switch control, up to six column pins can be used
as general-purpose open-drain outputs (GPOs) for LED
drive or logic control.
The MAX7360 is offered in a 40-pin (5mm x 5mm)
thin QFN package with an exposed pad, and a small
36-bump wafer level package (WLP) for cell phones,
pocket PCs, and other portable consumer electronic
applications. The MAX7360 operates over the -40NC to
+85NC extended temperature range.
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a single layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
= +70NC)
A
) (Note 1)
JC
JA
) (Note 1)
+ 0.3V)
CC
Operating Temperature Range .......................... -40NC to +85NC
Junction Temperature .....................................................+150NC
Storage Temperature Range ............................ -65NC to +150NC
ESD Protection
Human Body Model (R
All Pins .............................................................................Q2kV
IEC 61000-4-2 (R
Contact Discharge
ROW0–ROW7, COL0–COL7, PORT0–PORT7 to GND ....Q8kV
Air-Gap Discharge
ROW0–ROW7, COL0–COL7, PORT0–PORT7 to GND ..Q15kV
Lead Temperature (TQFN only, soldering, 10s) ..............+300NC
Soldering Temperature (reflow) .......................................+260NC
= 330I, CS = 150pF)
D
= 1.5kI, CS = 100pF)
D
ELECTRICAL CHARACTERISTICS
(VCC = +1.62V to +3.6V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25NC.) (Notes 2, 3)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Operating Supply VoltageV
External Supply Voltage
PORT0–PORT7
Operating Supply CurrentI
Sleep-Mode Supply CurrentI
Key-Switch Source CurrentI
Key-Switch Source VoltageV
Key-Switch ResistanceR
Startup Time from Shutdownt
Output Low Voltage
COL2–COL7
Oscillator Frequency (PWM
Clock)
Oscillator Frequency Variation
Key-Scan Frequencyf
V
Df
CC
PORT_
CC
SL
KEY
KEY
KEY
START
V
OL
f
OSC
OSC
KEY
All key switches open, oscillator running,
COL2–COL7 configured as key switches,
V
I2C-Interfaced Key-Switch Controller and LED
Driver/GPIOs with Integrated ESD Protection
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +1.62V to +3.6V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25NC.) (Notes 2, 3)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Data Hold Timet
Data Setup Timet
SCL Clock Low Periodt
SCL Clock High Periodt
MAX7360
Rise Time of Both SDA and SCL
Signals, Receiving
Fall Time of Both SDA and SCL
Signals, Receiving
Fall Time of SDA Signal,
Transmitting
Pulse Width of Spike Suppressedt
Capacitive Load for Each Bus
Line
Note 2: All parameters are tested at T
Note 3: All digital inputs at V
Note 4: Guaranteed by design.
Note 5: A master device must provide a hold time of at least 300ns for the SDA signal (referred to V
the undefined region of SCL’s falling edge.
Note 6: C
Note 7: I
Note 8: Input filters on the SDA, SCL, and AD0 inputs suppress noise spikes less than 50ns.
= total capacitance of one bus line in pF. tR and tF measured between +0.3VCC and +0.7VCC.
b
≤ 6mA.
SINK
CC
HD, DAT
SU, DAT
LOW
HIGH
t
R
t
F
t
F, TX
SP
C
= +25NC. Specifications over temperature are guaranteed by design.
I2C-Interfaced Key-Switch Controller and LED
Driver/GPIOs with Integrated ESD Protection
Pin Description
PIN
TQFNWLP
1A6ROW0Row Input from Key Matrix. Leave ROW0 unconnected or connect to GND if unused.
2B6ROW1Row Input from Key Matrix. Leave ROW1 unconnected or connect to GND if unused.
3C4ROW2Row Input from Key Matrix. Leave ROW2 unconnected or connect to GND if unused.
MAX7360
4C6ROW3Row Input from Key Matrix. Leave ROW3 unconnected or connect to GND if unused.
5, 15, 25, 35B4, C5, D2,
E4
6D6ROW4Row Input from Key Matrix. Leave ROW4 unconnected or connect to GND if unused.
7D5ROW5Row Input from Key Matrix. Leave ROW5 unconnected or connect to GND if unused.
8E6ROW6Row Input from Key Matrix. Leave ROW6 unconnected or connect to GND if unused.
9D4ROW7Row Input from Key Matrix. Leave ROW7 unconnected or connect to GND if unused.
10, 20, 27,
30, 40
11F6COL0Column Output to Key Matrix. Leave COL0 unconnected if unused.
12E5COL1Column Output to Key Matrix. Leave COL1 unconnected if unused.
13F5COL2
14F4COL3
16F3COL4
17E3COL5
18F2COL6
19F1COL7
21E2SDAI
22E1SCLI
23D3
C2N.C.No Connection. Not internally connected. Leave unconnected.
NAMEFUNCTION
GNDGround
Column Output to Key Matrix. Leave COL2 unconnected if unused. COL2 can be
configured as a GPO (see Table 9 in the Register Tables section).
Column Output to Key Matrix. Leave COL3 unconnected if unused. COL3 can be
configured as a GPO (see Table 9 in the Register Tables section).
Column Output to Key Matrix. Leave COL4 unconnected if unused. COL4 can be
configured as a GPO (see Table 9 in the Register Tables section).
Column Output to Key Matrix. Leave COL5 unconnected if unused. COL5 can be
configured as a GPO (see Table 9 in the Register Tables section).
Column Output to Key Matrix. Leave COL6 unconnected if unused. COL6 can be
configured as a GPO (see Table 9 in the Register Tables section).
Column Output to Key Matrix. Leave COL7 unconnected if unused. COL7 can be
configured as a GPO (see Table 9 in the Register Tables section).
2
C-Compatible, Serial-Data I/O
2
C-Compatible, Serial-Clock Input
INTK
Active-Low Key-Switch Interrupt Output. INTK is open drain and requires a pullup
resistor.
24D1
26C1V
28B1AD0Address Input. AD0 selects up to four device slave addresses (Table 3).
29A1I.C.Internally Connected. Connect to GND for normal operation.
31B2PORT0
32A2PORT1
33B3PORT2
34A3PORT3
36A4PORT4
37C3PORT5
38A5PORT6
39B5PORT7
——EP
NAMEFUNCTION
INTIActive-Low GPI Interrupt Output. INTI is open drain and requires a pullup resistor.
CC
Positive Supply Voltage. Bypass VCC to GND with a 0.1FF or higher ceramic capacitor.
GPIO Port. Open-drain I/O rated at +14V. PORT0 can be configured as a constantcurrent output.
GPIO Port. Open-drain I/O rated at +14V. PORT1 can be configured as a constantcurrent output.
GPIO Port. Open-drain I/O rated at +14V. PORT2 can be configured as a constantcurrent output.
GPIO Port. Open-drain I/O rated at +14V. PORT3 can be configured as a constantcurrent output.
GPIO Port. Open-drain I/O rated at +14V. PORT4 can be configured as a constantcurrent output.
GPIO Port. Open-drain I/O rated at +14V. PORT5 can be configured as a constantcurrent output.
GPIO Port. Open-drain I/O rated at +14V. PORT6 can be configured as a constantcurrent output, or a rotary switch input.
GPIO Port. Open-drain I/O rated at +14V. PORT7 can be configured as a constantcurrent output, or a rotary switch input.
Exposed Pad (TQFN only). EP is internally connected to GND. Connect EP to a ground
plane to increase thermal performance.
I2C-Interfaced Key-Switch Controller and LED
Driver/GPIOs with Integrated ESD Protection
Functional Block Diagram
PORT0
PORT1
PORT2
PORT3
PORT4
PORT5
PORT6
PORT7
COL0
COL1
COL2*
COL3*
COL4*
COL5*
COL6*
COL7*
ROW0
ROW1
ROW2
ROW3
ROW4
ROW5
ROW6
ROW7
MAX7360
INTI
INTK
SDA
SCL
AD0
MAX7360
I2C
INTERFACE
BUS
TIMEOUT
128kHz
OSCILLATOR
CONTROL
REGISTERS
FIFO
POR
PWM
GPIO
LOGIC
ROTARY
KEY
SCAN
LED ENABLE
GPIO ENABLE
GPIO INPUT
COLUMN ENABLE
GPO ENABLE
CURRENT DETECT
ROW ENABLE
PORT GPIO
AND
CONSTANT-
CURRENT
LED DRIVE
CURRENT
SOURCE
COLUMN
DRIVES
OPENDRAIN
ROW
DRIVES
*GPO
Detailed Description
The MAX7360 is a microprocessor peripheral low-noise
key-switch controller that monitors up to 64 key switches
with optional autorepeat, and key events that are presented in a 16-byte FIFO. The MAX7360 also features
eight open-drain GPIOs configured for digital I/O or
constant-current output for LED applications up to +14V.
The MAX7360 features an automatic sleep mode and
automatic wakeup that further reduce supply current
consumption. The MAX7360 can be configured to enter
sleep mode after a programmable time following a key
event. The FIFO content is maintained and can be read
in sleep mode. The MAX7360 does not enter autosleep
when a key is held down. The autowake feature takes
To prevent overloading the microprocessor with too
many interrupts, interrupt requests are issued on a
programmable number of FIFO entries, and/or after a
set period of time (Table 10). The key-switch status is
checked by reading the key-switch FIFO. A 1-byte read
access returns both the next key event in the FIFO (if
there is one) and the FIFO status. INTK functions as an
open-drain general-purpose output (GPO) capable of
driving an LED if key-switch interrupts are not required.
Up to six of the key-switch outputs function as opendrain GPOs capable of driving additional LEDs when
the application requires fewer keys to be scanned. For
each key-switch output used as a GPO, the number of
monitored key switches reduces by eight.
the MAX7360 out of sleep mode following a keypress
event. Enable/disable autosleep and autowake through
the configuration register (Table 8).
Key inputs are scanned statically, not dynamically,
to ensure low-EMI operation. As inputs only toggle in
response to switch changes, the key matrix can be
routed closer to sensitive circuit nodes.
The key-scan controller debounces and maintains a FIFO
of keypress and release events (including autorepeated
keypresses, if autorepeat is enabled). Table 2 shows the
key-switch order. The user-programmable key-switch
debounce time, and autosleep timer, is derived from the
64kHz clock, which in turn is derived from the 128kHz
oscillator. Time delay for autorepeat and key-switch
interrupt is based on the key-switch debounce time.
Keys FIFO Register (0x00)
The keys FIFO register contains the information pertaining
to the status of the keys FIFO, as well as the key events
that have been debounced (see Table 7 in the Register Tables section). Bits D0–D5 denote which of the 64 keys
have been debounced and the keys are numbered as in
Table 2.
D7 indicates if there is more data in the FIFO, except
when D5:D0 indicate key 63 or key 62. When D5:D0
indicate key 63 or key 62, the host should read one more
time to determine whether there is more data in the FIFO.
Use key 62 and key 63 for rarely used keys. D6 indicates
if it is a keypress or release event, except when D5:D0
indicate key 63 or key 62.
Reading the key-scan FIFO clears the interrupt INTK
depending on the setting of bit D5 in the configuration
register (0x01).
Configuration Register (0x01)
The configuration register controls the I
feature, enables key-release detection, enables autowake,
2
C bus timeout
and determines how INTK is deasserted. Write to bit D7
to put the MAX7360 into sleep mode or operating mode.
Autosleep and autowake, when enabled, also change the
status of D7 (see Table 8 in the Register Tables section).
Debounce Register (0x02)
The debounce register sets the time for each debounce
cycle, as well as setting whether the GPO ports are
enabled or disabled. Bits D0–D4 set the debounce time
in increments of 1ms starting at 9ms and ending at 40ms
(see Table 9 in the Register Tables section). Bits D5, D6,
and D7 set which of the GPO ports is enabled. Note the
GPO ports are enabled only in the combinations shown
in Table 9, from all disabled to all enabled.
Key-Switch Interrupt Register (0x03)
The interrupt register contains information related to the
settings of the interrupt request function, as well as the
status of the INTK output, which can also be configured
as a GPO. If bits D0–D7 are set to 0x00, the INTK output
is configured as a GPO that is controlled by bit D1 in the
port register. There are two types of interrupts, the FIFObased interrupt and time-based interrupt. Set bits D0–D4
to assert interrupts at the end of the selected number of
debounce cycles following a key event (see Table 10 in
the Register Tables section). This number ranges from
1–31 debounce cycles. Setting bits D7, D6, and D5 set
the FIFO-based interrupt when there are 2–14 key events
stored in the FIFO. Both interrupts can be configured
simultaneously and INTK asserts depending on which
condition is met first. INTK deasserts depending on the
status of bit D5 in the configuration register.
Ports Register (0x04)
The ports register sets the values of PORT2–PORT7 and
the INTK port, when configured, as open-drain GPOs.