General Description
The MAX7359 I2C interfaced peripheral provides microprocessors with management of up to 64 key switches.
Key codes are generated for each press and release of
a key for easier implementation of multiple key entries.
Key inputs are monitored statically, not dynamically, to
ensure low-EMI operation. The switches can be metallic
or resistive (carbon) with up to 5kΩ of resistance.
The MAX7359 features autosleep and autowake to further minimize the power consumption of the device.
The autosleep feature puts the device in a low-power
state (1µA typ) after a sleep timeout period. The
autowake feature configures the MAX7359 to return to
normal operating mode from sleep upon a key press.
The key controller debounces and maintains a FIFO of
key-press and release events (including autorepeat, if
enabled). An interrupt (INT) output can be configured to
alert key presses either as they occur, or at maximum rate.
Any of the column drivers (COL2/PORT2–COL7/PORT7)
or the INT, if not used, can function as a general-purpose output (GPO).
The MAX7359 is offered in small, 24-pin TQFN (3.5mm x
3.5mm) and 25-bump WLP (2.31mm x 2.31mm) packages for cell phones, pocket PCs, and other portable
consumer electronic applications. The MAX7359 operates over the -40°C to +85°C temperature range.
Applications
Cell Phones
PDAs
Handheld Games
Portable Consumer Electronics
Features
o Optional Key Release Detection on All Keys
o Monitor Up to 64 Keys
o +1.62V to +3.6V Operation
o Autosleep and Autowake to Minimize Current
Consumption
o Under 1µA Sleep Current
o FIFO Queues Up to 16 Debounced Key Events
o Key Debounce Time User Configurable from 9ms
to 40ms
o Low-EMI Design Uses Static Matrix Monitoring
o Hardware Interrupt at the FIFO Level or at the End
of Definable Time Period
o Up to Seven Open-Drain Logic Outputs Available
Capable of Driving LEDs
o 400kbps, 5.5V-Tolerant, 2-Wire Serial Interface
o Selectable 2-Wire, Serial-Bus Timeout
o Four I2C Address Choices
o Small, 24-Pin TQFN Package (3.5mm x 3.5mm) , or
25-Pin WLP Package (2.31mm x 2.31mm)
MAX7359
2-Wire Interfaced Low-EMI
Key Switch Controller/GPO
________________________________________________________________
Maxim Integrated Products
1
Ordering Information
19-0850; Rev 4; 6/10
EVALUATION KIT
AVAILABLE
+
Denotes a lead(Pb)-free/RoHS-compliant package.
*
EP = Exposed pad.
MAX7359
V
CC
COL_
GND
8
SCL
SDA
AD0
ROW_
8
SWITCH
ARRAY,
UP TO 64
SWITCHES
INPUT
+1.62V TO +3.6V
INT
Typical Application Circuits
Typical Application Circuits continued at end of data sheet.
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Pin Configurations
Pin Configurations continued at end of data sheet.
PART TEMP RANGE PIN-PACKAGE
MAX7359ETG+ -40°C to +85°C 24 TQFN-EP*
MAX7359EWA+ -40°C to +85°C 25 WLP
TOP VIEW
COL7/PORT7
ROW0
ROW1
*EP = EXPOSED PAD.
SCL
18 17 16 15 14 13
19
INT
20
V
CC
21
N.C.
22
23
24
+
123456
ROW2
(3.5mm x 3.5mm)
SDA
AD0
MAX7359
ROW3
COL3/PORT3
TQFN
GND
I.C.
EP*
ROW4
COL4/PORT4
COL0
ROW5
12
11
10
9
8
7
COL1
COL2/PORT2
COL5/PORT5
COL6/PORT6
ROW7
ROW6
MAX7359
2-Wire Interfaced Low-EMI
Key Switch Controller/GPO
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
(All voltages referenced to GND.)
V
CC
..........................................................................-0.3V to +4V
COL2/PORT2–COL7/PORT7 ....................................-0.3V to +4V
SDA, SCL, AD0, INT .................................................-0.3V to +6V
All Other Pins..............................................-0.3V to (V
CC
+ 0.3V)
DC Current on COL2/PORT2–COL7/PORT7 ......................25mA
GND Current .......................................................................80mA
Continuous Power Dissipation (T
A
= +70°C)
24-Pin TQFN (derate 15.4mW/°C above +70°C) ........1229mW
25-Bump WLP (derate 19.2mW/°C above +70°C)......1194mW
Junction-to-Case Thermal Resistance (
θ
J
C
) (Note 1)
24-Pin TQFN.................................................................5.4°C/W
25-Bump WLP ...............................................................17°C/W
Junction-to-Ambient Thermal Resistance (
θ
J
A
) (Note 1)
24-Pin TQFN...............................................................65.1°C/W
25-Bump WLP ...............................................................53°C/W
Operating Temperature Range (T
MIN
to T
MAX
) .....-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (TQFN only, soldering, 10s) ..............+300°C
Soldering Temperature (reflow) .......................................+260°C
ELECTRICAL CHARACTERISTICS
(VCC= +1.62V to +3.6V, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at VCC= +2.5V, TA= +25°C.) (Notes 2, 3)
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial
.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Operating Supply Voltage V
Operating Supply Current I
Sleep-Mode Supply Current I
POR 1.0 1.6 V
POR Hysteresis PORHYST VCC rising 42 mV
Key-Switch Source Current I
Key-Switch Source Voltage V
Key-Switch Resistance R
Startup Time from Shutdown t
Output Low Voltage
COL2/PORT2 to COL7/PORT7
INT Output V
Oscillator Frequency F
SERIAL-INTERFACE SPECIFICATIONS
Serial Bus Timeout t
Input High Voltage
SDA, SCL, AD0
Input Low Voltage
SDA, SCL, AD0
Output Low Voltage SDA V
Input Leakage Current VCC = 0V to +6V -1 +1 µA
CC
All key switches open, oscillator running,
CC
SL
KEY
KEY
KEY
START
V
OLPORTISINK
OLINTISINK
OSC
OUT
V
V
OLPORTISINK
COL2–COL7 configured as key switches
N keys pressed
Operating mode 0.42 0.55 V
(Note 4) 5 kΩ
With bus timeout enabled 10 40 ms
IH
IL
= 10mA 0.2 V
= 10mA 0.5 V
= 10mA 0.4 V
1.62 3.60 V
0.7 x
V
CC
20 x N)
25 60
(25 +
0.6 5 µA
20 35 µA
2 2.4 ms
64 kHz
0.3 x
V
CC
µA
V
V
MAX7359
2-Wire Interfaced Low-EMI
Key Switch Controller/GPO
_______________________________________________________________________________________ 3
I2C TIMING CHARACTERISTICS
(VCC= +1.62V to +3.6V, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at VCC= +2.5V, TA= +25°C.) (Notes 2, 3)
Note 2: All parameters are tested at TA= +25°C. Specifications over temperature are guaranteed by design.
Note 3: All digital inputs at V
CC
or GND.
Note 4: Guaranteed by design.
Note 5: C
b
= total capacitance of one bus line in pF. tRand tFmeasured between +0.3VCCand +0.7VCC.
Note 6: A master device must provide a hold time of at least 300ns for the SDA signal (referred to V
IL
of the SCL signal) to bridge
the undefined region of SCL’s falling edge.
Note 7: I
SINK
≤ 6mA.
Note 8: Input filters on the SDA, SCL, and AD0 inputs suppress noise spikes less than 50ns.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input Capacitance
(SCL, SDA, AD0)
SCL Serial-Clock Frequency f
Bus Free Time Between a STOP
and a START Condition
Hold Time (Repeated) START
Condition
Repeated START Condition
Setup Time
STOP Condition Setup Time t
Data Hold Time t
Data Setup Time t
SCL Clock Low Period t
SCL Clock High Period t
Rise Time of Both SDA and SCL
Signals, Receiving
Fall Time of Both SDA and SCL
Signals, Receiving
Fall Time of SDA Transmitting t
Pulse Width of Spike Suppressed t
C ap aci ti ve Load for E ach Bus Li ne C
t
t
C
SCL
t
BUF
HD, STA
SU, STA
SU, STO
HD, DAT
SU, DAT
LOW
HIGH
t
t
F, TX
SP
(Notes 4, 5) 10 pF
IN
Bus timeout disabled 0 400 kHz
1.3 µs
0.6 µs
0.6 µs
0.6 µs
(Note 6) 0.9 µs
100 ns
1.3 µs
0.7 µs
(Notes 4, 5)
R
(Notes 4, 5)
F
(Notes 4, 7)
(Notes 4, 8) 50 ns
(Note 4) 400 pF
b
0.1C
0.1C
0.1C
20 +
20 +
20 +
b
b
b
300 ns
300 ns
250 ns
MAX7359
2-Wire Interfaced Low-EMI
Key Switch Controller/GPO
4 _______________________________________________________________________________________
Typical Operating Characteristics
(VCC= +2.5V, TA= +25°C, unless otherwise noted.)
GPO PORT OUTPUT LOW VOLTAGE
vs. SINK CURRENT
300
VCC = +2.4V
250
200
(mV)
150
OL
V
100
50
0
010155202530
TA = +85°C
TA = +25°C
I
SINK
SUPPLY CURRENT vs. SUPPLY VOLTAGE
40
AUTOSLEEP = OFF
35
30
25
SUPPLY CURRENT (µA)
20
15
1.6 2.42.0 2.8 3.2 3.6
TA = +85°C
TA = +25°C
SUPPLY VOLTAGE (V)
(mA)
TA = -40°C
TA = -40°C
MAX7359 toc01
MAX7359 toc04
GPO PORT OUTPUT LOW VOLTAGE
vs. SINK CURRENT
300
VCC = +3.0V
250
200
(mV)
150
OL
V
100
50
0
010515202530
TA = +85°C
T
= +25°C
A
I
(mA)
SINK
TA = -40°C
KEY-SWITCH SOURCE CURRENT
vs. SUPPLY VOLTAGE
22.0
COL0 = GND
21.5
21.0
20.5
KEY-SWITCH SOURCE CURRENT (µA)
20.0
1.6 3.6
TA = +85°C
TA = -40°C
TA = +25°C
3.22.82.42.0
SUPPLY VOLTAGE (V)
MAX7359 toc02
MAX7359 toc05
GPO PORT OUTPUT LOW VOLTAGE
vs. SINK CURRENT
300
VCC = +3.6V
250
200
(mV)
150
OL
V
100
50
0
010515202530
TA = +85°C
TA = +25°C
I
(mA)
SINK
TA = -40°C
SLEEP MODE SUPPLY CURRENT
vs. SUPPLY VOLTAGE
2.0
1.5
1.0
0.5
SHUTDOWN SUPPLY CURRENT (µA)
0
1.6 2.62.1 3.1 3.6
SUPPLY VOLTAGE (V)
MAX7359 toc03
MAX7359 toc06
MAX7359
2-Wire Interfaced Low-EMI
Key Switch Controller/GPO
_______________________________________________________________________________________ 5
Functional Block Diagram
INT
SDA
SCL
MAX7359
INTERFACE
TIMEOUT
*GPO
I2C
BUS
64kHz
OSCILLATOR
CONTROL
REGISTERS
FIFO
POR
KEY SCAN
COLUMN ENABLE
GPO ENABLE
CURRENT DETECT
ROW ENABLE
COL0
COL1
CURRENT
SOURCE
COLUMN
DRIVES
OPENDRAIN
ROW
DRIVES
COL2*
COL3*
COL4*
COL5*
COL6*
COL7*
ROW0
ROW1
ROW2
ROW3
ROW4
ROW5
ROW6
ROW7
MAX7359
2-Wire Interfaced Low-EMI
Key Switch Controller/GPO
6 _______________________________________________________________________________________
Detailed Description
The MAX7359 is a microprocessor peripheral low-noise
key-switch controller that monitors up to 64 key switches
with optional autorepeat, and key events are presented
in a 16-byte FIFO. Key-switch functionality can be traded
to provide up to six open-drain logic outputs.
The MAX7359 features an automatic sleep mode and
automatic wakeup that further reduce supply current consumption. The MAX7359 can be configured to enter sleep
mode after a programmable time following a key event.
The FIFO content is maintained during sleep mode and
can be read in sleep mode. The MAX7359 does not enter
autosleep when a key is held down. The autowake feature
takes the MAX7359 out of sleep mode following a keypress event. Autosleep and autowake can be disabled.
Interrupt requests can be configured to be issued on a
programmable number of FIFO entries, or can be set
to a period of time to prevent overloading the microprocessor with too many interrupts. The key-switch status can be checked at any time by reading the
key-switch FIFO. A 1-byte read access returns both the
next key-event in the FIFO (if there is one) and the
FIFO status, so it is easy to operate the MAX7359 by
polling. If the INT pin is not required, it can be configured as an open-drain general-purpose output (GPO)
capable of driving an LED.
If the application requires fewer keys to be scanned, up
to six of the key-switch outputs can be configured as
open-drain GPOs capable of driving LEDs. For each
key-switch output used as a GPO, the number of key
switches that can be scanned is reduced by eight.
Pin Description
PIN
TQFN WLP
1A1
2A2
3A3
4B3
5A4
6A5
7B5
8B4
9C5
10 C4
11 D5
12 E5
13 E4
14 D4
15 D3
16 E3
17 E2
18 D2
19 E1
20 D1
21 C2, C3
22 C1
23 B2
24 B1
——
NAME FUNCTION
ROW2 Row Input from Key Matrix. Leave ROW2 unconnected or connect to GND if unused.
ROW3 Row Input from Key Matrix. Leave ROW3 unconnected or connect to GND if unused.
COL3/PORT3 Column Output to Key Matrix or GPO. Leave COL3/PORT3 unconnected if unused.
COL4/PORT4 Column Output to Key Matrix or GPO. Leave COL4/PORT4 unconnected if unused.
ROW4 Row Input from Key Matrix. Leave ROW4 unconnected or connect to GND if unused.
ROW5 Row Input from Key Matrix. Leave ROW5 unconnected or connect to GND if unused.
ROW6 Row Input from Key Matrix. Leave ROW6 unconnected or connect to GND if unused.
ROW7 Row Input from Key Matrix. Leave ROW7 unconnected or connect to GND if unused.
COL6/PORT6 Column Output to Key Matrix or GPO. Leave COL6/PORT6 unconnected if unused.
COL5/PORT5 Column Output to Key Matrix or GPO. Leave COL5/PORT5 unconnected if unused.
COL2/PORT2 Column Output to Key Matrix or GPO. Leave COL2/PORT2 unconnected if unused.
COL1 Column Output to Key Matrix. Leave COL1 unconnected if unused.
COL0 Column Output to Key Matrix. Leave COL0 unconnected if unused.
I.C. Internally Connected. Connect to GND for normal operation.
GND Ground
AD0 Adddress Input. ADO selects up to four device slave addresses (Table 10).
SDA I
SCL I
INT Active-Low Interrupt Output. INT is open drain.
V
CC
N.C. No Connection. Not internally connected.
COL7/PORT7 Column Output to Key Matrix or GPO. Leave COL7/PORT7 unconnected is unused.
ROW0 Row Input from Key Matrix. Leave ROW0 unconnected or connect to GND if unused.
ROW1 Row Input from Key Matrix. Leave ROW1 unconnected or connect to GND if unused.
EP
2
C-Compatible, Serial-Data I/O
2
C-Compatible, Serial-Clock Input
Positive Supply Voltage. Bypass VCC to GND with a 0.047µF or higher ceramic capacitor.
Exposed Pad (TQFN only). EP internally is connected to GND. Connect EP to a ground plane
to increase thermal performance.
MAX7359
2-Wire Interfaced Low-EMI
Key Switch Controller/GPO
_______________________________________________________________________________________ 7
Table 1. Key-Switch Mapping
Table 2. Register Address Map and Power-Up Condition
Key-Scan Controller
Key inputs are scanned statically, not dynamically, to
ensure low-EMI operation. As inputs only toggle in
response to switch changes, the key matrix can be
routed closer to sensitive circuit nodes.
The key controller debounces and maintains a FIFO of
key-press and release events (including autorepeated
key presses, if autorepeat is enabled). Table 1 shows
keys order.
_____________________Initial Power-Up
On power-up, all control registers are set to power-up
values and the MAX7359 is in sleep mode (Table 2).
Registers Description
Keys FIFO Register (0x00)
The keys FIFO register contains the information pertaining to the status of the keys FIFO, as well as the key
events that have been debounced (Table 3). Bits D0 to
D5 denote which of the 64 keys have been debounced
and the keys are numbered as in Table 1.
D7 indicates if there is more data in the FIFO except
when D5:D0 indicate key 63 or key 62. When D5:D0
indicate key 63 or key 62, the host should read one
more time to determine whether there is more data in
FIFO. It is better to use key 62 and key 63 for rarely
used keys. D6 indicates if it is a key-press or release
event except when D5:D0 indicate key 63 or key 62.
Reading the key-scan FIFO clears the interrupt INT
depending on the setting of bit D5 in the configuration
register (0x01).
Configuration Register (0x01)
The configuration register controls the I2C bus timeout
feature, enables key release detection, enables autowake,
and determines how INT should be deasserted. By writing
to bit D7, you can put the MAX7359 into sleep mode or
operating mode, however, autosleep and autowake,
when enabled, also change the status of this bit (Table 4).
PIN COL0 COL1 COL2/PORT2 COL3/PORT3 COL4/PORT4 COL5/PORT5 COL6/PORT6 COL7/PORT7
ROW0 KEY 0 KEY 8 KEY 16 KEY 24 KEY 32 KEY 40 KEY 48 KEY 56
ROW1 KEY 1 KEY 9 KEY 17 KEY 25 KEY 33 KEY 41 KEY 49 KEY 57
ROW2 KEY 2 KEY 10 KEY 18 KEY 26 KEY 34 KEY 42 KEY 50 KEY 58
ROW3 KEY 3 KEY 11 KEY 19 KEY 27 KEY 35 KEY 43 KEY 51 KEY 59
ROW4 KEY 4 KEY 12 KEY 20 KEY 28 KEY 36 KEY 44 KEY 52 KEY 60
ROW5 KEY 5 KEY 13 KEY 21 KEY 29 KEY 37 KEY 45 KEY 53 KEY 61
ROW6 KEY 6 KEY 14 KEY 22 KEY 30 KEY 38 KEY 46 KEY 54 KEY 62
ROW7 KEY 7 KEY 15 KEY 23 KEY 31 KEY 39 KEY 47 KEY 55 KEY 63
ADDRESS
CODE (hex)
0x00 Read only 0x3F Keys FIFO Read FIFO key scan data out
0x01 R/W 0x0A Configuration
0x02 R/W 0xFF Debounce Key debounce time setting and GPO enable
0x03 R/W 0x00 Interrupt INT frequency setting
0x04 R/W 0xFE Ports Ports 2–7 and INT GPO control
0x05 R/W 0x00 Key repeat Delay and frequency for key repeat
0x06 R/W 0x07 Sleep Idle time to autosleep
READ/WRITE
POWER-UP VALUE
(hex)
REGISTER
FUNCTION
DESCRIPTION
Power down, key release enable, autowakeup, and
2
I
C timeout enable
MAX7359
2-Wire Interfaced Low-EMI
Key Switch Controller/GPO
8 _______________________________________________________________________________________
Table 3. Keys FIFO Register Format (0x00)
SPECIAL FUNCTION
The key number indicated by D5:D0 is a key event. D7
is always for a key press of key 62 and key 63. When
D7 is 0, the key read is the last data in the FIFO. When
D7 is 1, there is more data in the FIFO. When D6 is 1,
key data read from FIFO is a key release. When D6 is
0, key data read from FIFO is a key press.
FIFO is empty. 0 0 111111
FIFO is overflow. Continue to read data in FIFO. 0 1 111111
Key 63 is pressed. Read one more time to determine
whether there is more data in FIFO.
Key 63 is released. Read one more time to determine
whether there is more data in FIFO.
Key repeat. Indicates the last data in FIFO. 0 0 111110
Key repeat. Indicates more data in FIFO. 0 1 111110
Key 62 is pressed. Read one more time to determine
whether there is more data in FIFO.
Key 62 is released. Read one more time to determine
whether there is more data in FIFO.
D7 D6 D5 D4 D3 D2 D1 D0
FIFO
empty
flag
10111111
11111111
10111110
11111110
Key
release
flag
KEYS FIFO REGISTER DATA
XXXXXX
MAX7359
2-Wire Interfaced Low-EMI
Key Switch Controller/GPO
_______________________________________________________________________________________ 9
Table 4. Configuration Register Format (0x01)
REGISTER BIT DESCRIPTION VALUE FUNCTION DEFAULT VALUE
2
C write, autosleep and
I
autowakeup all can
change this bit. This bit
can be read back by
2
I
C any time for current
status.
2
C should read FIFO until
0
0
0
0
1
0
1
0
D7 Sleep
D6 Reserved 0
D5 INTERRUPT
D4 Reserved 0
D3 Key release enable
D2 Reserved 0
D1 Wakeup
D0 Timeout enable
0 Sleep mode
1 Operating mode
This bit must always be 0. Improper operation
may result by writing a 1 to this location.
0 INT cleared when FIFO empty
INT cleared after host read.
1
0 Disable
1 Enable
0 Disable
1 Key press wakeup enable
0I
1I
In this mode, I
interrupt condition removed, or further INT
may be lost.
This bit must always be 0. Improper operation
may result by writing a 1 to this location.
This bit must always be 0. Improper operation
results by writing a 1 to this location.
2
C timeout enabled
2
C timeout disabled
MAX7359
2-Wire Interfaced Low-EMI
Key Switch Controller/GPO
10 ______________________________________________________________________________________
Debounce Register (0x02)
The debounce register sets the time for each debounce
cycle, as well as setting whether the GPO ports are
enabled or disabled. Bits D0 through D4 set the
debounce time in increments of 1ms starting at 9ms
and ending at 40ms (Table 5). Bits D5 through D7 set
which of the GPO ports is enabled. Note the GPO ports
can be enabled only in the combinations shown in
Table 5, from all disabled to all enabled.
Table 5. Debounce Register Format (0x02)
REGISTER DESCRIPTION
Debounce time is 9ms X X X 0 0 0 0 0
Debounce time is 10ms X X X 0 0 0 0 1
Debounce time is 11ms X X X 0 0 0 1 0
Debounce time is 12ms X X X 0 0 0 1 1
Debounce time is 37ms X X X 1 1 1 0 0
Debounce time is 38ms X X X 1 1 1 0 1
Debounce time is 39ms X X X 1 1 1 1 0
Debounce time is 40ms X X X 1 1 1 1 1
GPO ports disabled (full key-scan functionality) 0 0 0 X X X X X
GPO port 7 enabled 0 0 1 X X X X X
GPO ports 7 and 6 enabled 0 1 0 X X X X X
GPO ports 7, 6, and 5 enabled 0 1 1 X X X X X
GPO ports 7, 6, 5, and 4 enabled 1 0 0 X X X X X
GPO ports 7, 6, 5, 4, and 3 enabled 1 0 1 X X X X X
GPO ports 7, 6, 5, 4, 3, and 2 enabled 1 1 XXXXXX
Power-up default setting 1 1 111111
D7 D6 D5 D4 D3 D2 D1 D0
PORTS ENABLE DEBOUNCE TIME
.
.
.
REGISTER DATA
MAX7359
2-Wire Interfaced Low-EMI
Key Switch Controller/GPO
______________________________________________________________________________________ 11
Interrupt Register (0x03)
The interrupt register contains information related to the
settings of the interrupt request function, as well as the
status of the INT output, which can also be configured as
a GPO. If bits D0 through D7 are set to 0x00, the INT out-
put is configured as a GPO that is controlled by bit D1 in
the port register. There are two types of interrupts, the
FIFO based-interrupt and time-based interrupt. The timebased interrupt can be configured to assert INT after a
number of debounce cycles. By setting bits D0 through
D4 to an appropriate value, the interrupt can be asserted
at the end of the selected number of debounce cycles
following a key event (Table 6). This number ranges from
1 to 31 debounce cycles. The FIFO based interrupt can
be configured to assert INT when there are between 4
through 16 key events stored in the FIFO. Bits D7 through
D5 set the FIFO based interrupt. Both interrupts can be
configured simultaneously and INT asserts depending on
which condition is met first. INT deasserts depending on
the status of bit D5 in the configuration register.
Table 6. Interrupt Register Format (0x03)
Ports Register (0x04)
The ports register sets the values of ports 2 through 7 and
the INT port when configured as open-drain GPOs. The
settings in this register are ignored for ports not configured as GPOs, and a read from this register returns the
values stored in the register (Table 7).
Autorepeat Register (0x05)
The MAX7359 autorepeat feature notifies the host that at
least one key has been pressed for a continuous period
of time. The autorepeat register enables or disables this
feature, sets the time delay after the last key event before
the key repeat code (0x7E) is entered into the FIFO, and
sets the frequency at which the key repeat code is
entered into the FIFO thereafter. Bit D7 specifies whether
the autorepeat function is enabled with 0 denoting
autorepeat disabled and 1 denoting autorepeat enabled.
Bits D0 through D3 specify the autorepeat delay in terms
of debounce cycles ranging from eight debounce cycles
to 128 debounce cycles (Table 8). Bits D4 through D6
specify the autorepeat rate or frequency ranging from 4
to 32 debounce cycles.
When autorepeat is enabled, holding the key pressed
results in a key repeat event that is denoted by 0x7E. The
key being pressed does not show up again in the FIFO.
REGISTER DATA
REGISTER DESCRIPTION
INT used as GPO 00000000
FIFO based INT disabled 0 0 0 Not all zero
INT asserts every debounce cycles 00000001
INT asserts every 2 debounce cycles 00000010
INT asserts every 29 debounce 00011101
INT asserts every 30 debounce 00011110
INT asserts every 31 debounce 00011111
Time based INT disabled Not all zero 0 0 0 0 0
INT asserts when FIFO has 2 key events 0 0 1 0 0 0 0 0
INT asserts when FIFO has 4 key events 0 1 0 0 0 0 0 0
INT asserts when FIFO has 6 key events 0 1 1 0 0 0 0 0
INT asserts when FIFO has 16 key events 1 1 1 0 0 0 0 0
Both time base and FIFO based interrupts active Not all zero Not all zero
Power-up default setting 0 0 000000
D7 D6 D5 D4 D3 D2 D1 D0
FIFO-BASED INT TIME-BASED INT
.
.
.
.
.
.
MAX7359
2-Wire Interfaced Low-EMI
Key Switch Controller/GPO
12 ______________________________________________________________________________________
Table 7. Ports Register Format (0x04)
Table 8. Autorepeat Register Format (0x05)
REGISTER BIT DESCRIPTION VALUE FUNCTION DEFAULT VALUE
D7 PORT 7 Control
D6 PORT 6 Control
D5 PORT 5 Control
D4 PORT 4 Control
D3 PORT 3 Control
D2 PORT 2 Control
D1 INT Port Control
D0 Reserved 0 — 0
0 Clear port 7 low
1 Set port 7 high (high impedance)
0 Clear port 6 low
1 Set port 6 high (high impedance)
0 Clear port 5 low
1 Set port 5 high (high impedance)
0 Clear port 4 low
1 Set port 4 high (high impedance)
0 Clear port 3 low
1 Set port 3 high (high impedance)
0 Clear port 2 low
1 Set port 2 high (high impedance)
0 Clear port INT low
1 Set port INT high (high impedance)
1
1
1
1
1
1
1
REGISTER DATA
REGISTER DESCRIPTION
Autorepeat is disabled 0 X X X X X X X
Autorepeat is enabled 1 AUTOREPEAT RATE AUTOREPEAT DELAY
Key-switch autorepeat delay is 8 debounce cycles 1 X X X 0 0 0 0
Key-switch autorepeat delay is 16 debounce cycles 1 X X X 0 0 0 1
Key-switch autorepeat delay is 24 debounce cycles 1 X X X 0 0 1 0
Key-switch autorepeat delay is 112 debounce cycles 1 X X X 1 1 0 1
Key-switch autorepeat delay is 120 debounce cycles 1 X X X 1 1 1 0
Key-switch autorepeat delay is 128 debounce cycles 1 X X X 1 1 1 1
Key-switch autorepeat frequency is 4 debounce cycles 1 0 0 0 X X X X
Key-switch autorepeat frequency is 8 debounce cycles 1 0 0 1 X X X X
Key-switch autorepeat frequency is 12 debounce cycles 1 0 1 0 X X X X
Key switch autorepeat frequency is 32 debounce cycles 1 1 1 1 X X X X
Power-up default setting 0 0 0 0 0 0 0 0
D7 D6 D5 D4 D3 D2 D1 D0
ENABLE AUTOREPEAT RATE AUTOREPEAT DELAY
.
.
.
.
.
.
Only one autorepeat code is entered into the FIFO, regardless of the number of keys pressed. The autorepeat code
continues to be entered in the FIFO at the frequency set by
the bits D4–D1 until another key event is recorded.
Following the key-release event, if any keys are still
pressed, the MAX7359 restarts the autorepeat sequence.
Autosleep Register (0x06)
Autosleep puts the MAX7359 in sleep mode to draw minimal
current. When enabled, the MAX7359 enters sleep mode if
no keys are pressed for the autosleep time (Table 9).
Sleep Mode
In sleep mode, the MAX7359 draws minimal current.
Switch matrix current sources are turned off and pulled
up to VCC. Writing a 0 to D7 in the configuration register
(0x01) puts the device in sleep mode. Writing a 1 to D7
or a key press, when the part is programmed to
autowake, can take the MAX7359 out of sleep mode.
Bit D7 in the configuration register gives the sleep
mode status and can be read anytime. The FIFO data is
maintained while in sleep mode.
Autowake
Key presses initiate autowake and the MAX7359 goes
into operating mode. Key presses that autowake the
MAX7359 are not lost. When a key is pressed while the
MAX7359 is in sleep mode, all analog circuitry, including switch matrix current sources, turn on in 2ms. The
initial key needs to be pressed for 2ms plus the
debounce time to be stored in the FIFO. Autowakeup
can be disabled by writing a 0 to D1 in the configuration register (0x01).
Serial Interface
Figure 1 shows the 2-wire serial interface timing details.
Serial Addressing
The MAX7359 operates as a slave that sends and
receives data through an I2C-compatible 2-wire interface. The interface uses a serial-data line (SDA) and a
serial-clock line (SCL) to achieve bidirectional communication between master(s) and slave(s). A master (typically a microcontroller) initiates all data transfers to and
from the MAX7359 and generates the SCL clock that
synchronizes the data transfer.
The MAX7359’s SDA line operates as both an input and
an open-drain output. A pullup resistor, typically 4.7kΩ,
is required on SDA. The MAX7359’s SCL line operates
only as an input. A pullup resistor is required on SCL if
there are multiple masters on the 2-wire interface, or if
the master in a single-master system has an open-drain
SCL output.
Each transmission consists of a START (S) condition
(Figure 2) sent by a master, followed by the MAX7359 7bit slave address plus R/W bit, a register address byte, 1
or more data bytes, and finally a STOP (P) condition.
START and STOP Conditions
Both SCL and SDA remain high when the interface is not
busy. A master signals the beginning of a transmission
with a START condition by transitioning SDA from high to
low while SCL is high. When the master has finished
communicating with the slave, it issues a STOP condition
by transitioning SDA from low to high while SCL is high.
The bus is then free for another transmission.
Bit Transfer
One data bit is transferred during each clock pulse
(Figure 3). The data on SDA must remain stable while
SCL is high.
MAX7359
2-Wire Interfaced Low-EMI
Key Switch Controller/GPO
______________________________________________________________________________________ 13
Table 9. Autosleep Register Format (0x06)
REGISTER REGISTER DATA
AUTOSLEEP REGISTER
No Autosleep 0 0 0 0 0 0 0 0
Autosleep for (ms)
8192 0 0 0 0 0 0 0 1
4096 0 0 0 0 0 0 1 0
2048 0 0 0 0 0 0 1 1
1024 0 0 0 0 0 1 0 0
512 00000 1 01
256 00000 1 10
256 00000 1 11
Power-up default settings 0 0 0 0 0 1 1 1
D7 D6 D5 D4 D3 D2 D1 D0
RESERVED AUTOSHUTDOWN TIME
MAX7359
2-Wire Interfaced Low-EMI
Key Switch Controller/GPO
14 ______________________________________________________________________________________
Figure 1. 2-Wire Serial Interface Timing Details
Figure 2. START and STOP Conditions
Figure 3. Bit Transfer
SDA
t
SCL
t
HD, STA
t
LOW
SU, DAT
t
HD, DAT
t
HIGH
t
R
t
F
t
SU, STA
t
R
t
HD, STA
t
SU, STO
t
t
F
F, TX
t
BUF
START
CONDITION
SDA
SCL
S
START
CONDITION
SDA
REPEATED
START CONDITION
STOP
CONDITION
CONDITION
START
CONDITION
P
STOP
SCL
DATA LINE STABLE;
DATA VALID
CHANGE OF DATA
ALLOWED
MAX7359
2-Wire Interfaced Low-EMI
Key Switch Controller/GPO
______________________________________________________________________________________ 15
MAX7359
Acknowledge
The acknowledge bit is a clocked 9th bit (Figure 4),
which the recipient uses to handshake receipt of each
byte of data. Thus, each byte transferred effectively
requires 9 bits. The master generates the 9th clock
pulse, and the recipient pulls down SDA during the
acknowledge clock pulse, so the SDA line is stable low
during the high period of the clock pulse. When the
master is transmitting to the MAX7359, the MAX7359
generates the acknowledge bit because the MAX7359
is the recipient. When the MAX7359 is transmitting to
the master, the master generates the acknowledge bit
because the master is the recipient.
Slave Addresses
The MAX7359 has a 7-bit long slave address (Figure 5).
The bit following a 7-bit slave address is the R/W bit,
which is low for a write command and high for a read
command.
The first 4 bits (MSBs) of the MAX7359 slave address
are always 0111. Slave address bits A3, A2, and A1
correspond, by the matrix in Table 10, to the states of
the device address input AD0, and A0 corresponds to
the R/W bit. The AD0 input can be connected to any of
four signals: GND, VCC, SDA, or SCL, giving four possible slave address pairs, allowing up to four MAX7359
devices to share the bus. Because SDA and SCL are
dynamic signals, care must be taken to ensure that AD0
transitions no sooner than the signals on the SDA and
SCL pins.
The MAX7359 monitors the bus continuously, waiting for
a START condition followed by its slave address. When
the MAX7359 recognizes its slave address, it acknowledges and is then ready for continued communication.
Bus Timeout
The MAX7359 features a 20ms minimum bus timeout on
the 2-wire serial interface, largely to prevent the
MAX7359 from holding the SDA I/O low during a read
transaction if the SCL hangs for any reason before a serial transaction has been completed. Bus timeout operates
by causing the MAX7359 to internally terminate a serial
transaction, either read or write, if SCL low exceeds
20ms. After a bus timeout, the MAX7359 waits for a valid
START condition before responding to a consecutive
transmission. This feature can be enabled or disabled
under user control by writing to the configuration register
(Table 4).
Table 10. 2-Wire Interface Address Map
Figure 5. Slave Address
Figure 4. Acknowledge
PIN AD0
GND 0111000R/W
V
CC
SDA 0111100R/W
SCL 0111110R/W
A7 A6 A5 A4 A3 A2 A1 A0
0111010R/W
DEVICE ADDRESS
SCL
SDA
BY
TRANSMITTER
SDA
BY
RECEIVER
SDA
SCL
START
CONDITION
S
01 1A3A2A11
MSB
CLOCK PULSE FOR
ACKNOWLEDGE
1 2 8 9
ACKR/W
LSB
MAX7359
2-Wire Interfaced Low-EMI
Key Switch Controller/GPO
16 ______________________________________________________________________________________
Figure 6. Command Byte Received
Figure 7. Command and Single Data Byte Received
MAX7359
Message Format for Writing the
Key-Scan Controller
A write to the MAX7359 comprises the transmission of the
slave address with the R/W bit set to zero, followed by at
least 1 byte of information. The first byte of information is
the command byte. The command byte determines which
register of the MAX7359 is to be written by the next byte,
if received. If a STOP condition is detected after the command byte is received, the MAX7359 takes no further
action (Figure 6) beyond storing the command byte.
Any bytes received after the command byte are data
bytes. The first data byte goes into the internal register of
the MAX7359 selected by the command byte (Figure 7).
If multiple data bytes are transmitted before a STOP
condition is detected, these bytes are generally stored
in subsequent MAX7359 internal registers (Table 7)
because the command byte address generally autoincrements (Table 11).
Message Format for Reading the
Key-Scan Controller
The MAX7359 is read using the MAX7359’s internally
stored command byte as an address pointer, the same
way the stored command byte is used as an address
pointer for a write. The pointer generally autoincrements
after each data byte is read using the same rules as for
a write (Table 11). Thus, a read is initiated by first configuring the MAX7359’s command byte by performing a
write (Figure 6). The master can now read n consecutive bytes from the MAX7359, with the first data byte
being read from the register addressed by the initialized command byte. When performing read-after-write
verification, remember to reset the command byte’s
address because the stored command byte address is
generally autoincremented after the write (Figure 8,
Table 11).
Operation with Multiple Masters
If the MAX7359 is operated on a 2-wire interface with multiple masters, a master reading the MAX7359 should use
a repeated start between the write that sets the
MAX7359’s address pointer, and the read(s) that takes
the data from the location(s). This is because it is possible
for master 2 to take over the bus after master 1 has set up
the MAX7359’s address pointer but before master 1 has
read the data. If master 2 subsequently resets the
MAX7359’s address pointer, master 1’s read may be from
an unexpected location.
Table 11. Autoincrement Rules
COMMAND BYTE IS STORED ON RECEIPT OF
SAAP0SLAVE ADDRESS COMMAND BYTE
ACKNOWLEDGE FROM MAX7359
SAAAP0SLAVE ADDRESS COMMAND BYTE DATA BYTE
ACKNOWLEDGE CONDITION
ACKNOWLEDGE FROM MAX7359
R/W
ACKNOWLEDGE FROM MAX7359
D7 D6 D5 D4 D3 D2 D1 D0 D1 D0D3 D2D5 D4D7 D6
R/W
D7 D6 D5 D4 D3 D2 D1 D0
ACKNOWLEDGE FROM MAX7359
REGISTER
FUNCTION
Keys FIFO 0x00 0x00
Autoshutdown 0x06 0x00
All other 0x01 thru 0x05 Addr + 0x01
ADDRESS
CODE (hex)
ACKNOWLEDGE FROM MAX7359
1 BYTE
AUTOINCREMENT
COMMAND BYTE ADDRESS
AUTOINCREMENT
ADDRESS (hex)
MAX7359
2-Wire Interfaced Low-EMI
Key Switch Controller/GPO
______________________________________________________________________________________ 17
MAX7359
Command Address Autoincrementing
Address autoincrementing allows the MAX7359 to be
configured with fewer transmissions by minimizing the
number of times the command address needs to be
sent. The command address stored in the MAX7359
generally increments after each data byte is written or
read (Table 11). Autoincrement only works when doing
a multiburst read or write.
Applications Information
Ghost-Key Elimination
Ghost keys are a phenomenon inherent with key-switch
matrices. When three switches located at the corners of
a matrix rectangle are pressed simultaneously, the
switch that is located at the last corner of the rectangle
(the ghost key) also appears to be pressed. This occurs
because the potentials at the two sides of the ghost-key
switch are identical due to the other three connections—
the switch is electrically shorted by the combination of
the other three switches (Figure 9). Because the key
appears to be pressed electrically, it is impossible to
detect which of the four keys is the ghost key.
The MAX7359 employs a proprietary scheme that
detects any three-key combination that generates a
fourth ghost key, and does not report the third key that
causes a ghost key event. This means that although
ghost keys are never reported, many combinations of
three keys are effectively ignored when pressed at the
same time. Applications requiring three-key combinations (such as <Ctrl><Alt><Del>) must ensure that the
three keys are not wired in positions that define the vertices of a rectangle (Figure 10). There is no limit on the
number of keys that can be pressed simultaneously as
long as the keys do not generate ghost key events and
FIFO is not full.
Low-EMI Operation
The MAX7359 uses two techniques to minimize EMI
radiating from the key-switch wiring. First, the voltage
across the switch matrix never exceeds 0.55V when not
in sleep mode, irrespective of supply voltage V
CC
. This
reduces the voltage swing at any node when a switch is
pressed to 0.55V maximum. Second, the keys are not
dynamically scanned, which would cause the keyswitch wiring to continuously radiate interference.
Instead, the keys are monitored for current draw (only
occurs when pressed), and debounce circuitry only
operates when one or more keys are actually pressed.
Power-Supply Considerations
The MAX7359 operates with a +1.62V to +3.6V powersupply voltage. Bypass the power supply to GND with a
0.047µF or higher ceramic capacitor as close as possible to the device.
Switch On-Resistance
The MAX7359 is designed to be insensitive to resistance either in the key switches or the switch routing to
and from the appropriate COLx and ROWx up to 5kΩ.
These controllers are therefore compatible with lowcost membrane and conductive carbon switches.
Port Capacitance
There are discharge and charge processes at the switch
closing point during the key scan. To restrict the charging time at less than that allocated for each individual key
detection, the external capacitance at each port, including those from ESD-protection diode, should be less than
100pF for the application where two keys can be simultaneously pressed. The above applies only when two keys
pressed share the same column port. The allowed external capacitance can be relaxed to 160pF if simultaneously pressed keys do not share the same column port.
Software Reset
The sequence machine for key-detection control can
be reset using I2C commands implementable by the
software. During the normal operating mode, bit D7 of
the configuration register 0x01 is 1. To software reset
the MAX7359’s key-detection sequence machine, send
two I2C commands to set the D7 bit to 0 and then to 1,
respectively.
Figure 8. N Data Bytes Received
ACKNOWLEDGE FROM MAX7359
D7 D6 D5 D4 D3 D2 D1 D0 D1 D0D3 D2D5 D4D7 D6
ACKNOWLEDGE FROM MAX7359
SAAAP0SLAVE ADDRESS COMMAND BYTE DATA BYTE
ACKNOWLEDGE FROM MAX7359
R/W
N BYTES
AUTOINCREMENT
COMMAND BYTE ADDRESS
MAX7359
2-Wire Interfaced Low-EMI
Key Switch Controller/GPO
18 ______________________________________________________________________________________
Figure 9. Ghost-Key Phenomenon
Figure 10. Valid Three-Key Combinations
MAX7359
MAX7359
ROW0
ROW1
ROW2
ROW3
ROW4
ROW5
ROW6
ROW7
COL0
COL1
COL2/PORT2
COL3/PORT3
COL4/PORT4
COL5/PORT5
GND
V
CC
COL6/PORT6
COL7/PORT7
AD0
SCL
SDA
INT
SCL
SDA
INT
+1.8V
GND
µC
V
CC
+3.3V+3.3V
+5V
KEY 0
KEY 1
KEY 2
KEY 3
KEY 4
KEY 5
KEY 6
KEY 7
KEY 8
KEY 9
KEY 10
KEY 11
KEY 12
KEY 13
KEY 14
KEY 15
KEY 16
KEY 17
KEY 18
KEY 19
KEY 20
KEY 21
KEY 22
KEY 23
KEY 24
KEY 25
KEY 26
KEY 27
KEY 28
KEY 29
KEY 30
KEY 31
KEY 32
KEY 33
KEY 34
KEY 35
KEY 36
KEY 37
KEY 38
KEY 39
KEY 40
KEY 41
KEY 42
KEY 43
KEY 44
KEY 45
KEY 46
KEY 47
Typical Application Circuits (continued)
REGULAR KEY-PRESS
KEY-SWITCH MATRIX
EVENT
EXAMPLES OF VALID THREE-KEY COMBINATIONS
GHOST-KEY
EVENT
KEY-SWITCH MATRIX KEY-SWITCH MATRIX
MAX7359
2-Wire Interfaced Low-EMI
Key Switch Controller/GPO
______________________________________________________________________________________ 19
MAX7359
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages
.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
24 TQFN-EP T243A3+1
21-0188
25 WLP W252F2+1
21-0453
Pin Configurations (continued)
TOP VIEW
(BUMPS ON BOTTOM)
MAX7359
3
2
1
5
4
+
ROW2
A
ROW1
B
COL7/
PORT7
C
V
CC
D
INT
E
COL3/
ROW3
ROW0
N.C.
SCL
SDA
(2.31mm × 2.31mm)
PORT3
COL4/
PORT4
N.C.
GND
AD0
WLP
ROW4
ROW7
COL5/
PORT5
I.C.
COL0
ROW5
ROW6
COL6/
PORT6
COL2/
PORT2
COL1
MAX7359
2-Wire Interfaced Low-EMI
Key Switch Controller/GPO
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
0 7/07 Initial release —
1 4/08 Changed SCL device address for A1 in Table 10 15
2 2/09
3 8/09 Added WLP package information 1, 2, 3, 19
4 6/10
REVISION
DATE
DESCRIPTION
Added Port Capacitance and Software Reset sections to Applications
Information section
Updated Absolute Maximum Ratings and Notes 6 and 8 (now Notes 5 and 7)
in Electrical Characteristics
PAGES
CHANGED
17
2, 3
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