MAXIM MAX7356, MAX7357, MAX7358 User Manual

General Description

The MAX7356/MAX7357/MAX7358 8-channel I2C
switches/multiplexers expand the main I

2

C bus to any

combination of 8 extended I

2

C buses. They enable a
master on the main bus to isolate and communicate
with devices or groups of devices that may otherwise
have slave address conflicts. Any extended bus can be
connected or disconnected by control packets from the
main I2C bus writing to the main control register of
these I

2

C switches.

The MAX7357 and MAX7358 feature an enhanced
mode that includes a built-in timer used to monitor all
extended buses for lock-up conditions. If the clock or
data line of any of these buses is low for more than
25ms (typ), a lock condition is detected. An optional
interrupt can be generated through the bidirectional
RST/INT. The master can read the bus lock-up register
to find out which extended bus is locked up. The mas­ter can also enable the MAX7357 or the MAX7358 to
send a “flush-out” sequence on the faulty channel.
There is an optional preconnection check that
can be enabled to toggle the extended bus clock and
data line low then high to ensure the downstream bus is
not locked high prior to connecting it to the host bus.

The MAX7356/MAX7357/MAX7358 are transparent
to signals sent and received at each channel, allowing
multiple masters. Any device connected to an I

2

C
bus can transmit and receive signals; however, only the
master connected to the host side of the MAX7356/
MAX7357/MAX7358 should address the device.

The MAX7356/MAX7357/MAX7358 are available in 24-pin
TSSOP and TQFN packages and are specified over the
extended -40°C to +85°C temperature range.

Applications

Features

o Bus Lock-Up Detection and Isolation (MAX7357,

MAX7358)

o Host Notification on Detection of Lock-Up

(MAX7357, MAX7358)

o Maintain Fault Diagnostic Information (MAX7357,

MAX7358)

o Dual-Function RST/INT Provides Lock-Up

Notification and Hardware Reset (MAX7357,
MAX7358)

o RST Input Resets I

2

C Interface (MAX7358)

o 3 Address Control Inputs
o Low RONSwitches
o Logic-Level Translation
o Low 0.1µA (typ) Standby Current
o Support Hot Insertion
o 100kbps Standard-Mode or 400kbps Fast-Mode

I

2

C Interface

o Address Translation Allows Multiple Device with

Same ID

o 5.5V-Tolerant Inputs
o 2.3V to 5.5V Supply

MAX7356/MAX7357/MAX7358

1-to-8 I2C Bus Switches/Multiplexers with Bus

Lock-Up Detection, Isolation, and Notification

________________________________________________________________

Maxim Integrated Products

1

19-4207; Rev 0; 9/08

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT AVAILABLE

Ordering Information

+

Denotes a lead-free/RoHS-compliant package.

*

EP = Exposed pad.

**

Future product—contact factory for availability.

Typical Operating Circuit and Pin Configurations appear at end of data sheet.

Selector Guide

Servers
RAID
Base Stations
Control and Automation Devices
SFP Control Interface
Networking Equipment

PART TEMP RANGE PIN-PACKAGE

MAX7356ETG+ -40°C to +85°C 24 TQFN-EP*

MAX7356EUG+** -40°C to +85°C 24 TSSOP

MAX7357ETG+ -40°C to +85°C 24 TQFN-EP*

MAX7357EUG+** -40°C to +85°C 24 TSSOP

MAX7358ETG+ -40°C to +85°C 24 TQFN-EP*

MAX7358EUG+** -40°C to +85°C 24 TSSOP

PART

MAX7356 No No Basic mode RST only

MAX7357 Yes Yes, enhanced mode only Enhanced mode Yes

MAX7358 Yes Yes, enhanced mode only Basic mode Yes

ENHANCED

MODE

PRECONNECTION

WIGGLE TEST

POWER-UP

STATE

BIDIRECTIONAL

RST/INT

MAX7356/MAX7357/MAX7358

1-to-8 I2C Bus Switches/Multiplexers with Bus
Lock-Up Detection, Isolation, and Notification

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS (3.3V SUPPLY)

(VDD= +2.3V to +3.6V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VDD= +3.3V, TA= +25°C.) (Notes 2–5)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a 4-layer

board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial

.

(Voltages referenced to GND.)

VDD.................................................................. -0.3V to +6.0V

All Other Pins.....................................................-0.3V to +6.0V

Input Currents

V

DD

...............................................................................100mA

GND ..............................................................................100mA

All Input Pins.....................................................................±20mA

Output Current ....................................................................25mA

Continuous Power Dissipation (T

A

= +70°C)

24-Pin TSSOP (derate 13.9mW/°C above +70°C) .....1111mW

24-Pin TQFN (derate 27.8mW/°C above +70°C) .......2222mW

Junction-to-Case Thermal Resistance (

θ

JC

) (Note 1)

24-Pin TSSOP...............................................................13°C/W

24-Pin TQFN................................................................3.0°C/W

Junction-to-Ambient Thermal Resistance (

θ

JA

) (Note 1)

24-Pin TSSOP............................................................72.0°C/W

24-Pin TQFN..............................................................36.0°C/W

Operating Temperature Range ......................... -40°C to +85°C

Junction Temperature .................................................... +150°C

Storage Temperature Range ........................... -65°C to +150°C

Lead Temperature (soldering, 10s) ................................+300°C

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

POWER SUPPLY

Supply Voltage V

Supply Current I

Standby Current I

Power-On Reset Voltage V

Power-On Reset Hysteresis V

INPUT SCL, INPUT/OUTPUT SDA

Low-Level Input Voltage V

High-Level Input Voltage V

Low-Level Output Current I

Input Leakage Current ILH, I

Input Capacitance C

SELECT INPUTS A0 to A2, RST

Low-Level Input Voltage V

High-Level Input Voltage V

Input Leakage Current I

Input Capacitance C

DD

DD

STB

POR

HYST

IL

IH

OL

I

IL

IH

LI

I

VDD = 3.6V;
no load, f
400kHz

No load, VI = V

VDD rising 0.9 1.4 2.1 V

VOL = 0.4V 3

VOL = 0.6V 6

V

LI

and V

SCL

VI = GND 15 pF

A0 to A2, and RST at VDD or GND -1 +1 µA

VI = GND 2 pF

Basic mode 30 50

=

SCL

Enhanced mode
(MAX7357/MAX7358 only)

or GND, VDD = 3.6V 0.1 1 µA

DD

= VDD or GND -1 +1 µA

SDA

2.3 3.6 V

0.7 x
V

DD

0.7 x
V

DD

45 70

0.4 V

0.3 x
V

DD

0.3 x
V

DD

µA

V

V

mA

V

V

MAX7356/MAX7357/MAX7358

1-to-8 I2C Bus Switches/Multiplexers with Bus

Lock-Up Detection, Isolation, and Notification

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (3.3V SUPPLY) (continued)

(VDD= +2.3V to +3.6V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VDD= +3.3V, TA= +25°C.) (Notes 2–5)

ELECTRICAL CHARACTERISTICS (5V SUPPLY)

(VDD= +4.5V to +5.5V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VDD= +5V, TA= +25°C.) (Notes 2–5)

PASS GATE

Switch Resistance R

Switch Output Voltage V

Leakage Current I

Input/Output Capacitance C

OUTPUT RST/INT

Low-Level Output Current I

Leakage Current ILH, I

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

ON

SW

VDD = 3.0V to 3.6V, VO = 0.4V, IO = 15mA 5 11 30

VDD = 2.3V to 2.7V, VO = 0.4V, IO = 10mA 7 16 55

V

= VDD = 3.3V, I

SWin

V

= V

S Wi n

V

= VDD = 2.5V, I

SWin

V

= V

S Wi n

= 3.0V to 3.6V , I

D D

= 2.3V to 2.7V , I

D D

= -100µA 1.9

SWout

= - 100µA 1.6 2.8

S Wo ut

= -100µA 1.5

SWout

= - 100µA 1.1 2.0

S Wo ut

Basic mode -1 +1

OL

VI = VDD or GND

L

VI = GND 3 pF

IO

Enhanced mode
(MAX7357/MAX7358)

-2 +2

VOL = 0.4V (MAX7357/MAX7358) 3 mA

V

LI

= VDD or GND -1 +1 µA

RST/INT

µA

POWER SUPPLY

Supply Voltage V

Supply Current I

Standby Current I

Power-On Reset Voltage V

Power-On Reset Hysteresis V

INPUT SCL, INPUT/OUTPUT SDA

Low-Level Input Voltage V

High-Level Input Voltage V

Low-Level Output Current I

Input Leakage Current ILH, I

Input Capacitance C

SELECT INPUTS A0 TO A2, RST

Low-Level Input Voltage V

High-Level Input Voltage V

Input Leakage Current I

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DD

DD

STB

POR

HYST

IL

IH

OL

I

IL

IH

LI

VDD = 5V;
no load, f
400kHz

No load, VI = V

Basic mode 65 100

=

Enhanced mode

SCL

(MAX7357/MAX7358 only)

or GND, VDD = 5.5V 0.2 1 µA

DD

VDD rising 0.9 1.4 2.1 V

V

= 0.4V 3

OL

= 0.6V 6

V

OL

V

= V

LI

SCL

= VDD or GND -1 +1 µA

SDA

VI = GND 15 pF

A0 to A2, and RST pins at VDD or GND -1 +1 µA

4.5 5.5 V

90 130

0.4 V

0.3 x
V

DD

0.7 x
V

DD

0.3 x
V

DD

0.7 x
V

DD

µA

mA

Ω

V

V

V

V

V

MAX7356/MAX7357/MAX7358

1-to-8 I2C Bus Switches/Multiplexers with Bus
Lock-Up Detection, Isolation, and Notification

4 _______________________________________________________________________________________

TIMING CHARACTERISTICS (STANDARD-MODE) (Figures 1, 2, 3)

(VDD= 2.3V to 5.5V, TA= -40°C to +85°C, unless otherwise noted.) (Notes 2, 6)

ELECTRICAL CHARACTERISTICS (5V SUPPLY) (continued)

(VDD= +4.5V to +5.5V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VDD= +5V, TA= +25°C.) (Notes 2–5)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Input Capacitance C

PASS GATE

Switch Resistance R

Switch Output Voltage V

Leakage Current I

Input/Output Capacitance C

OUTPUT RST/INT

Low-Level Output Current I

Leakage Current ILH, I

ON

SW

OL

Propagation Delay from SDA to
SD_ or SCL to SC_

SCL Clock Frequency f

Bus Free Time Between a STOP
and START Condition

Hold Time (Repeated) START
Condition After this Period, the
First Clock Pulse is Generated

LOW Period of the SCL Clock t

HIGH Period of the SCL Clock t

Setup Time for a Repeated
START Condition

Setup Time for a STOP Condition t

Data Hold Time t

Data Setup Time t

Rise Time of Both SDA and SCL
Signals

Fall Time of Both SDA and SCL
Signals

Capacitive Load for Each Bus
Line

Pulse Width of Spikes that Must
be Suppressed by the Input Filter

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

t

PD

SCL

t

BUF

t

HD;STA

LOW

HIGH

t

SU;STA

SU;STO

HD;DAT

SU;DAT

t

t

C

t

SP

VI = GND 2 pF

I

VDD = 4.5V to 5.5V, VO = 0.4V, IO = 15mA 4 9 24 Ω

V

= VDD = 5.0V, I

SWin

V

= V

S Wi n

VI = VDD or GND

L

VI = GND 3 pF

IO

VOL = 0.4V (MAX7357/MAX7358) 3 mA

V

LI

RST/INT

(Note 7) 0.3 ns

(Note 8) 0 3.45 µs

R

F

b

= 4.5V to 5.5V , I

D D

= VDD or GND -1 +1 µA

= -100µA 3.6

SWout

= - 100µA 2.6 4.5

S Wo ut

MAX7356 -1 +1

Enhanced mode
(MAX7357/MAX7358)

-2 +2

0 100 kHz

4.7 µs

4.0 µs

4.7 µs

4.0 µs

4.7 µs

4.0 µs

250 ns

1000 ns

300 ns

400 pF

50 ns

V

µA

MAX7356/MAX7357/MAX7358

1-to-8 I2C Bus Switches/Multiplexers with Bus

Lock-Up Detection, Isolation, and Notification

_______________________________________________________________________________________ 5

TIMING CHARACTERISTICS (STANDARD-MODE) (Figures 1, 2, 3) (continued)

(VDD= 2.3V to 5.5V, TA= -40°C to +85°C, unless otherwise noted.) (Notes 2, 6)

TIMING CHARACTERISTICS (FAST-MODE) (Figures 1, 2, 3)

(VDD= 2.3V to 5.5V, TA= -40°C to +85°C, unless otherwise noted.) (Notes 2, 6)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Data Valid Time t

Data Valid Acknowledge t

Low-Level Reset Time t

Reset Time t

Recovery to Start t

VD;DAT

VD:ACK

REC;STA

WL(rst)

rst

(High to low) 1

(Low to high) 0.6

5ns

500 ns

0ns

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Propagation Delay from SDA to
SD_ or SCL to SC_

SCL Clock Frequency f

Bus Free Time Between a STOP
and START Condition
Hold Time (Repeated) START
Condition After this Period,
the Fi r st C l ock P ul se i s Gener ated

LOW Period of the SCL Clock t

HIGH Period of the SCL Clock t

Setup Time for a Repeated
START Condition

Setup Time for a STOP Condition t

Data Hold Time t

Data Setup Time t

Rise Time of Both SDA and SCL
Signals

Fall Time of Both SDA and SCL
Signals

Capacitive Load for Each Bus
Line

Pulse Width of Spikes that Must
be Suppressed by the Input Filter

Data Valid Time t

Data Valid Acknowledge t

Low-Level Reset Time t

Reset Time t

Recovery to START t

t

HD;STA

t

SU;STA

SU;STO

HD;DAT

SU;DAT

VD;DAT

VD;ACK

REC;STA

t

PD

SCL

t

BUF

LOW

HIGH

t

t

C

t

SP

WL(rst)

rst

(Note 7) 0.3 ns

0 400 kHz

1.3 µs

0.6 µs

1.3 µs

0.6 µs

0.6 µs

0.6 µs

(Note 8) 0 0.9 µs

100 ns

R

F

b

(High to low) 1

(Low to high) 0.6

20 +

0.1C

b

20 +

0.1C

b

5ns

500 ns

0ns

µs

1µs

300 ns

300 ns

400 pF

50 ns

µs

1µs

MAX7356/MAX7357/MAX7358

1-to-8 I2C Bus Switches/Multiplexers with Bus
Lock-Up Detection, Isolation, and Notification

6 _______________________________________________________________________________________

TIMING CHARACTERISTICS (FAST-MODE) (Figures 1, 2, 3) (continued)

(VDD= 2.3V to 5.5V, TA= -40°C to +85°C, unless otherwise noted.) (Notes 2, 6)

Note 2: All devices are 100% production tested at T

A

= +25°C. Specifications are over -40°C to +85°C and are guaranteed by

design.

Note 3: Subscript SW refers to all SC_ and SD_ pins.
Note 4: V

SWin

= Switch input voltage; I

SWout

= Current between SD_ and SDA or SC_ and SCL. See Figure 4.

Note 5: V

I

= V

SD_

or V

SC_

.

Note 6: All timing is measured using 20% and 80% levels, unless otherwise noted.
Note 7: Pass gate propagation delay is calculated from the 20Ω typical R

ON

and the 15pF load capacitance.

Note 8: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V

IH(min)

of the SCL signed)

to bridge the undefined region of the falling edge of SCL.

SDA

SCL

t

BUF

t

SU;STO

t

SP

t

HD;STA

t

SU;STA

t

F

t

HIGH

t

HD;DAT

t

R

t

LOW

t

HD;STA

SP

Sr

P

t

SU;DAT

Figure 1. 2-Wire Serial-Interface Timing Diagram

SCL

SDA

RESET

t

REC;STA

t

WL(rst)

t

rst

Figure 2. RST Timing Diagram

MAX7356/MAX7357/MAX7358

1-to-8 I2C Bus Switches/Multiplexers with Bus

Lock-Up Detection, Isolation, and Notification

_______________________________________________________________________________________ 7

Figure 3. I2C Bus Timing Diagram

Figure 4. Switch Output Voltage and Current

Typical Operating Characteristics

(VDD= +5V, TA= +25°C, unless otherwise noted.)

START

t

SU;STA

CONDITION

(S)

PROTOCOL

SCL

t

BUF

SDA

t

HD;STA

DEVICE

+

V

SWin

-

BIT 7
MSB

(A7)

t

LOWtHIGH

t

r

V

SW

I

SWout

t

VD;ACK

STOP

CONDITION

(P)

t

SU;STO

BIT 6

(A6)

1/f

SCL

t

f

t

SU;DAT

t

HD;DAT

BIT 0

(R/W)

ACKNOWLEDGE

t

VD;DAT

(A)

V

vs. SUPPLY VOLTAGE

SW

I

= 100µA

SWout

2.3 5.5
VDD (V)

4.73.93.1

MAX7356 toc01

(V)
V

5.5

5.0

4.5

4.0

3.5

3.0

SW

2.5

2.0

1.5

1.0

0.5

0

SUPPLY CURRENT vs. SUPPLY VOLTAGE

100

f

= 400kHz

SCL

80

ENHANCED MODE

60

(µA)

DD

I

40

20

0

2.3 5.5

BASIC MODE

VDD (V)

SUPPLY CURRENT vs. SCL FREQUENCY

100

MAX7356 toc02

80

60

(µA)

DD

I

4.73.93.1

ENHANCED MODE

40

f

(kHz)

SCL

BASIC MODE

300200100

20

0

0400

MAX7356 toc03