The MAX7320 2-wire serial-interfaced peripheral features eight push-pull outputs with selectable power-up
logic states.
The +5.5V tolerant RST input clears the serial interface,
terminating any I2C†communication to or from the
MAX7320.
The MAX7320 uses two address inputs with four-level
logic to allow 16 I2C slave addresses. The slave
address also determines the power-up state level for
the outputs in groups of four ports.
The MAX7320 supports hot insertion. The serial interface SDA, SCL, AD0, AD2, and RST remain high
impedance in power-down (V+ = 0V) with up to +6V
asserted on them.
The MAX7320 is one device in a family of pin-compatible
port expanders with a choice of input ports, open-drain
I/O ports, and push-pull output ports (see Table 1).
The MAX7320 is available in 16-pin QSOP and 16-pin
TQFN packages, and is specified over the automotive
temperature range (-40°C to +125°C).
Applications
Cell Phones/PDAs
Satellite Radios
Notebooks
Automotive
RAID
Servers
Features
♦ 400kHz, +5.5V-Tolerant I2C Serial Interface
♦ +1.71V to +5.5V Operating Voltage
♦ Eight Push-Pull Output Ports with Selectable
Power-Up Logic States
♦ RST Clears the Serial Interface, Terminating Any
Serial Transaction to or from the MAX7320
♦ AD0 and AD2 Inputs Select from 16 Slave
Addresses
♦ Low 0.6µA (typ) Standby Current
♦ -40°C to +125°C Temperature Range
Ordering Information
PART
MAX7320AEE+
MAX7320ATE+
+Denotes lead-free package.
TEMP
RANGE
-40°C to
+125°C
-40°C to
+125°C
PINPACKAGE
16 QSOP—E16-4
16 TQFN
3mm x 3mm
x 0.8mm
TOP
MARK
ADBT1633-4
PKG
CODE
MAX7320
Pin Configurations, Typical Application Circuit, and
Functional Diagram appear at end of data sheet.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
(All voltages referenced to GND.)
Supply Voltage V+....................................................-0.3V to +6V
SCL, SDA, AD0, AD2, RST .......................................-0.3V to +6V
O0–07...............................................................0.3V to V+ + 0.3V
00–07 Output Current .......................................................±25mA
(V+ = +1.71V to +5.5V, TA= -40°C to +125°C, unless otherwise noted. Typical values are at V+ = +3.3V, TA= +25°C.) (Note 1)
TIMING CHARACTERISTICS
(V+ = +1.71V to +5.5V, TA= -40°C to +125°C, unless otherwise noted. Typical values are at V+ = +3.3V, TA= +25°C.) (Note 1)
Note 1: All parameters tested at TA= +25°C. Specifications over temperature are guaranteed by design.
Note 2: Guaranteed by design.
Note 3: A master device must provide a hold time of at least 300ns for the SDA signal (referred to V
IL
of the SCL signal) to bridge
the undefined region of SCL’s falling edge.
Note 4: C
b
= total capacitance of one bus line in pF. tRand tFmeasured between 0.3 x V+ and 0.7 x V+, I
SINK
≤ 6mA.
Note 5: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Port Output Data Validt
PPV
CL ≤ 100pF4µs
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Serial Clock Frequencyf
Bus Free Time Between a STOP
and a START Condition
216 RSTReset Input, Active Low. Drive RST low to clear the 2-wire interface.
4–7, 9–12 2–5, 7–10O0–O7Output Ports. O0 to O7 are push-pull outputs.
86GNDGround
1311N.C.No Connection. Not internally connected.
1412SCLI2C-Compatible Serial Clock Input
1513SDAI2C-Compatible Serial Data I/O
1614V+Positive Supply Voltage. Bypass V+ to GND with a 0.047µF ceramic capacitor.
—EPEPExposed Pad. Connect exposed pad to GND.
NAMEFUNCTION
Address Inputs. Select device slave address with AD0 and AD2. Connect AD0 and AD2
to either GND, V+, SCL, or SDA to give four logic combinations (see Table 3).
Detailed Description
MAX7319–MAX7329 Family Comparison
The MAX7319–MAX7323 family consists of five pincompatible, eight-port expanders. Each version is optimized for different applications. The MAX7328 and
MAX7329 are second sources to the PCF8574 and
PCF8574A.
The MAX7324–MAX7327 family consists of four pincompatible, 16-port expanders that integrate the functions of the MAX7320 and one of either the MAX7319,
MAX7321, MAX7322, or MAX7323.
Functional Overview
The MAX7320 is a general-purpose port expander
operating from a +1.71V to +5.5V supply that provides
eight push-pull output ports. The MAX7320 is rated to
sink a total of 100mA and source a total of 50mA from
all eight combined outputs.
The MAX7320 is set to one of 16 I2C slave addresses
(0x50 to 0x5F) using address select inputs AD0 and AD2,
and is accessed over an I
2
C serial interface up to
400kHz. Note the MAX7320 offers a different range of I
2
C
slave addresses than the MAX7319, MAX7321,
MAX7322, and MAX7323 (these expanders use the
address range 0x60 to 0x6F).
Input-only versions:
Eight input ports with programmable latching
transition detection interrupt and selectable pullups.
Offers maximum versatility for automatic input
monitoring. An interrupt mask selects which inputs
cause an interrupt on transitions, and transition flags
identify which inputs have changed (even
momentarily) since the ports were last read.
Output-only versions:
Eight push-pull outputs with selectable power-up
default states.
Push-pull outputs offer faster rise time than opendrain outputs, and require no pullup resistors.
I/O versions:
Eight open-drain I/O ports with latching transition
detection interrupt and selectable pullups.
Open-drain outputs can level shift the logic-high
state to a higher or lower voltage than V+ using
external pullup resistors. Any port can be used as an
input by setting the open-drain output to logic-high.
Transition flags identify which inputs have changed
(even momentarily) since the ports were last read.
Four input-only, four output-only versions:
Four input ports with programmable latching
transition detection interrupt and selectable pullups.
Four push-pull outputs with selectable power-up
default levels.
Table 1. MAX7319–MAX7329 Family Comparison (continued)
Table 2. Read and Write Access to Eight-Port Expander Family
2
C
I
PART
MAX7323110xxxxUp to 4—Up to 44
SLAVE
ADDRESS
INPUTS
MAX7328
MAX7329
16-PORT EXPANDERS
MAX73248Yes—8Software equivalent to a MAX7320 plus a MAX7321.
MAX7325Up to 8—Up to 88Software equivalent to a MAX7320 plus a MAX7319.
MAX73264Yes—12Software equivalent to a MAX7320 plus a MAX7322.
MAX7327
0100xxx
0111xxx
101xxxx
and
110xxxx
Up to 8—Up to 8—
Up to 4—Up to 412Software equivalent to a MAX7320 plus a MAX7323.
INPUT
INTERRUPT
MASK
OPENDRAIN
OUTPUTS
PUSH-
PULL
OUTPUTS
APPLICATION
Four I/O, four output-only versions:
Four open-drain I/O ports with latching transition
detection interrupt and selectable pullups.
Four push-pull outputs with selectable power-up
default levels.
PCF8574-, PCF8574A-compatible versions:
Eight open-drain I/O ports with nonlatching transition
detection interrupt and pullups on all ports.
All ports power up as inputs (or logic-high outputs).
Any port can be used as an input by setting the
open-drain output to logic-high.
2
I
PART
MAX7319110xxxx8Yes——
MAX7320101xxxx———8
MAX7321110xxxxUp to 8—Up to 8—
MAX7322110xxxx4Yes—4
MAX7323110xxxxUp to 4—Up to 44<port outputs>
MAX73280100xxxUp to 8—Up to 8—
MAX73290111xxxUp to 8—Up to 8—
C SLAVE
ADDRESS
INPUTS
INTERRUPT
MASK
OPENDRAIN
OUTPUTS
PUSH-
PULL
OUTPUTS
2
C DATA WRITEI2C DATA READ
I
<I7–I0 interrupt
mask>
<O7–O0 port
outputs>
<P7–P0 port
outputs>
<O7, O6 outputs,
I5–I2 interrupt
mask, O1, O0
outputs>
<P7–P0 port
outputs>
<P7–P0 port
outputs>
<I7–I0 port inputs>
<I7–I0 transition flags>
<O7-O0 port inputs>
<P7–P0 port inputs>
<P7–P0 transition flags>
<O7, O6, I5–I2, O1, O0 port
inputs>
<0, 0, I5–I2 transition flags,
0, 0>
<O7, O6, P5–P2, O1, O0 port
inputs>
<0, 0, P5-P2 transition flags,
0, 0>
<P7–P0 port inputs>
<P7–P0 port inputs>
The RST input clears the serial interface in case of a
hung bus, terminating any serial transaction to or from
the MAX7320.
When the MAX7320 is read through the serial interface,
the actual logic states at the ports are read back.
Output port power-up logic states are selected by the
address select inputs AD0 and AD2. Ports default to
logic-high or logic-low on power-up in groups of four
(see Table 3).
RST
Input
The RST input voids any I2C transaction involving the
MAX7320 and forces the MAX7320 into the I2C STOP
condition. A reset does not change the contents of the
output register. RST is overvoltage tolerant to +5.5V.
Standby Mode
When the serial interface is idle, the MAX7320 automatically enters standby mode, drawing minimal supply
current.
Slave Address and Power-Up
Default Logic States
Address inputs AD0 and AD2 determine the MAX7320
slave address and set the power-up output logic states.
Power-up logic states are set in groups of four (see
Table 3). The MAX7320 uses a different range of slave
addresses (101xxxx) than the MAX7319, MAX7321,
MAX7322, and MAX7323 (110xxxx).
The MAX7320 slave address is determined on each I
2
C
transmission, regardless of whether the transmission is
actually addressing the MAX7320. The MAX7320 distinguishes whether address inputs AD0 and AD2 are connected to SDA or SCL instead of fixed logic levels V+
or GND during this transmission. This means that the
MAX7320 slave address can be configured dynamically in the application without cycling the device supply.
On initial power-up, the MAX7320 cannot decode the
address inputs AD0 and AD2 fully until the first I2C
transmission. AD0 and AD2 initially appear to be connected to V+ or GND. This is important because the
address selection determines the power-up logic levels
of the output ports. However, at power-up, the I2C SDA
and SCL bus interface lines are high impedance at the
pins of every device (master or slave) connected to the
bus, including the MAX7320. This is guaranteed as part
of the I2C specification. Therefore, address inputs AD0
and AD2 that are connected to SDA or SCL normally
appear at power-up to be connected to V+. The powerup output state selection logic uses AD0 to select the
power-up state for ports O3–O0, and uses AD2 to
select the power-up state for ports O7–O4. The rule is
that a logic-high, SDA, or SCL connection selects a
logic-high power-up state, and a logic-low selects a
logic-low power-up state for each set of four ports (see
Table 3). The output power-up logic level configuration
is correct for a standard I2C configuration, where SDA
or SCL appear to be connected to V+ by the external
I2C pullups.
There are circumstances where the assumption that
SDA = SCL = V+ on power-up is not true; for example,
in true hot-swap applications in which there is legitimate bus activity during power-up. Also, if SDA and
SCL are terminated with pullup resistors to a different
supply voltage than the MAX7320’s supply, and if that
pullup supply rises later than the MAX7320’s, then SDA
or SCL may appear at power-up to be connected to
GND. In such applications, use the four address combinations that are selected by connecting address inputs
AD0 and AD2 to GND or V+ (shown in bold in Table 3).
These selections are guaranteed to be correct at
power-up, independent of SDA and SCL behavior. If
one of the other 12 address combinations is used, be
aware that unexpected port power-up default states
may occur until the first I2C transmission (to any device,
not necessarily the MAX7320).
Port Outputs
Write one byte to the MAX7320 to set all output port
states simultaneously.
Serial Interface
Serial-Addressing
The MAX7320 operates as a slave that sends and
receives data through an I
2
C interface. The interface
uses a serial data line (SDA) and a serial clock line
(SCL) to achieve bidirectional communication between
master(s) and slave(s). A master initiates all data trans-
fers to and from the MAX7320, and generates the SCL
clock that synchronizes the data transfer (Figure 1).
SDA operates as both an input and an open-drain output.
A pullup resistor, 4.7kΩ (typ), is required on SDA. SCL
operates only as an input. A pullup resistor, 4.7kΩ (typ),
is required on SCL if there are multiple masters on the 2wire interface, or if the master in a single-master system
has an open-drain SCL output.
Each transmission consists of a START condition sent
by a master, followed by the MAX7320’s 7-bit slave
address plus R/W bit, one or more data bytes, and
finally a STOP condition (Figure 2).
START and STOP Conditions
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmission with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, the master
issues a STOP (P) condition by transitioning SDA from
low to high while SCL is high. The bus is then free for
another transmission (Figure 2).
Bit Transfer
One data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(Figure 3).
The acknowledge bit is a clocked 9th bit the recipient
uses to acknowledge receipt of each byte of data
(Figure 4). Each byte transferred effectively requires 9
bits. The master generates the ninth clock pulse, and
the recipient pulls down SDA during the acknowledge
clock pulse, such that the SDA line is stable low during
the high period of the clock pulse. When the master is
transmitting to the MAX7320, the device generates the
acknowledge bit because the MAX7320 is the recipient. When the MAX7320 is transmitting to the master,
the master generates the acknowledge bit because the
master is the recipient.
Slave Address
The MAX7320 has a 7-bit slave address (Figure 5). The
8th bit following the 7-bit slave address is the R/W bit. It is
low for a write command, and high for a read command.
The 1st (A6), 2nd (A5), and 3rd (A4) bits of the
MAX7320 slave address are always 1, 0, and 1.
Connect AD0 and AD2 to GND, V+
,
SDA, or SCL to
select the slave address bits A3, A2, A1, and A0. The
MAX7320 has 16 possible slave addresses (Table 3),
allowing up to 16 MAX7320 devices on an I
2
C bus.
Note the MAX7320 offers a different range of I2C slave
addresses from the MAX7319, MAX7321, MAX7322 and
MAX7323, for which 1st (A6), 2nd (A5), and 3rd (A4)
bits of the slave address are always 1, 1, and 0.
Accessing the MAX7320
A single-byte read from the MAX7320 returns the sta-
tus of the eight output ports, read back as inputs.
A 2-byte read repeatedly returns the status of the eight
output ports, read back as inputs.
A multibyte read (more than 2 bytes before the I
2
C
STOP bit) repeatedly returns the status of the eight output ports, read back as inputs.
A single-byte write to the MAX7320 sets the logic state
of all eight outputs.
A multibyte write to the MAX7320 repeatedly sets the
logic state of all eight outputs.
Reading from the MAX7320
A read from the MAX7320 starts with the master transmitting the MAX7320’s slave address with the R/W bit
set high. The MAX7320 acknowledges the slave
address, and samples the logic state of the output
ports during the acknowledge bit. The master can read
one or more bytes from the MAX7320 and then issue a
STOP condition (Figure 6). The MAX7320 transmits the
current port data, read back from the actual port outputs (not the port output latches) during the acknowledge. If a port is forced to a logic state other than its
programmed state, the read back reflects this. If driving
a capacitive load, readback port level verification algorithms may need to take the RC rise/fall time into
account.
Typically, the master reads one byte from the MAX7320,
then issues a STOP condition (Figure 6). However, the
master can read 2 or more bytes from the MAX7320,
then issue a STOP condition. In this case, the MAX7320
resamples the port outputs during each acknowledge
and transmits the new data each time.
Writing to the MAX7320
A write to the MAX7320 starts with the master transmitting the MAX7320’s slave address with the R/W bit set
low. The MAX7320 acknowledges the slave address
and samples the ports during the acknowledge bit. The
master can transmit one or more bytes of data. The
MAX7320 acknowledges each subsequent byte of data
and updates the output ports until the master issues a
STOP condition (Figure 7).
SDA, SCL, AD0, AD2, and RST are overvoltage protected to +6V independent of V+. This allows the MAX7320
to be operated from a lower supply voltage, such as
+3.3V, while the I2C interface is driven from a higher
logic level, such as +5V.
Each of the output ports, O0–O7, has a protection
diode to V+ and to GND (Figure 8). When a port output
is driven to a voltage higher than V+ or lower than
GND, the appropriate protection diode clamps the output to a diode drop above V+ or below GND. When the
MAX7320 is powered down (V+ = 0V), each output port
appears as a diode connected to GND (Figure 8).
Power-Supply Considerations
The MAX7320 operates with a supply voltage of +1.71V
to +5.5V over the -40°C to +125°C temperature range.
Bypass V+ to GND with a ceramic capacitor of at least
0.047µF as close to the device as possible. For the TQFN
version, additionally connect the exposed pad to GND.
The MAX7320 is subset pin compatible with the
MAX6965, MAX7315, and MAX7316. The pin differences are shown in Table 4. The MAX7320 is not software compatible with MAX6965, MAX7315, or
MAX7316. In many cases it is possible to design a PC
board to work with all these port expanders, providing
design flexibility.
Pin Configurations
Table 4. MAX7320, MAX6965, MAX7315,
and MAX7316 Pin Compatibility
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages
.)
MARKING
E/2
D/2
D
0.10 C0.08 C
E
AAAA
C
L
(NE - 1) X e
(ND - 1) X e
C
L
A
A2
A1
L
e
k
L
E2
C
L
e
PACKAGE OUTLINE
8, 12, 16L THIN QFN, 3x3x0.8mm
D2/2
D2
b
E2/2
0.10 M C A B
C
L
L
e
21-0136
12x16L QFN THIN.EPS
1
I
2
8L 3x3
PKG
REF.MIN.
MIN.
NOM. MAX.
0.70 0.75 0.80
A
b
0.25 0.30 0.35
D
2.90
3.00 3.10
E
2.90 3.00 3.10
e
0.65 BSC.
L
0.35
0.55 0.75
ND
NE
0
0.02
A1
A2
0.20 REF
0.25
k
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF T ERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO
JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED
WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.20 mm AND 0.25 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS .
9. DRAWING CONFORMS TO JEDEC MO220 REVISION C.
10. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY.
11. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY.
12. WARPAGE NOT TO EXCEED 0.10mm.
12L 3x3
NOM. MAX.NOM.
0.70
0.75
0.20
0.25
2.90
3.00
2.90
3.00
0.50 BSC.
0.45
8
2
2
-
0.55
12N
0.05
0.0230.05
0
0.20 REF
-
0.25
3
-
0.80
0.30
3.10
3.10
0.65
-
16L 3x3
MIN.MAX.
0.70
0.75
0.80
0.20
0.25
0.30
2.90
3.00
3.10
2.90
3.00
0.50 BSC.
0.30
0.40
16
4
040.02
0.20 REF
-
0.25
EXPOSED PAD VARIATIONS
PKG.
CODES
TQ833-11.250.25 0.700.35 x 45° WEEC1.250.700.25
-
T1233-1
T1233-3
T1233-4
T1633-20.95
T1633F-3
T1633FH-3 0.65 0.80 0.95
T1633-40.95
T1633-50.95
3.10
0.50
0.05
D2
MIN.
NOM.
0.95
1.10
1.10
0.95
1.10
0.65
0.80
1.10 1.25 0.95 1.10
1.10
MAX.
1.25
1.25
1.251.10
1.25
0.95
1.25
E2
NOM.
MIN.
MAX.
1.10
0.95
1.25
0.95 1.100.35 x 45°1.25WEED-10.95
1.100.95
1.10
1.25
0.95
0.80
0.95
0.65
0.95
0.65 0.80
1.25
1.10 1.25
0.95
PACKAGE OUTLINE
8, 12, 16L THIN QFN, 3x3x0.8mm
PIN ID
JEDEC
WEED-1
0.35 x 45°
WEED-11.25
0.35 x 45°
0.35 x 45°
WEED-2
0.225 x 45°
WEED-2
0.225 x 45°
WEED-2
0.35 x 45°
WEED-2
0.35 x 45° WEED-2
21-0136
2
I
2
MAX7320
I2C Port Expander with Eight Push-Pull Outputs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages
.)
QSOP.EPS
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