The MAX7314 I2C-compatible serial interfaced peripheral provides microprocessors with 16 I/O ports plus one
output-only port and one input-only port. Each I/O port
can be individually configured as either an open-drain
current-sinking output rated at 50mA and 5.5V, or a logic
input with transition detection. The output-only port can
be assigned as an interrupt output for transition detection. The outputs are capable of driving LEDs, or providing logic outputs with external resistive pullup up to 5.5V.
Eight-bit PWM current control is built in for all 17 output
ports. A 4-bit global control applies to all LED outputs
and provides coarse adjustment of current from fully off
to fully on with 14 intensity steps in between. Each output has an individual 4-bit control, which further divides
the globally set current into 16 more steps.
Alternatively, the current control can be configured as a
single 8-bit control that sets all outputs at once.
Each output has independent blink timing with two blink
phases. All LEDs can be individually set to be on or off
during either blink phase, or to ignore the blink control.
The blink period is controlled by a clock input (up to 1kHz)
on BLINK or by a register. The BLINK input can also be
used as a logic control to turn the LEDs on and off, or as a
general-purpose input.
The MAX7314 supports hot insertion. All port pins, the
INT output, SDA, SCL, RST, BLINK, and the slave
address input ADO remain high impedance in powerdown (V+ = 0V) with up to 6V asserted upon them.
The MAX7314 is controlled through a 2-wire serial interface, and uses four-level logic to allow four I
addresses from only one select pin.
2
♦ 400kbps, 2-Wire Serial Interface, 5.5V Tolerant
♦ 2V to 3.6V Operation
♦ Overall 8-Bit PWM LED Intensity Control
Global 16-Step Intensity Control
Individual 16-Step Intensity Controls
♦ 2-Phase LED Blinking
♦ 50mA Maximum Port Output Current
♦ Supports Hot Insertion
♦ Outputs are 5.5V-Rated Open Drain
♦ Inputs are Overvoltage Protected to 5.5V
♦ Transition Detection with Interrupt Output
♦ 1.2µA (typ), 3.6µA (max) Operating Current
♦ Small 4mm x 4mm, Thin QFN Package
♦ -40°C to +125°C Temperature Range
Ordering Information
PARTTEMP RANGE
MAX7314ATG-40°C to +125°C
MAX7314AEG-40°C to +125°C 24 QSOP—
PINPACKAGE
24 Thin QFN
4mm x 4mm
x 0.8mm
Typical Application Circuit
C
5V
Features
PKG
CODE
T2444-4
MAX7314
Applications
LCD Backlights
LED Status Indication
Relay Drivers
Keypad Backlights
RGB LED Drivers
System I/O Ports
Pin Configurations continued at end of data sheet.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage (with respect to GND)
V+ .............................................................................-0.3V to +4V
SCL, SDA, AD0, BLINK, RST, P0–P15 .....................-0.3V to +6V
INT/O16 ...................................................................-0.3V to +8V
DC Current on P0–P15, INT/O16 ........................................55mA
DC Current on SDA.............................................................10mA
Maximum GND Current ....................................................350mA
Continuous Power Dissipation (T
A
= +70°C)
24-Pin QSOP (derate 9.5mW/°C over +70°C)..............761mW
24-Pin QFN (derate 20.8mW/°C over +70°C) ............1666mW
Operating Temperature Range
(T
MIN
to T
MAX
) .............................................-40°C to +125°C
(Typical Operating Circuit, V+ = 2V to 3.6V, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at V+ = 3.3V, TA = +25°C.)
(Note 1)
Note 1: All parameters tested at TA= +25°C. Specifications over temperature are guaranteed by design.
Note 2: A master device must provide a hold time of at least 300ns for the SDA signal (referred to V
IL
of the SCL signal) to bridge
the undefined region of SCL’s falling edge.
Note 3: Guaranteed by design.
Note 4: C
b
= total capacitance of one bus line in pF. tRand tFmeasured between 0.3 x VDDand 0.7 x VDD.
Note 5: I
SINK
≤ 6mA. Cb= total capacitance of one bus line in pF. tRand tFmeasured between 0.3 x VDDand 0.7 x VDD.
Note 6: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
The MAX7314 is a general-purpose input/output (GPIO)
peripheral that provides 16 I/O ports, P0–P15, controlled through an I2C-compatible serial interface. A
17th output-only port, INT/O16, can be configured as
an interrupt output or as a general-purpose output port.
All output ports sink loads up to 50mA connected to
external supplies up to 5.5V, independent of the
MAX7314’s supply voltage. The MAX7314 is rated for a
ground current of 350mA, allowing all 17 outputs to sink
20mA at the same time. Figure 1 shows the output
structure of the MAX7314. The ports default to inputs on
power-up.
18-Port GPIO with LED Intensity Control,
Interrupt, and Hot-Insertion Protection
4–11, 13–201–8, 10–17P0–P15Input/Output Ports. P0–P15 are open-drain I/Os rated at 5.5V, 50mA.
129GNDGround. Do not sink more than 350mA into the GND pin.
2118BLINKInput Port Configurable as Blink Control or General-Purpose Input
2219SCLI2C-Compatible Serial Clock Input
2320SDAI2C-Compatible Serial Data I/O
2421V+
—PADExposed Pad Exposed Pad on Package Underside. Connect to GND.
DATA FROM
SHIFT REGISTER
DATA FROM
SHIFT REGISTER
WRITE
CONFIGURATION
PULSE
WRITE PULSE
NAMEFUNCTION
Output Port. Open-drain output rated at 7V, 50mA. Configurable as interrupt
output or general-purpose output.
Reset Input. Active low clears the 2-wire interface and puts the device in the
same condition as power-up reset.
Address Input. Sets device slave address. Connect to either GND, V+, SCL,
or SDA to give four logic combinations. See Table 1.
Positive Supply Voltage. Bypass V+ to GND with a 0.047µF ceramic
capacitor.
CONFIGURATION
REGISTER
D
Q
FF
C
Q
K
OUTPUT
PORT
REGISTER
D
FF
C
K
Q
Q
OUTPUT PORT
REGISTER DATA
I/O PIN
Q2
READ PULSE
INPUT PORT
REGISTER
D
Q
FF
C
Q
K
GND
INPUT PORT
REGISTER DATA
TO INT
Port Inputs and Transition Detection
Input ports registers reflect the incoming logic levels of
the port pins, regardless of whether the pin is defined
as an input or an output. Reading an input ports register latches the current-input logic level of the affected
eight ports. Transition detection allows all ports configured as inputs to be monitored for changes in their
logic status. The action of reading an input ports register samples the corresponding 8 port bits’ input condition. This sample is continuously compared with the
actual input conditions. A detected change in input
condition causes the INT/O16 interrupt output to go
low, if configured as an interrupt output. The interrupt is
cleared either automatically if the changed input
returns to its original state, or when the appropriate
input ports register is read.
The INT/O16 pin can be configured as either an interrupt output or as a 17th output port with the same static
or blink controls as the other 16 ports (Table 4).
Port Output Control and LED Blinking
The two blink phase 0 registers set the output logic levels of the 16 ports P0–P15 (Table 8). These registers
control the port outputs if the blink function is disabled.
A duplicate pair of registers, the blink phase 1 registers,
are also used if the blink function is enabled (Table 9).
In blink mode, the port outputs can be flipped between
using the blink phase 0 registers and the blink phase 1
registers using hardware control (the BLINK input)
and/or software control (the blink flip flag in the configuration register) (Table 4). The logic level of the BLINK
input can be read back through the blink status bit in
the configuration register (Table 4). The BLINK input,
therefore, can be used as a general-purpose logic input
(GPI port) if the blink function is not required.
PWM Intensity Control
The MAX7314 includes an internal oscillator, nominally
32kHz, to generate PWM timing for LED intensity control.
PWM intensity control can be enabled on an output-byoutput basis, allowing the MAX7314 to provide any mix
of PWM LED drives and glitch-free logic outputs (Table
10). PWM can be disabled entirely, in which case all output ports are static and the MAX7314 operating current
is lowest because the internal oscillator is turned off.
PWM intensity control uses a 4-bit master control and 4
bits of individual control per output (Tables 13, 14). The
4-bit master control provides 16 levels of overall intensity control, which applies to all PWM-enabled output
ports. The master control sets the maximum pulse
width from 1/15 to 15/15 of the PWM time period. The
individual settings comprise a 4-bit number, further
reducing the duty cycle to be from 1/16 to 15/16 of the
time window set by the master control.
For applications requiring the same PWM setting for all
output ports, a single global PWM control can be used
instead of all the individual controls to simplify the control software and provide 240 steps of intensity control
(Tables 10 and 13).
Standby Mode
When the serial interface is idle and the PWM intensity
control is unused, the MAX7314 automatically enters
standby mode. If the PWM intensity control is used, the
operating current is slightly higher because the internal
PWM oscillator is running. When the serial interface is
active, the operating current also increases because
the MAX7314, like all I2C slaves, has to monitor every
transmission.
The MAX7314 operates as a slave that sends and
receives data through an I
2
C-compatible 2-wire interface. The interface uses a serial data line (SDA) and a
serial clock line (SCL) to achieve bidirectional communication between master(s) and slave(s). A master (typically a microcontroller) initiates all data transfers to and
from the MAX7314 and generates the SCL clock that
synchronizes the data transfer (Figure 2).
The MAX7314 SDA line operates as both an input and
an open-drain output. A pullup resistor, typically 4.7kΩ,
is required on the SDA. The MAX7314 SCL line operates only as an input. A pullup resistor, typically 4.7kΩ,
is required on SCL if there are multiple masters on the
2-wire interface, or if the master in a single-master system has an open-drain SCL output.
Each transmission consists of a START condition
(Figure 3) sent by a master, followed by the MAX7314
7-bit slave address plus R/W bit, a register address
byte, one or more data bytes, and finally a STOP condition (Figure 3).
Start and Stop Conditions
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmission with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, it issues a
STOP (P) condition by transitioning SDA from low to
high while SCL is high. The bus is then free for another
transmission (Figure 3).
Bit Transfer
One data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(Figure 4).
Acknowledge
The acknowledge bit is a clocked 9th bit that the recipient uses to handshake receipt of each byte of data
(Figure 5). Thus, each byte transferred effectively
requires 9 bits. The master generates the 9th clock
pulse, and the recipient pulls down SDA during the
acknowledge clock pulse so the SDA line is stable low
during the high period of the clock pulse. When the
master is transmitting to the MAX7314, the device generates the acknowledge bit because the MAX7314 is
the recipient. When the MAX7314 is transmitting to the
master, the master generates the acknowledge bit
because the master is the recipient.
Slave Address
The MAX7314 has a 7-bit long slave address (Figure 6).
The eighth bit following the 7-bit slave address is the
R/W bit. The R/W bit is low for a write command, high
for a read command.
18-Port GPIO with LED Intensity Control,
Interrupt, and Hot-Insertion Protection