The MAX7304 consists of 16 port GPIOs, with 12 pushpull GPIOs and four open-drain GPIOs configurable as
PWM-controlled LED drivers. The device supports a
1.62V to 3.6V separate power supply for level translation.
An address-select input (AD0) allows up to four unique
slave addresses for the device.
Each GPIO can be programmed to one of the two
externally applied logic voltage levels. PORT15–PORT12
can also be configured as LED drivers that feature
constant-current sinks and PWM intensity control with the
internal oscillator. The maximum constant-current level for
each open-drain LED port is 20mA. The intensity of the
LED on each open-drain port can be individually adjusted
through a 256-step PWM control. The port also features
LED fading.
The same index rows and columns in the device can be
used as a direct logic-level translator.
The device is offered in a 24-pin (3.5mm x 3.5mm) TQFN
package with an exposed pad, and a small 25-bump
(2.159mm x 2.159mm) wafer-level package (WLP) for
cell phones, pocket PCs, and other portable consumer
electronic applications.
The device operates over the -40NC to +85NC extended
temperature range.
Applications
Cell Phones
Notebooks
PDAs
Handheld Games
Portable Consumer Electronics
Features
SFour LED Driver Pins on PORT15–PORT12
SIntegrated High-ESD Protection
±8kV IEC 61000-4-2 Contact Discharge
±15kV IEC 61000-4-2 Air-Gap Discharge
S5V Tolerant, Open-Drain I/O Ports Capable of
Constant-Current LED Drive
S256-Step PWM Individual LED Intensity-Control
Accuracy
SIndividual LED Blink Rates and Common LED
Fade-In /Out Rates from 256ms to 4096ms
SUser-Configurable Debounce Time (1ms to 32ms)
SConfigurable Edge-Triggered Port Interrupt (INT)
S1.62V to 3.6V Operating Supply Voltage
SIndividually Programmable GPIOs to Two Logic
Levels
S8-Channel Individual Programmable Level
Translators
SSupports Hot Insertion
S400kbps, 5.5V Tolerant I2C Serial Interface with
Selectable Bus Timeout
Ordering Information appears at end of data sheet.
For related parts and recommended products to use with this part,
refer to www.maxim-ic.com/MAX7304.related.
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX7304
I2C-Interfaced 16-Port,
Level-Translating GPIO and LED Driver
with High Level of Integrated ESD Protection
ABSOLUTE MAXIMUM RATINGS
V
CC, VLA
PORT11–PORT0 to GND .......................... -0.3V to (VCC + 0.3V)
PORT15–PORT12 to GND ....................................... -0.3V to +6V
SDA, SCL, AD0, INT to GND ..................................-0.3V to +6V
VLA to VCC ...........................................................-0.3V to +2.3V
DC Current on PORT15–PORT12 to GND .........................25mA
DC Current on PORT11–PORT0 to GND .............................7mA
VCC, VLA, GND Current .....................................................80mA
DC Current VCC, VLA to PORT11–PORT0 ...........................5mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
TQFN
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
to GND ....................................................-0.3V to +4V
(VCC = 1.62V to 3.6V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = 3.3V, TA = +25NC.) (Notes 2, 3)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Pulse Width of Spike Suppressedt
Capacitive Load for Each Bus LineC
Bus Timeoutt
SP
B
TIMEOUT
ESD PROTECTION
PORT_
All Other PinsHuman Body Model
Note 2: All parameters are tested at TA = +25NC. Specifications over temperature are guaranteed by design.
Note 3: All digital inputs at VCC or GND.
Note 4: Guaranteed by design.
Note 5: CB = total capacitance of one bus line in pF. tR and tF measured between 0.8V and 2.1V.
Note 6: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) to bridge
the undefined region of SCL’s falling edge.
Note 7: I
= 6mA. CB = total capacitance of one bus line in pF. tR and tF measured between 0.8V and 2.1V.
SINK
Note 8: Input filters on the SDA, SCL, and AD0 inputs suppress noise spikes less than 50ns.
1A2PORT5GPIO Port 5. Push-pull I/O.
2B2PORT6GPIO Port 6. Push-pull I/O.
3A3PORT7GPIO Port 7. Push-pull I/O.
4B3PORT15GPIO Port 15. Open-drain I/O. PORT15 can be configured as a constant-current sink.
5A4PORT14GPIO Port 14. Open-drain I/O. PORT14 can be configured as a constant-current sink.
6A5PORT13GPIO Port 13. Open-drain I/O. PORT13 can be configured as a constant-current sink.
7B4PORT12GPIO Port 12. Open-drain I/O. PORT12 can be configured as a constant-current sink.
8, 23B1, B5, C3GNDGround
9C5PORT11GPIO Port 11. Push-pull I/O.
10C4PORT10GPIO Port 10. Push-pull I/O.
11D5PORT9GPIO Port 9. Push-pull I/O.
12E5PORT8GPIO Port 8. Push-pull I/O.
13D4V
14E4AD0Address Input. Selects up to four device slave addresses (Table 2).
15D3SDAI2C-Compatible, Serial-Data I/O
16E3SCLI2C-Compatible Serial-Clock Input
17E2
NAMEFUNCTION
LA
Second Logic Level for GPIO Level Shifting (where VCC P VLA P 3.6V)
INTActive-Low Key-Switch Interrupt Output. INT is open-drain and requires a pullup resistor.
Positive Supply Voltage. Bypass to GND with a 0.1FF capacitor as close as possible to
the device.
19E1PORT0GPIO Port 0. Push-pull I/O.
20D1PORT1GPIO Port 1. Push-pull I/O.
21C2PORT2GPIO Port 2. Push-pull I/O.
22C1PORT3
GPIO Port 3. Push-pull I/
24A1PORT4GPIO Port 4. Push-pull I/O.
——EP
MAX7304
Exposed Pad (TQFN Only). Internally connected to GND. Connect to a large ground plane
to maximize thermal performance. Not intended as an electrical connection point.
constant-current and PWM intensity control. The maximum
constant-current level for each open-drain LED port is
The MAX7304 is an I2C-interfaced 16-port GPIO expander. The device features 12 push-pull GPIOs configured
for digital I/O and four open-drain GPIOs configurable
as constant-current outputs for LED applications up to
5V. The device supports a second 1.62V to 3.6V power
supply for level translation. The second logic supply
20mA. The intensity of the LED on each open-drain port
can be individually adjusted through a 256-step PWM
control. The port also features LED fading.
The device meets ESD requirements for Q8kV contact
discharge and Q15kV air-gap discharge on all port pins
(configured as GPIO and/or LED drivers).
voltage (VLA) must be set equal to or higher than VCC.
Each GPIO can be programmed to one of the two externally applied logic voltage levels. PORT15–PORT12
can also be configured as LED drivers that feature
On power-up, all control registers reset to power-up
values (Table 1) and the device is in sleep mode.
Table 1. Register Address Map and Power-Up Conditions
ADDRESS
CODE (hex)
0x01
0x31
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x40
0x42
0x43
0x45
0x48Read only0x00I2C timeout flagI2C timeout since last POR
0x50
0x51
0x52
0x53
READ/
WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POWER-UP
VALUE (hex)
0x0BConfigurationPower-down and I2C timeout enable
0x00LED driver enableLED driver enable register
0x00GPIO direction 1GPIO input/output control register 1 for PORT7–PORT0
0x00GPIO direction 2GPIO input/output control register 2 for PORT15–PORT8
0xFFGPO output mode 1
0x0FGPO output mode 2
0x00GPIO supply voltage 1
0x00GPIO supply voltage 2
0xFFGPIO values 1Debounced input or output values of PORT7–PORT0
0xFFGPIO values 2Debounced input or output values of PORT15–PORT8
0x00GPIO level-shifter enableGPIO level-shifter pair enable
0x00
0x00GPIO debouncePORT7–PORT0 debounce time setting
Table 1. Register Address Map and Power-Up Conditions (continued)
MAX7304
ADDRESS
CODE (hex)
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
READ/
WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POWER-UP
VALUE (hex)
0x00
0x00
0x00
0x00
0xFFInterrupt mask 1Interrupt mask for PORT7–PORT0
0xFFInterrupt mask 2Interrupt mask for PORT15–PORT8
0x00GPI trigger mode 1
0x00GPI trigger mode 2
REGISTER
FUNCTION
PORT12 LED
configuration
PORT13 LED
configuration
PORT14 LED
configuration
PORT15 LED
configuration
GPIOs
The device has 16 GPIO ports, of which four have
LED control functions. The ports can be used as logic
inputs and logic outputs. PORT15–PORT12 are also
configurable as constant-current PWM LED drivers. Each
ports’ logic level is referenced to VCC or VLA. The GPIO
port’s inputs can also be debounced. When in PWM
mode, the ports are set up to start their PWM cycle in
45N phase increments. This prevents large current spikes
on the LED supply voltage when driving multiple LEDs.
Configuration Register (0x01)
The configuration register controls the I2C bus timeout
feature (see Table 5 in the Register Tables section). The
bus timeout feature prevents the SDA being held low
when the SCL line hangs.
LED Driver Enable Register (0x31)
Bits D[3:0] correspond to PORT15–PORT12 on the
device. Set the corresponding bit to 1 for enabling the
LED driver circuitry and 0 for normal GPIO function (see
Table 6 in the Register Tables section).
GPIO Direction 1 and 2 Registers (0x34, 0x35)
These registers configure the pin as an input or an
output. GPIO direction 1 register bits D[7:0] correspond
with PORT7–PORT0 (see Table 7 in the Register Tables
section). GPIO direction 2 register bits D[7:0] correspond
with PORT15–PORT8 (see Table 8 in the Register Tables
section). Set the corresponding bit to 0 to configure as
input and 1 to configure as output.
DESCRIPTION
PORT12 interrupt, PWM mode control, and blinkperiod settings
PORT13 interrupt, PWM mode control, and blinkperiod settings
PORT14 interrupt, PWM mode control, and blinkperiod settings
PORT15 interrupt, PWM mode control, and blinkperiod settings
GPI edge-triggered detection setting for
PORT7–PORT0
GPI edge-triggered detection setting for
PORT15–PORT8
When the port is initially programmed as an input, there
is a delay of one debounce period prior to detecting
a transition on the input port. This is to prevent a false
interrupt from occurring when changing a port from an
output to an input.
GPO Output Mode 1 and 2 Registers (0x36, 0x37)
These registers configure the pins as an open-drain or