MAXIM MAX7302 User Manual

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General Description

The MAX7302 I2C-/SMBus™-compatible, serial-interfaced peripheral features 9 level-translating I/Os, and operates from a 1.62V to 3.6V power supply. The MAX7302 features a port supply V

that allows level-translation on I/O ports to operate from a separate power supply from 1.62V to 5.5V. An address select input, AD0, allows up to four unique slave addresses for the device.

The MAX7302 ports P2–P9 can be configured as inputs, push-pull outputs, and open-drain outputs. Port P1 can be configured as a general-purpose input, open-drain output, or an open-drain INT output. Ports P2–P9 can be configured as OSCIN and OSCOUT, respectively. Ports P2–P9 can also be used as configurable logic arrays (CLAs) to form user-defined logic gates, replacing external discrete gates. Outputs are capable of sinking up to 25mA, and sourcing up to 10mA when configured as push-pull outputs.

The MAX7302 includes an internal oscillator for PWM, blink, and key debounce, or to cascade multiple MAX7302s. The external clock can be used to set a specific PWM and blink timing. The RST input asynchronously clears the 2-wire interface and terminates a bus lockup involving the MAX7302.

All ports configured as an output feature a 33-step PWM, allowing any output to be set from fully off, 1/32 to 31/32 duty cycle, to fully on. All output ports also feature LED blink control, allowing blink periods of 1/8s, 1/4s, 1/2s, 1s, 2s, 4s, or 8s. Any port can blink during this period with a 1/16 to 15/16 duty cycle.

The MAX7302 is specified over the -40°C to +125°C temperature range and is available in 16-pin QSOP and 16-pin TQFN (3mm x 3mm) packages.

Applications

Cell Phones

Servers

System I/O Ports

LCD/Keypad Backlights

LED Status Indicators

Features

♦ 1.62V to 5.5V I/O Level-Translation Port Supply (VLA) ♦ 1.62V to 3.6V Power Supply ♦ 9 Individually Configurable GPIO Ports

P1 Open-Drain I/O P2–P9 Push-Pull or Open-Drain I/Os

♦ Individual 33-Step PWM Intensity Control ♦ Blink Controls with 15 Steps on Outputs ♦ 1kHz PWM Period Provides Flicker-Free LED

Intensity Control

♦ 25mA (max) Port Output Sink Current (100mA

max Ground Current)

♦ Inputs Overvoltage Protected Up to 5.5V (VLA) ♦ Transition Detection with Optional Interrupt Output ♦ Optional Input Debouncing ♦ I/O Ports Configurable as Logic Gates (CLA) ♦ External RST Input ♦ Oscillator Input and Output Enable Cascading

Multiple Devices

♦ Low 0.75µA (typ) Standby Current

MAX7302

SMBus/I2C Interfaced 9-Port,

Level-Translating GPIO and LED Driver with CLA

________________________________________________________________ Maxim Integrated Products 1

Ordering Information

19-0749; Rev 0; 7/07

Pin Configurations appear at end of data sheet.

SMBus is a trademark of Intel Corp.

PART

TEMP RANGE

PINPACKAGE

PKG

CODE

MAX7302AEE+

16 QSOP

E16-4

MAX7302ATE+

16 TQFN-EP*

T1633-4

+Denotes lead-free package. *EP = Exposed paddle.

ADO

µC

SDA

GND

+1.8V

P2 P3 P4 P5

1.8V OPEN-DRAIN OUTPUT P6 P7 P8 P9

+4.5V

MAX7302

4.5V PUSH-PULL OUTPUT

4.5V LOGIC INPUT

3.3V LOGIC INPUT

2.5V LOGIC INPUT

SCL

RST

INT

SDA

SCL

RST

P1/INT

Typical Operating Circuit

-40°C to +125°C

-40°C to +125°C (3mm x 3mm)

MAX7302

SMBus/I2C Interfaced 9-Port, Level-Translating GPIO and LED Driver with CLA

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VDD= 1.62V to 3.6V, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at VDD= 3.3V, VLA= 3.3V, TA= +25°C.) (Note 1)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

(All voltages referenced to GND.) V

..........................................................................-0.3V to +4V

, SCL, SDA, AD0, RST, P1..................................-0.3V to +6V

P2–P9 ............................................................-0.3V to V

+ 0.3V

P1–P9 Sink Current ............................................................25mA

P2–P9 Source Current ........................................................10mA

SDA Sink Current ...............................................................10mA

Current .......................................................................10mA

Current ........................................................................35mA

GND Current ....................................................................100mA

Continuous Power Dissipation (TA= +70°C)

16-Pin QSOP (derate 8.3mW/°C over +70°C)..............666mW

16-Pin TQFN (derate 14.7mW/°C over +70°C) ..........1176mW

Operating Temperature Range .........................-40°C to +125°C

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

PARAMETER

SYMBOL

CONDITIONS MIN TYP

MAX

UNITS

Operating Supply Voltage V

Port Logic Supply Voltage V

Power-On-Reset Voltage V

POR

VDD rising 1.0 1.3 1.6 V

Power-On-Reset Hysteresis

10 158 300

STB

Internal oscillator disabled; SCL, SDA, digital inputs at V

GND; P1–P9 (as inputs) at V

GND

0.75 2

Standby Current (Interface Idle)

OSC

Internal oscillator enabled; SCL, SDA, digital inputs at V

GND; P1–P9 (as inputs) at V

GND

17 25

µA

S up p l y C ur r ent ( Inter face Runni ng ) I

SUP

SCL

= 400kHz;

31 40 µA

Port Supply Current (VLA)I

VLA

Port inputs at VLA or GND 0.06 5 µA

Input High Voltage SDA, SCL, AD0, RST V

0.7 x V

Input Low Voltage SDA, SCL, AD0, RST V

Input High Voltage P1–P9 V

IHP

Input is VDD referred 0.7 x V

Input Low Voltage P1–P9 V

ILP

Input is VDD referred

Input High Voltage P1–P9 V

IHPA

Input is VLA referred 0.7 x V

Input Low Voltage P1–P9 V

ILPA

Input is VLA referred

IIH, IILVDD or GND -1 +1 µA

Input Leakage Current P1–P9

VLA or GND -2 +2 µA

Input Capacitance SDA, SCL, AD0, P1–P9, RST

8pF

VDD = 1.62V, I

SINK

= 3mA 0.05

VDD = 2.5V, I

SINK

= 16mA 0.19

Output Low Voltage P1–P9 V

VDD = 3.3V, I

SINK

= 20mA 0.19

VLA = 1.62V, I

SOURCE

= 0.5mA

1.58

VLA ≥ 2.5V, I

SOURCE

= 5mA

2.32Output High Voltage P2–P9 V

VLA ≥ 3.3V, I

SOURCE

= 10mA

3.1

Output Low Voltage SDA

SINK

= 6mA 0.3 V

PORHYST

1.62 3.60

1.62 5.50

Inp ut Leakag e C ur r ent S D A, S C L, AD 0, RST

, I

IHP

ILP

OLSDA

other d i g i tal i np uts at VDD or G N D

0.3 x V

0.11

0.31

1.55

VLA - 0.

VLA - 0.6

MAX7302

SMBus/I2C Interfaced 9-Port,

Level-Translating GPIO and LED Driver with CLA

_______________________________________________________________________________________ 3

PORT, INTERRUPT (INT), AND RESET (RST) TIMING CHARACTERISTICS

(VDD= 1.62V to 3.6V, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at VDD= 3.3V, VLA= 3.3V, TA= +25°C.) (Note 1)

(Figures 10, 15, 16 and 17)

PARAMETER

CONDITIONS

TYP

UNITS

CLK

= internal oscillator 32 kHz

Oscillator Frequency f

CLK

1 MHz

Port Output Data Valid High Time t

PPVH

CL ≤ 100pF 4 µs

Port Output Data Valid Low Time (Note 6) t

PPVL

CL ≤ 100pF (Note 2)

Port Input Setup Time t

PSU

CL = 100pF 0 µs

Port Input Hold Time t

CL = 100pF 4 µs

CLA Rise Time P5, P9 as Push-Pull Outputs 17

CLA Fall Time P5, P9 as Push-Pull Outputs

CL = 100pF, VLA ≥ 2.7V

CLA Propagation Delay P2, P3, or P4 to P5; P6, P7, or P8 to P9

CL = 100pF, VLA ≥ 2.7V 28 50 ns

INT Input Data Valid Time t

CL = 100pF 4 µs

INT Reset Delay Time from Acknowledge t

CL = 100pF 4 µs

RST Rising to START Condition Setup Time t

RST

RST Pulse Width t

SERIAL INTERFACE TIMING CHARACTERISTICS

(VDD= 1.62V to 3.6V, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at VDD= 3.3V, VLA= 3.3V, TA= +25°C.) (Note 1)

(Figure 10)

PARAMETER

CONDITIONS

TYP

UNITS

Serial-Clock Frequency f

SCL

kHz

Bus Timeout

31 ms

BUF

µs

Hold Time, (Repeated) START Condition

µs

Repeated START Condition Setup Time

µs

STOP Condition Setup Time

µs

Data Hold Time

(Note 3)

µs

Data Setup Time

SCL Clock Low Period t

LOW

µs

SCL Clock High Period t

HIGH

µs

(Notes 2, 4)

Fall Time of SDA Transmitting t

F.TX

(Note 4)

Pulse Width of Spike Suppressed t

(Note 5) 50 ns

C ap aci ti ve Load for E ach Bus Li ne C

(Note 2)

Note 1: All parameters are tested at TA= +25°C. Specifications over temperature are guaranteed by design. Note 2: Guaranteed by design. Note 3: A master device must provide a hold time of at least 300ns for the SDA signal (referred to V

of the SCL signal) to bridge the

undefined region of SCL’s falling edge.

Note 4: C

= total capacitance of one bus line in pF. tRand tFare measured between 0.3 x VDDand 0.7 x VDD.

Note 5: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns. Note 6: A startup time is required for the internal oscilator to start if it is not running already.

SYMBOL

= OS C IN exter nal i np ut

C LK

RFCLA

PDCLA

Bus Fr ee Tim e Betw een a S TOP and a S TART C ond i ti on

Rise Time of Both SDA and SCL Signals, Receiving

Fall Time of Both SDA and SCL Signals, Receiving

SYMBOL

TIMEOUT

HD,STA

SU,STA

SU,STO

HD,DAT

SU,DAT

MIN

900 500

MIN

1.3

0.6

100

1.3

0.7

20 + 0.1C b 300

20 + 0.1C b 250

MAX

1 / f

CLK

MAX

400

0.9

400

MAX7302

SMBus/I2C Interfaced 9-Port, Level-Translating GPIO and LED Driver with CLA

4 _______________________________________________________________________________________

Typical Operating Characteristics

(VDD= 3.3V, VLA= 3.3V and TA= +25°C, unless otherwise noted.)

STANDBY CURRENT

vs. TEMPERATURE

MAX7302 toc01

TEMPERATURE (°C)

SUPPLY CURRENT (µA)

1007525 500-25

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

-50 125

INTERFACE IDLE INTERNAL OSCILLATOR DISABLED

VDD = 3.6V

VDD = 1.62V

VDD = 3.3V

STANDBY CURRENT

vs. TEMPERATURE

MAX7302 toc02

TEMPERATURE (°C)

SUPPLY CURRENT (µA)

1007525 500-25

-50 125

INTERFACE IDLE INTERNAL OSCILLATOR RUNNING

VDD = 3.6V

VDD = 1.62V

VDD = 3.3V

STANDBY CURRENT

vs. TEMPERATURE

MAX7302 toc03

TEMPERATURE (°C)

SUPPLY CURRENT (µA)

1007525 500-25

100

-50 125

INTERFACE RUNNING

VDD = 3.6V

VDD = 1.62V

VDD = 3.3V

VOL vs. TEMPERATURE

MAX7302 toc04

TEMPERATURE (°C)

(V)

1007550250-25

0.06

0.12

0.18

0.24

0.30

-50 125

LOAD CURRENT = 20mA

VDD = 3.3V

VOL vs. I

SINK

MAX7302 toc05

SINK

(mA)

(V)

30252015105

0.1

0.2

0.3

0.4

035

VDD = 3.3V

VDD = 1.62V

VOH vs. TEMPERATURE

MAX7302 toc06

TEMPERATURE (°C)

(V)

1007550250-25

0.6

1.2

1.8

2.4

3.0

3.6

-50 125

LOAD CURRENT = 10mA

VDD = 3.6V

VDD = 3.3V

VOH vs. I

SOURCE

MAX7302 toc07

SOURCE

(mA)

(V)

1082 4 6

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

012

VLA = 3.6V

VLA = 1.62V

VLA = 3.3V

INTERNAL OSCILLATOR FREQUENCY

vs. TEMPERATURE

MAX7302 toc08

TEMPERATURE (°C)

FREQUENCY (kHz)

1007550250-25

-50 125

VDD = 3.3V

VDD = 3.6V

VDD = 1.62V

MAX7302

SMBus/I2C Interfaced 9-Port,

Level-Translating GPIO and LED Driver with CLA

_______________________________________________________________________________________ 5

Typical Operating Characteristics (continued)

(VDD= 3.3V, VLA= 3.3V and TA= +25°C, unless otherwise noted.)

CLA PROPAGATION DELAY

OUTPUT RISING

MAX7302 toc10

40ns/div

PORT2

2V/div

PORT3

2V/div

PORT5

2V/div

CL = 100pF

MAX7302 toc11

40ns/div

CLA PROPAGATION DELAY

OUTPUT FALLING

PORT2

2V/div

PORT3

2V/div

PORT5

2V/div

CL = 100pF

PORT2 5V/div

PORT3

5V/div

PORT4

5V/div

PORT5

5V/div

STAGGERED PWM OUTPUTS

400µs/div

MAX7302 toc09

MAX7302

SMBus/I2C Interfaced 9-Port, Level-Translating GPIO and LED Driver with CLA

6 _______________________________________________________________________________________

Pin Description

QSOP TQFN

115V

2 16 AD0

31RST

4 2 P1/INT

5 3 P2/OSCIN

6 4 P3/OSCOUT

7, 8, 9,

11, 12, 13

10 8 GND Ground

14 12 SCL Serial-Clock Input

15 13 SDA Serial-Data I/O

16 14 V

— EP EP Exposed Paddle on Package Underside. Connect to GND.

5, 6, 7,

9, 10, 11

NAME FUNCTION

P4–P9 Input/Output Ports. P4–P9 are general-purpose I/Os.

Port Supply for P1–P9. Connect VLA to a power supply between 1.62V and 5.5V. Bypass V

Address Input. Sets the device slave address. Connect to GND, V provide four address combinations.

Reset Inp ut. RST i s an acti ve- l ow i np ut, r efer enced to V and can b e confi g ur ed to p ut the d evi ce i n the p ow er - up r eset and /or to r eset the P W M and b l i nk ti m i ng .

Input/Output Port. P1/INT is a general-purpose I/O that can be configured as a transition detection interrupt output.

Input/Output Port. P2/OSCIN is a general-purpose I/O that can be configured as the oscillator input for PWM and blink features.

Input/Output Port. P3/OSCOUT is a general-purpose I/O that can be configured as the PWM/blink/timing oscillator output for PWM and blink features.

Positive Supply Voltage. Bypass VDD to GND with a 0.047µF ceramic capacitor.

to GND with a 0.047µF ceramic capacitor.

, SCL, or SDA to

, that cl ear s the 2- w i r e i nter face

MAX7302

SMBus/I2C Interfaced 9-Port,

Level-Translating GPIO and LED Driver with CLA

_______________________________________________________________________________________ 7

Detailed Description

The MAX7302 9-port, general-purpose port expander operates from a 1.62V to 3.6V power supply. Port P1 can be configured as an input and an open-drain output. Port P1 can also be configured to function as an INT output. Ports P2–P9 can be configured as inputs, push-pull outputs, and open-drain outputs. Ports P2–P9 can be used as simple configurable logic arrays (CLAs) to form user-defined logic gates.

Each port configured as an open-drain or push-pull output can sink up to 25mA. Push-pull outputs also have a 5mA source drive capability. The MAX7302 is rated to sink a total of 100mA into any combination of

its output ports. Output ports have PWM and blink capabilities, as well as logic drive.

Initial Power-Up

On power-up, the MAX7302 default configuration has all 9 ports, P1–P9, configured as input ports with logic levels referenced to VLA. The transition detection interrupt status flag resets and stays high (see Tables 1 and 2).

Device Configuration Registers

The device configuration registers set up the interrupt function, serial-interface bus timeout, and PWM/blink oscillator options, global blink period, and reset options (see Tables 3 and 4).

Block Diagram

AD0

SCL

SDA

RST

MAX7302

I2C

BANK

OUTPUT

LOGIC

I/O

CONTROL

CLA

I/O

INPUT LOGIC

P1–P9

GND

MAX7302

SMBus/I2C Interfaced 9-Port, Level-Translating GPIO and LED Driver with CLA

8 _______________________________________________________________________________________

Table 1. Register Address Map

ADDRESS

Ports P1–P9

Ports P_ are V

-referred input ports with interrupt

and debounce disabled

Configuration 26

RS T d oes not r eset r eg i ster s or counters; b l i nk p er i od i s 1H z; tr ansi ti on fl ag cl ear ; i nterr up t status fl ag cl ear

0x26

Configuration 27

Ports P1–P9 are GPIO ports; bus timeout is disabled

0x27

Ports CLA0 to CLA1 Default gate structure

CLA0 to CLA1 CLA not enable 0x70

Configuration 27 Lock, Ports P1–P5 Lock

Configuration 27 is not locked; ports P1–P5 are not locked

0x72

Ports P6–P9 Lock Ports P6–P9 are not locked 0x73

Table 2. Power-Up Register Status

Port P1 or INT Output 0x01 0x02 0x80

Port P2 or OSCIN Input 0x02 0x03 0x80

Port P3 or OSCOUT Output 0x03 0x04 0x80

Port P4 0x04 0x05 0x80

Port P5 0x05 0x06 0x80

Port P6 0x06 0x07 0x80

Port P7 0x07 0x08 0x80

Port P8 0x08 0x09 0x80

Port P9 0x09 0x0A or 0x4A 0x80

Configuration 26 0x26 0x27 0xEC

Configuration 27 0x27 0x28 0x8F

Ports P2–P5 Configurable Logic CLA0 0x28 0x29 0x00

Ports P6–P9 Configurable Logic CLA1 0x29 0x2A 0x00

Write Ports P2–P5 Same Data; Read P2 0x3C 0x3D 0x80

Write Ports P6–P9 Same Data; Read P6 0x3D 0x3E 0x80

FACTORY RESERVED (Do not write to these registers) 0x3C–0x3F 0x3F–0x40 0x00

CLA0 and CLA1 Configurable Logic Enable 0x70 0x71 0x00

CLA0 and CLA1 Configurable Logic Lock 0x71 0x72 0x00

Configuration 67 Lock, Ports P1–P5 Lock 0x72 0x73 0x00

Ports P6–P9 Lock 0x73 0x74 0xF0

FACTORY RESERVED (Do not write to these registers) 0x00 0x01 0x80

CODE (HEX)

0x01–0x09 1 0 0 0 0 0 0

0x28–0x29 0 0 0 0 0 0 0

D7 D6 D5 D4 D3 D2 D1

1110110

1000111

0000000

1111000

MAX7302

SMBus/I2C Interfaced 9-Port,

Level-Translating GPIO and LED Driver with CLA

_______________________________________________________________________________________ 9

Table 4. Configuration Register (0x27)

DESCRIPTION

FUNCTION

0 An interrupt has occurred on at least one interrupt enabled input port.

Interrupt status flag

(read only)

1* No interrupt has occurred on an interrupt enabled input port.

0 A transition has occurred on an input port.

Transition flag

(read only)

1* No transition has occurred on an input port.

D5 Reserved — Reserved

D4, D3, D2

0/1 Blink timer bits, see Table 10.

0* RST does not reset counters PWM/blink

D1 RST timer

1 RST resets PWM/blink counters

0* RST does not reset registers to power-on-reset state.

D0 RST POR

1 RST resets registers to power-on-reset state.

Table 3. Configuration Register (0x26)

*Default state.

VALUE

Blink prescalor bits

D7 Bus timeout

D6, D5, D4 Reserved

D3 P3/OSCOUT

D2 P2/OSCIN

D1 P1/INT output

D0 Input transition 0 Set to 0 on power-up to detect transition on inputs.

0 Enables the bus timeout feature.

1 Disables the bus timeout feature.

0 Reserved

1 Reserved

0 Sets P3 to output the oscillator.

1* Sets P3 as a GPIO controlled by register 0x03.

0 Sets P2 as the oscillator input.

1* Sets P2 as a GPIO controlled by register 0x02.

0 Sets P1 as the interrupt output.

1 Sets P1 as a GPIO controlled by register 0x01.

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