The MAX7060 frequency and power-programmable
ASK/FSK transmitter operates at 280MHz to 450MHz
frequencies. This device incorporates a fully integrated
fractional-N synthesizer, which allows the user to set the
RF operating frequency to a large fraction of the 280MHz
to 450MHz frequency range with a single crystal. For
example, the MAX7060 can be tuned from 285MHz to
420MHz with a 15MHz crystal. The RF output power is
user-controlled between +14dBm and -14dBm, with a
5V supply or with battery voltages as low as 3.2V. At the
minimum specified battery voltage of 2.1V, the RF output
power-control range is between +10dBm and -14dBm.
To maintain a good output power match across a broad
range of frequencies, the MAX7060 also contains a programmable matching capacitor connected in parallel
with the power amplifier (PA) output.
ASK modulation is accomplished by switching the PA
on and off, so excellent modulation (on/off) ratios are
achieved. ASK amplitude shaping is available to reduce
the width of the transmission spectrum. FSK modulation is accomplished by changing the coefficients of
the high-resolution fractional-N synthesizer, so FSK
deviation is extremely accurate. Data rates up to 50kbps
Manchester coded for ASK and 70kbps Manchester
coded for FSK can be maintained while still satisfying
regulatory emission-bandwidth standards. The full set of
configuration functions are handled by an on-chip serial
peripheral interface (SPI). There is also a manual mode
where a limited number of settings can be made directly
through selected pins.
The startup time is very short, and data can be transmitted 250Fs after the enable command. The MAX7060
operates from a 2.1V to 3.6V supply, or internal regulators can be used for supply voltages between 4.5V and
5.5V. The standby current in the 3V mode is 400nA at
room temperature, and can be reduced to 5nA using the
low-power shutdown (LSHDN) pin.
The MAX7060 is available in a 24-pin (4mm x 4mm) thin
QFN package and is specified for the automotive temperature range from -40NC to +125NC.
ASK/FSK Transmitter
Features
S Fully Integrated, Fast Fractional-N PLL
280MHz to 450MHz RF Frequency Frequency Range 100% Tested at +125NC < 250µs Startup Time Adjustable FSK Mark and Space Frequencies Ultra-Clean FSK Modulation 50kbps Manchester Data Rate ASK 70kbps Manchester Data Rate FSK
S Programmable Power Amplifier
+14dBm Tx Power with 5V Supply +10dBm Tx Power at 2.1V Supply 28dB Power-Control Range in 1dB Steps
and GPO2_MOD to GND .....................-0.3V to (V
PAOUT, ROUT,
and PAVOUT to GND ...................... -0.3V to (V
XTAL1 and XTAL2 to GND ................... -0.3V to (V
MAX7060
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS (5V OPERATION)
(Typical Application Circuit, 50I system impedance, tuned for 315MHz to 434MHz operation. V
280MHz to 450MHz, f
= +5V, TA = +25NC, PA matched for optimum output power, unless otherwise noted. All min and max values are 100% tested at TA
= +125NC and guaranteed by design and characterization over temperature, unless otherwise noted.)
Supply VoltageV
Regulated Analog Supply
Voltage
Active Supply CurrentI
Standby CurrentI
DIGITAL I/O
Input High Threshold V
Input Low Threshold V
to GND.......................................-0.3V to +6.0V
DD5
+ 0.3V)
DD5
+ 0.3V)
PAVDD
+ 0.3V)
AVDD
= 15MHz to 16MHz, TA = -40NC to +125NC, unless otherwise noted. Typical values are at V
XTAL
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DD
AVDD3.2V
PLL on, PA off
PLL on, PA on, data
at 50% duty cycle
(ASK), +10dBm
(PApwr = 0x19)
output power
(Notes 1, 2)
DD
STDBY
PLL on, PA on, data
at 100% duty cycle,
+10dBm (PApwr =
0x19) output power
(Note 1)
PLL on, PA on, data
at 100% duty cycle,
max (PApwr = 0x1E)
output power
(Note 1)
V
ENABLE
V
LSHDN
IH
IL
< VIL,
< VIL
Continuous Power Dissipation (TA = +70NC)
24-Pin Thin QFN
DC ELECTRICAL CHARACTERISTICS (5V OPERATION) (continued)
(Typical Application Circuit, 50I system impedance, tuned for 315MHz to 434MHz operation. V
280MHz to 450MHz, f
= +5V, TA = +25NC, PA matched for optimum output power, unless otherwise noted. All min and max values are 100% tested at TA
= +125NC and guaranteed by design and characterization over temperature, unless otherwise noted.)
= 15MHz to 16MHz, TA = -40NC to +125NC, unless otherwise noted. Typical values are at V
XTAL
IH
IL
I
= 100FA (GPO1 and GPO2_MOD,
SINK
OH
OL
gp1bst bit = 0)
I
= 200FA (GPO1), boost = on
SINK
(gp1bst bit = 1)
I
SOURCE
GPO2_MOD, gp1bst bit = 0)
I
SOURCE
(gp1bst bit = 1)
= 100FA (GPO1 and
= 200FA (GPO1), boost = on
DC ELECTRICAL CHARACTERISTICS (3V OPERATION)
(Typical Application Circuit, 50I system impedance, tuned for 315MHz to 434MHz operation. V
V
= V
DVDD
erwise noted. Typical values are at V
optimum output power, unless otherwise noted. All min and max values are 100% tested at TA = +125NC and guaranteed by design
and characterization over temperature, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Supply VoltageV
Active Supply CurrentI
Standby CurrentI
Shutdown CurrentI
= 2.1V to 3.6V, fRF = 280MHz to 450MHz, f
PAVDD
= V
DD5
DD
DD
STDBY
SHDN
GPOVDD
PLL on, PA off
PLL on, PA on, data
at 50% duty cycle
(ASK), +10dBm
(PApwr = 0x19)
output power
(Notes 1, 2)
PLL on, PA on, data
at 100% duty cycle,
+10dBm (PApwr =
0x19) output power
(Note 1)
V
ENABLE
V
LSHDN
V
ENABLE
V
LSHDN
= V
< VIL,
< V
< VIL,
> V
IL
IH
= 15MHz to 16MHz, TA = -40NC to +125NC, unless oth-
DC ELECTRICAL CHARACTERISTICS (3V OPERATION) (continued)
(Typical Application Circuit, 50I system impedance, tuned for 315MHz to 434MHz operation. V
V
= V
DVDD
erwise noted. Typical values are at V
optimum output power, unless otherwise noted. All min and max values are 100% tested at TA = +125NC and guaranteed by design
and characterization over temperature, unless otherwise noted.)
= 15MHz to 16MHz, TA = -40NC to +125NC, unless oth-
XTAL
= V
= 100FA (GPO1 and GPO2_MOD,
= 200FA (GPO1), boost = on
= 100FA (GPO1 and
= 200FA (GPO1), boost = on
AVDD
= V
DVDD
= V
PAVDD
= 2.7V, TA = +25NC, PA matched for
0.9 x
V
DVDD
= V
DD5
1.3
V
GPOVDD
- 0.10
V
GPOVDD
- 0.14
0.10
0.14
5
GPOVDD
0.1 x
V
DVDD
= V
AVDD
V
V
FA
FA
V
V
=
AC ELECTRICAL CHARACTERISTICS (5V OPERATION)
(Typical Application Circuit, 50I system impedance, tuned for 315MHz to 434MHz operation, V
280MHz to 450MHz, f
= +5V, TA = +25NC, PA matched for optimum output power, unless otherwise noted. All min and max values are 100% tested at TA
= +125NC and guaranteed by design and characterization over temperature, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
GENERAL CHARACTERISTICS
Frequency Range280450MHz
Power-On Timet
Maximum Data Rate
(PApwr = 0x1E)
= 15MHz to 16MHz, TA = -40NC to +125NC, unless otherwise noted. Typical values are at V
XTAL
ENABLE low-to-high transition, frequency
settled to within 50kHz of the desired
ON
carrier (includes time for V
ENABLE low-to-high transition, frequency
settled to within 5kHz of the desired carrier
(includes time for V
ASK mode
(no shaping)
FSK mode
PAVOUT
PAVOUT
Manchester encoded50
Nonreturn to zero100
Manchester encoded70
Nonreturn to zero140
AC ELECTRICAL CHARACTERISTICS (5V OPERATION) (continued)
(Typical Application Circuit, 50I system impedance, tuned for 315MHz to 434MHz operation, V
280MHz to 450MHz, f
= +5V, TA = +25NC, PA matched for optimum output power, unless otherwise noted. All min and max values are 100% tested at TA
= +125NC and guaranteed by design and characterization over temperature, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Carrier-Frequency Switching
Time
PLL
VCO GainK
PLL Phase Noise
Loop Bandwidth300kHz
Reference Frequency Input Level500mV
Frequency Divider Range1928
Frequency Deviation (FSK)
CRYSTAL OSCILLATOR
= 15MHz to 16MHz, TA = -40NC to +125NC, unless otherwise noted. Typical values are at V
XTAL
Time from end of SPI write or change of
FREQ0, FREQ1, or FREQ2 pins, to
frequency settled to within 5kHz of desired
carrier
(Typical Application Circuit, 50I system impedance, tuned for 315MHz to 434MHz operation. V
V
= V
DVDD
erwise noted. Typical values are at V
optimum output power, unless otherwise noted. All min and max values are 100% tested at TA = +125NC and guaranteed by design
and characterization over temperature, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
GENERAL CHARACTERISTICS
MAX7060
Frequency Range280450MHz
Power-On Timet
Maximum Data Rate
(PApwr = 0x19)
Carrier-Frequency Switching
Time
PLL
VCO GainK
PLL Phase Noise
Loop Bandwidth300kHz
Reference Frequency Input Level500mV
Frequency Divider Range1928
AC ELECTRICAL CHARACTERISTICS (3V OPERATION) (continued)
(Typical Application Circuit, 50I system impedance, tuned for 315MHz to 434MHz operation. V
V
= V
DVDD
erwise noted. Typical values are at V
optimum output power, unless otherwise noted. All min and max values are 100% tested at TA = +125NC and guaranteed by design
and characterization over temperature, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Maximum Carrier Harmonics
(Note 1)
Reference Spur-43dBc
PAOUT Capacitor Tuning Range0 to 7.75pF
= 2.1V to 3.6V, fRF = 280MHz to 450MHz, f
PAVDD
= V
DD5
GPOVDD
= V
AVDD
= 15MHz to 16MHz, TA = -40NC to +125NC, unless oth-
XTAL
= V
DVDD
= V
= 2.7V, TA = +25NC, PA matched for
PAVDD
SERIAL PERIPHERAL INTERFACE (SPI) TIMING CHARACTERISTICS
(SPI timing characteristics are valid for both 3V and 5V modes. SPI timing is production tested at worst-case temperature and supply
with a clock frequency of 3MHz.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Minimum SCLK_PWR0 Low to
Falling-Edge of CS_DEV Setup Time
Minimum CS_DEV Low to Rising
Edge of SCLK_PWR0 Setup Time
Minimum SCLK_PWR0 Low to
Rising Edge of CS_DEV Setup
Time
Minimum SCLK_PWR0 Low After
Rising Edge of CS_DEV Hold Time
t
SC
t
CSS
t
HCS
t
HS
= V
DD5
GPOVDD
-24dBc
30ns
15ns
60ns
15ns
= V
AVDD
=
MAX7060
Minimum Data Valid to SCLK_
PWR0 Rising-Edge Setup Time
Minimum Data Valid to SCLK_
PWR0 Rising-Edge Hold Time
Minimum SCLK_PWR0 High Pulse
Width
Minimum SCLK_PWR0 Low Pulse
Width
Minimum CS_DEV High Pulse
Width
Maximum Transition Time from
Falling-Edge of CS_DEV to Valid
GPO2_MOD
Maximum Transition Time from
Falling Edge of SCLK_PWR0 to
Valid GPO2_MOD
Note 1: Supply current and output power are greatly dependent on board layout and PAOUT match.
Note 2: 50% duty cycle at 10kHz ASK data (Manchester coded).
Note 3: Dependent on PCB trace capacitance.