The MAX7049 high-performance, single-chip, ultralow-power ASK/FSK UHF transmitter operates in the
industrial, scientific, medical (ISM) band at 288MHz to
945MHz carrier frequencies. The IC also includes a low
phase noise fractional-N synthesizer for precise tuning,
fast frequency agility, and low out-of-band power. To
support narrow-band applications, the IC has both
amplitude-shaping and frequency-shaping functions that
enable the user to optimize spectral efficiency. The IC
offers Tx power up to +15dBm. These features make the
transmitter ideally suited for long-range applications.
Additional system-level features of the IC include a digital
temperature sensor and a number of flexible GPOs for
monitoring radio status and for the control of external
functions. A complete transmitter system can be built
using a low-end microprocessor control unit (MCU), the
IC, a crystal, and a small number of passive components.
The IC is available in a small, 5mm x 5mm, 28-pin TQFN
package with an exposed pad. It is specified to operate
in the -40°C to +125°C automotive temperature range.
Applications
Automatic Meter Reading (AMR)
RF Modules
Long-Range, One-Way Remote Keyless Entry (RKE)
Wireless Sensor Networks
TPMS
Home Security
Home Automation
RFID
Remote Controls
Benefits and Features
S Transmitter (Tx)
Provides Long Transmit Range Up to +15dBm
21mA Tx Current for +10dBm Tx Power*
41mA Tx Current for +15dBm Tx Power*
Modulation Shaping, ASK, FSK
S General
Delivers Long Battery Life
< 50nA Shutdown Current
< 350nA Sleep Current
Minimizes the Number of I/Os Required
Between the IC and the MCU Serial Peripheral
Interface (SPI™)
Regulatory CompliantFCC Part 15 Frequency Hopping
ETSI EN300-220 Compatible
On-Chip Temperature Sensor
Fast Fractional-N Synthesizer with a
User-Defined External Loop Filter
*VDD = 3.0V. Includes losses for the matching network and
regulatory-compliant harmonic filter.
Ordering Information appears at end of data sheet.
For related parts and recommended products to use with this part,
refer to www.maxim-ic.com/MAX7049.related.
XOVDD, DVDD, and AVDD to EP ....................-0.3V to +3.6V
ENABLE, DATAIN, SDI, SDO, CS, SCLK,
GPO1, GPO2, HOP, and SHDN to EP . -0.3V to (VDD + 0.3V)
All Other Pins to EP .................................. -0.3V to (VDD + 0.3V)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
CAUTION! ESD SENSITIVE DEVICE
DC ELECTRICAL CHARACTERISTICS
(Figure 2, 50I system impedance, VDD = +2.1V to +3.6V, fRF = 868MHz, TA = -40°C to +125°C, unless otherwise noted. Typical
values are at VDD = +3.0V, TA = +25°C, unless otherwise noted. All min and max values are 100% tested at TA = +125°C and are
guaranteed by design and characterization over temperature, unless otherwise noted.)
(Figure 2, 50I system impedance, VDD = +2.1V to +3.6V, fRF = 868MHz, TA = -40°C to +125°C, unless otherwise noted. Typical
values are at VDD = +3.0V, TA = +25°C, unless otherwise noted. All min and max values are 100% tested at TA = +125°C and are
guaranteed by design and characterization over temperature, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Pulldown Sink Current 12.5
Pullup Source Current 12.5
In buffer mode, GPO1 250FA sink current,
Output Low Voltage V
Output High VoltageV
SDO 1mA sink current, and GPO2 4mA
OL
sink current
In buffer mode, GPO1 250FA source current,
SDO 1mA source current, and GPO2 4mA
OH
source current
0.225
VDD - 0.225
AC ELECTRICAL CHARACTERISTICS
(Figure 2, 50I system impedance, VDD = +2.1V to +3.6V, fRF = 868MHz, TA = -40°C to +125°C, unless otherwise noted. Typical
values are at VDD = +3.0V, TA = +25°C, unless otherwise noted. All min and max values are 100% tested at TA = +125°C and are
guaranteed by design and characterization over temperature, unless otherwise noted.)
FA
V
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
GENERAL CHARACTERISTICS
Divide-by-1 LO divider setting863945
Operating Frequency
Divide-by-3 LO divider setting287.7315
Maximum Data Rate
Maximum Frequency Deviation100kHz synthesizer loop bandwidth
Frequency Settling Timet
POWER AMPLIFIER
Maximum Output Power P
Programmable PA Bias Current
Step
Programmable PA Power
Dynamic Range
Modulation DepthWith respect to +10dBm output power57dB
Maximum Carrier HarmonicsWith output matching network-50dBc
MAX
Manchester encoded100
NRZ encoded200
From Enable low-to-high transition to LO
within 5kHz of final value, 100kHz synthesizer
loop bandwidth
ON
From Enable low-to-high transition to LO
within 1kHz of final value, 100kHz synthesizer
loop bandwidth
Match to 50I, including harmonic filter
With Q1% 56.2kI external PA reference
current setting resistor
Power range from decimal 1 to decimal 63
on digital PA bias current
(Figure 2, 50I system impedance, VDD = +2.1V to +3.6V, fRF = 868MHz, TA = -40°C to +125°C, unless otherwise noted. Typical
values are at VDD = +3.0V, TA = +25°C, unless otherwise noted. All min and max values are 100% tested at TA = +125°C and are
guaranteed by design and characterization over temperature, unless otherwise noted.)
(Figure 2, 50I system impedance, VDD = +2.1V to +3.6V, fRF = 868MHz, TA = -40°C to +125°C, unless otherwise noted. Typical
values are at VDD = +3.0V, TA = +25°C, unless otherwise noted. All min and max values are 100% tested at TA = +125°C and are
guaranteed by design and characterization over temperature, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Minimum SCLK Low to Rising
Edge of CS Setup Time
Minimum SCLK Low after Rising
Edge of CS Hold Time
Minimum Data Valid to SCLK
Rising-Edge Setup Time
Minimum Data Valid to SCLK
Rising-Edge Hold Time
Minimum SCLK High Pulse
Width
Minimum SCLK Low Pulse Widtht
Minimum CS High Pulse Width
Maximum Transition Time from
Falling Edge of CS to Valid SDO
Maximum Transition Time from
Falling Edge of SCLK to
Valid SDO
(Figure 2, 50Ω system impedance, VDD = +2.1V to +3.6V, fRF = 288MHz to 945MHz, TA = -40°C to +125°C, unless otherwise noted.
Typical values are at VDD = +3.0V, TA = +25°C, unless otherwise noted.)
(Figure 2, 50Ω system impedance, VDD = +2.1V to +3.6V, fRF = 288MHz to 945MHz, TA = -40°C to +125°C, unless otherwise noted.
Typical values are at VDD = +3.0V, TA = +25°C, unless otherwise noted.)
(Figure 2, 50Ω system impedance, VDD = +2.1V to +3.6V, fRF = 288MHz to 945MHz, TA = -40°C to +125°C, unless otherwise noted.
Typical values are at VDD = +3.0V, TA = +25°C, unless otherwise noted.)
ASK MODULATION SPECTRUM
(3kHz RBW, 4kHz SQUARE-WAVE MODULATION,
+9dBm OUTPUT POWER, WITH
+10dBm AT 3V MATCH)
0
-10
-20
-30
-40
-50
-60
-70
-80
867.75
867.85 867.95 868.05 868.15 868.25
867.80 867.90 868.00 868.10 868.20
GAUSSIAN
FREQUENCY (MHz)
FSK MODULATION SPECTRUM
(3kHz RBW, 4kHz SQUARE-WAVE MODULATION,
Q100kHz DEVIATION, +10dBm OUTPUT
POWER, WITH +10dBm AT 3V MATCH)
0
-10
GAUSSIAN
-20
-30
-40
-50
POWER (dBc)
-60
-70
-80
-90
867.4867.8868.2868.6867.6868.0868.4
UNSHAPED
FREQUENCY (MHz)
MAX7049 toc13
FSK MODULATION SPECTRUM (1kHz RBW,
4kHz SQUARE-WAVE MODULATION,
±4kHz DEVIATION, +10dBm OUTPUT
POWER, WITH +10dBm AT 3V MATCH)
0
-10
GAUSSIAN
-20
-30
-40
POWER (dBc)
-50
-60
-70
-80
867.95 867.97 867.99 868.01 868.03 868.05
867.96 867.98 868.00 868.02 868.04
MAX7049 toc16
FREQUENCY (MHz)
FSK MODULATION SPECTRUM
±4kHz DEVIATION, +10dBm OUTPUT POWER,
WITH +10dBm AT 3V MATCH)
0
-10
MAX7049 toc14
UNSHAPED
-20
-30
-40
POWER (dBc)
-50
-60
-70
-80
867.95 867.97 867.99 868.01 868.03 868.05
FREQUENCY (MHz)
FSK MODULATION SPECTRUM
(3kHz RBW, 4kHz SQUARE-WAVE MODULATION,
Q100kHz DEVIATION, +10dBm OUTPUT
POWER, WITH +10dBm AT 3V MATCH)
0
-10
UNSHAPED
-20
-30
-40
-50
POWER (dBc)
-60
-70
-80
-90
867.4867.8868.2868.6867.6868.0868.4
FREQUENCY (MHz)
(Figure 2, 50Ω system impedance, VDD = +2.1V to +3.6V, fRF = 288MHz to 945MHz, TA = -40°C to +125°C, unless otherwise noted.
Typical values are at VDD = +3.0V, TA = +25°C, unless otherwise noted.)
1PAVDDPower Amplifier Supply Voltage Input. Bypass to ground with 33pF capacitor as close as possible to the pin.
External PA Bias Current Setting Resistor Connection. Couple to ground through a Q1% tolerance low-
2REXTPA
3, 10,
14
N.C.No Connection. Leave unconnected.
4LOVDD
5VCOVDD
6CTRL
7CPVDD
8CPOUTCharge-Pump Output. Connect through passive loop filter to CTRL.
9PLLVDD Synthesizer Supply Voltage Input. Bypass to ground with 33pF capacitor as close as possible to the pin.
11XOVDD
temperature coefficient resistor. A resistor of 56.2kI is recommended for a 0.5mA nominal PA bias
current DAC LSB value.
Local Oscillator (LO) Supply Voltage Input. Bypass to ground with 33pF capacitor as close as possible
to the pin.
Voltage-Controlled Oscillator (VCO) Supply Voltage. Bypass to ground with 1FF capacitor as close as
possible to the pin.
Control (Tuning) Voltage for VCO Input. Referenced to VCOVDD pin. Connect through passive loop filter to
CPOUT.
Charge-Pump Supply Voltage Input. Bypass to ground with 0.01FF capacitor as close as possible to the pin.
Crystal Oscillator Supply Voltage Input. Bypass to ground with 0.1FF capacitor as close as possible to
the pin.
Collector Crystal Input. Connect to crystal either directly or through an AC-coupling capacitor. A shunt
12XTALC
13XTALB
15SDOSerial Peripheral Interface (SPI) Data Output. It can also be configured as a general-purpose digital output.
16DATAIN Transmitter Data Input. The Datain function can also be controlled by SPI. Internally pulled to ground.
17ENABLE
18SCLKSPI Clock. Internally pulled to ground.
19SDISPI Data Input. Internally pulled to ground.
20
21GPO2General-Purpose Output 2. High drive strength digital general-purpose output.
22DVDD
23HOP
24GPO1General-Purpose Output 1. Low drive strength digital general-purpose output.
25SHDN
26AVDD
27PA+
28PA-
—EP
CS
capacitance to ground might be needed depending on the specified load capacitance of the crystal and
PCB stray capacitances. Can be driven by an AC-coupled external reference with a signal swing of
0.8V
Base Crystal Input. Connect to crystal either directly or through an AC-coupling capacitor. A shunt
capacitance to ground might be needed depending on the specified load capacitance of the crystal and
PCB stray capacitances. Must be DC shorted to ground if XTALC is driven by external reference.
Enable. Drive high for active operation. Drive low or leave unconnected to put the device into Sleep mode.
The enable function can also be controlled by SPI. Internally pulled to ground.
SPI Active-Low Chip Select. Internally pulled to supply.
Digital Supply Voltage Input. Bypass to ground with 0.1FF capacitor as close as possible to the pin.
Frequency Hop Pin. Transfers the base[20:0] bits to the fractional-N divider. See the Fractional-N Synthesizer
section. The hop function can also be controlled by SPI. Internally pulled to ground.
Shutdown Digital Input. Turns off internal power-on-reset (POR) circuit when driven high. Register contents
are set to the initial state when driven high. Must be driven low for normal operation. Not internally pulled to
supply or ground.
Analog Supply Voltage Input. Bypass to ground with a 1FF capacitor as close as possible to the pin.
Power Amplifier (PA) Positive Output. Requires DC current path to supply voltage through an inductive path.
The DC current path can be part of the output impedance matching and harmonic filter network.
Power Amplifier (PA) Negative Output. Requires DC current path to supply voltage through an inductive path.
The DC current path can be part of the output impedance matching and harmonic filter network.
Exposed Pad. This is the only ground connection. Solder evenly to the PCB ground plane for proper
operation. Multiple vias from the solder pad to the PCB ground plane are recommended.
The MAX7049 includes a single precision local oscillator
fractional-N synthesizer with an integrated VCO, fractional-N divider, phase/frequency detector, charge pump,
LO divider, and lock detector. The loop filter is located
off-chip to allow the user to optimize the synthesizer noise
and transient characteristics for a particular application.
In FSK transmit mode, the synthesizer transitions between
the mark and the space frequency based on the state
of the DATAIN pin or datain bit (Datain register, 0x3D,
bit 6). A user-programmable frequency-shaping function
enables the user to precisely define the transition from the
mark frequency to the space frequency and vice versa to
minimize spectral width of the modulated Tx waveform.
The IC utilizes a differential emitter-coupled, dual-opencollector power amplifier for the transmitter output.
SCLK 18
PFD
XTALB
21
* OPTIONAL I/Os FROM/ TO MCU.
DATAIN*
SDO*
17ENABLE*
16
15
The bias current of the output stage is set with a combination of an external resistor and an internal amplitudeshaping function. The programmable shaping function enables the user to precisely define the transition
between carrier on and carrier off and vice versa based
on the state of the DATAIN pin or datain bit so as to
minimize the spectral width of the modulated Tx signal.
Linear amplitude ramping is used in FSK mode as the PA
is enabled at the beginning of a data burst and disabled
at the end of a data burst for spectral control.
A complete transmitter system can be built using a
low-end MCU, the IC, a crystal, and a small number of
passive components for power-supply bypassing and for
RF matching, as illustrated in Figure 2.
Communication between the MCU and the IC is accomplished through a 4-pin SPI bus and a number of optional
digital inputs and outputs.