MAXIM MAX6955 Technical data

General Description

The MAX6955 is a compact display driver that interfaces microprocessors to a mix of 7-segment, 14-segment, and 16-segment LED displays through an I2C-compatible 2-wire serial interface. The MAX6955 drives up to 16 digits 7-segment, 8 digits 14-segment, 8 digits 16-segment, or 128 discrete LEDs, while functioning from a supply voltage as low as 2.7V. The driver includes five I/O expander or general-purpose I/O (GPIO) lines, some or all of which can be configured as a key-switch reader. The key-switch reader automatically scans and debounces a matrix of up to 32 switches.

Included on chip are full 14- and 16-segment ASCII 104-character fonts, a hexadecimal font for 7-segment displays, multiplex scan circuitry, anode and cathode drivers, and static RAM that stores each digit. The maximum segment current for the display digits is set using a single external resistor. Digit intensity can be independently adjusted using the 16-step internal digital brightness control. The MAX6955 includes a low-power shutdown mode, a scan-limit register that allows the user to display from 1 to 16 digits, segment blinking (synchronized across multiple drivers, if desired), and a test mode, which forces all LEDs on. The LED drivers are slew-rate limited to reduce EMI.

For an SPI™-compatible version, refer to the MAX6954 data sheet. An evaluation kit (EV kit) for the MAX6955 is available.

Applications

Set-Top Boxes Automotive

Panel Meters Bar Graph Displays

White Goods Audio/Video Equipment

Features

♦ 400kbps 2-Wire I2C-Compatible Interface ♦ 2.7V to 5.5V Operation ♦ Drives Up to 16 Digits 7-Segment, 8 Digits

14-Segment, 8 Digits 16-Segment, 128 Discrete LEDs, or a Combination of Digit Types

♦ Drives Common-Cathode Monocolor and Bicolor

LED Displays

♦ Built-In ASCII 104-Character Font for 14-Segment

and 16-Segment Digits and Hexadecimal Font for 7-Segment Digits

♦ Automatic Blinking Control for Each Segment ♦ 10µA (typ) Low-Power Shutdown (Data Retained) ♦ 16-Step Digit-by-Digit Digital Brightness Control ♦ Display Blanked on Power-Up ♦ Slew-Rate-Limited Segment Drivers for Lower EMI ♦ Five GPIO Port Pins Can Be Configured as Key-

Switch Reader to Scan and Debounce Up to 32 Switches with n-Key Rollover

♦ IRQ Output when a Key Input is Debounced ♦ 36-Pin SSOP and 40-Pin TQFN Packages ♦ Automotive Temperature Range Standard

MAX6955

2-Wire Interfaced, 2.7V to 5.5V LED Display

Driver with I/O Expander and Key Scan

________________________________________________________________ Maxim Integrated Products 1

Ordering Information

19-2548; Rev 2; 12/06

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

PART

TEMP RANGE

PINPACKAGE

PKG

CODE

MAX6955AAX

36 SSOP A36-2

MAX6955ATL+

T4066- 5

Pin Configurations and Typical Operating Circuits appear at end of data sheet.

ISET

OSC

OSC_OUT

BLINK

SCL AD0 AD1 SDA

2-WIRE SERIAL INTERFACE

RAM

BLINK

CONTROL

CONFIGURATION

CHARACTER GENERATOR

ROM

CURRENT

SOURCE

DIVIDER/ COUNTER NETWORK

DIGIT

MULTIPLEXER

PWM

BRIGHTNESS

CONTROL

GPIO

AND KEY-SCAN

CONTROL

LED

DRIVERS

O0 TO O18

P0 TO P4

MAX6955

Functional Diagram

EVALUATION KIT

AVAILABLE

SPI is a trademark of Motorola, Inc.

*EP = Exposed paddle.

+Denotes lead-free package.

-40°C to +125°C

40 TQFN-EP* (6mm x 6mm)

MAX6955

2-Wire Interfaced, 2.7V to 5.5V LED Display Driver with I/O Expander and Key Scan

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Voltage (with Respect to GND)

V+ .........................................................................-0.3V to +6V

SCL, SDA, AD0, AD1 ...........................................-0.3V to +6V

All Other Pins............................................-0.3V to (V+ + 0.3V)

Current

O0–O7 Sink Current ......................................................935mA

O0–O18 Source Current .................................................55mA

SCL, SDA, AD0, AD1, BLINK, OSC, OSC_OUT, ISET ....20mA

P0, P1, P2, P3, P4 ...........................................................40mA

GND .....................................................................................1A

Continuous Power Dissipation (T

= +70°C)

36-Pin SSOP (derate at 11.8mW/°C above +70°C) .....941mW

40-Pin TQFN (derate at 25.6mW/°C above +70°C)....2051.3mW

Operating Temperature Range

MIN

to T

MAX

) ...............................................-40°C to +125°C

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

DC ELECTRICAL CHARACTERISTICS

(Typical Operating Circuit, V+ = 2.7V to 5.5V, TA= T

MIN

to T

MAX

, unless otherwise noted.) (Note 1)

PARAMETER

CONDITIONS

UNITS

Operating Supply Voltage V+ 2.7 5.5 V

TA = +25°C 10 35

Shutdown Supply Current I

SHDN

Shutdown mode, all digital inputs at V+ or GND

= T

MIN

to T

MAX

µA

TA = +25°C 22 30

Operating Supply Current I+

All segments on, all digits scanned, intensity set to full, internal oscillator, no display or OSC_OUT load connected

= T

MIN

to T

MAX

OSC = RC oscillator, R

SET

= 56kΩ,

SET

= 22pF, V+ = 3.3V

Master Clock Frequency f

OSC

OSC driven externally 1 8

MHz

Dead Clock Protection Frequency

OSC

95 kHz

OSC Internal/External Detection Threshold

OSC

1.7 V

OSC High Time t

50 ns

OSC Low Time t

50 ns

Slow Segment Blink Period

OSC = RC oscillator, R

SET

= 56kΩ,

SET

= 22pF, V+ = 3.3V

Fast Segment Blink Period

OSC = RC oscillator, R

SET

= 56kΩ,

SET

= 22pF, V+ = 3.3V

0.5 s

Fast or Slow Segment Blink Duty Cycle

SYMBOL

MIN TYP MAX

SLOWBLINK

FASTBLINK

49.5 50.5

MAX6955

2-Wire Interfaced, 2.7V to 5.5V LED Display

Driver with I/O Expander and Key Scan

_______________________________________________________________________________________ 3

DC ELECTRICAL CHARACTERISTICS (continued)

(Typical Operating Circuit, V+ = 2.7V to 5.5V, TA= T

MIN

to T

MAX

, unless otherwise noted.) (Note 1)

PARAMETER

CONDITIONS

UNITS

LED

= 2.2V,

V+

= 3.3V

Segment Drive Source Current I

SEG

LED

= 2.2V,

V+

= 2.7V

= +25°C -32 -40 -48 mA

Segment Current Slew Rate

TA = +25°C, V+ = 3.3V 11

mA/µs

Segment Drive Current Matching

∆I

SEG

TA = +25°C, V+ = 3.3V 5 %

LOGIC INPUTS AND OUTPUTS

Input High Voltage SDA, SCL, AD0, AD1

0.7 x V+

Input Low Voltage SDA, SCL, AD0, AD1

0.3 x V+

Input Leakage Current SDA, SCL, AD0, AD1, OSC, P0, P1, P2, P3, P4

, I

-1 +1 µA

SDA Output Low Voltage V

OLSDAISINK

= 6mA 0.4 V

Port Logic-High Input Voltage P0, P1, P2, P3, P4

IHP

0.7 x V+

Port Logic-Low Input Voltage P0, P1, P2, P3, P4

ILP

0.3 x V+

Port Hysteresis Voltage P0, P1, P2, P3, P4

∆V

0.03 x V+

Port Input Pullup Current from V+

IPU

P0 to P3 configured as key-scan inputs, V+ = 3.3V

75 µA

Port Output Low Voltage V

OLP

SINK

= 8mA 0.3 0.5 V

Blink Output Low Voltage V

OLBKISINK

= 0.6mA 0.1 0.3 V

OSC_OUT Output High Voltage

SOURCE

= 1.6mA

V+ -

0.4

OSC_OUT Output Low Voltage

SINK

= 1.6mA 0.4 V

SYMBOL

∆I

SEG

/∆t

MIN TYP MAX

OHOSC

OLOSC

MAX6955

2-Wire Interfaced, 2.7V to 5.5V LED Display Driver with I/O Expander and Key Scan

4 _______________________________________________________________________________________

TIMING CHARACTERISTICS

(Typical Operating Circuit, V+ = 2.7V to 5.5V, TA= T

MIN

to T

MAX

, unless otherwise noted.) (Note 1)

PARAMETER

CONDITIONS

UNITS

TIMING CHARACTERISTICS

Serial Clock Frequency f

SCL

kHz

Bus Free Time Between a STOP and a START Condition

BUF

1.3 µs

Hold Time (Repeated) START Condition

0.6 µs

Repeated START Condition Setup Time

0.6 µs

STOP Condition Setup Time

0.6 µs

Data Hold Time

(Note 3) 0.9 µs

Data Setup Time

SCL Clock Low Period t

LOW

1.3 µs

SCL Clock High Period t

HIGH

0.6 µs

Rise Time of Both SDA and SCL Signals, Receiving

(Notes 2, 4)

20 +

Fall Time of Both SDA and SCL Signals, Receiving

(Notes 2, 4)

20 +

Fall Time of SDA Transmitting tF, t

(Notes 2, 5)

20 +

Pulse Width of Spike Suppressed t

(Notes 2, 6) 0 50 ns

Capacitive Load for Each Bus Line

(Note 2)

Note 1: All parameters tested at TA= +25°C. Specifications over temperature are guaranteed by design. Note 2: Guaranteed by design. Note 3: A master device must provide a hold time of at least 300ns for the SDA signal (referred to V

- of the SCL signal) in order to

bridge the undefined region of SCL’s falling edge.

Note 4: C

= total capacitance of one bus line in pF. tRand tFmeasured between 0.3V+ and 0.7V+.

Note 5: I

SINK

≤ 6mA. CB= total capacitance of one bus line in pF. tRand tFmeasured between 0.3V+ and 0.7V+.

Note 6: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.

SYMBOL

MIN TYP MAX

400

STA

tSU, t

STA

SU:STO

tHD, t

DAT

tSU, t

DAT

100

300

0.1C

400

MAX6955

2-Wire Interfaced, 2.7V to 5.5V LED Display

Driver with I/O Expander and Key Scan

_______________________________________________________________________________________ 5

Typical Operating Characteristics

(V+ = 3.3V, LED forward voltage = 2.4V, Typical Application Circuit, TA= +25°C, unless otherwise noted.)

INTERNAL OSCILLATOR FREQUENCY

vs. TEMPERATURE

MAX6955 toc01

TEMPERATURE (°C)

OSCILLATOR FREQUENCY (MHz)

110805020-10

3.8

4.0

4.2

4.4

3.6

-40

SET

= 56kΩ

SET

= 22pF

SUPPLY VOLTAGE (V)

5.04.54.03.53.02.5 5.5

INTERNAL OSCILLATOR FREQUENCY

vs. SUPPLY VOLTAGE

MAX6955 toc02

OSCILLATOR FREQUENCY (MHz)

3.8

4.0

4.2

4.4

3.6

SET

= 56kΩ

SET

= 22pF

100ns/div

OSC: 500mV/div

OSC_OUT: 2V/div

MAX6954 toc03

OSC

OSC_OUT

INTERNAL OSCILLATOR WAVEFORM

AT OSC AND OSC_OUT PINS

SET

= 56kΩ

SET

= 22pF

DEAD CLOCK OSCILLATOR FREQUENCY

vs. SUPPLY VOLTAGE

100

105

110

SUPPLY VOLTAGE (V)

5.04.54.03.53.02.5 5.5

MAX6955 toc04

OSCILLATOR FREQUENCY (MHz)

SET

= 56kΩ

SET

= GND

CURRENT NORMALIZED TO 40mA

0.94

0.96

0.98

1.00

1.02

0.92

SEGMENT SOURCE CURRENT

vs. SUPPLY VOLTAGE

SUPPLY VOLTAGE (V)

5.04.54.03.53.02.5 5.5

MAX6955 toc05

LED

= 1.8V

1V/div

200µs/div

MAX6954 toc06

O18

WAVEFORM AT PINS O0 AND O18,

MAXIMUM INTENSITY

GPIO SINK CURRENT

vs. TEMPERATURE

MAX 6955 toc07

TEMPERATURE (°C)

GPIO SINK CURRENT (mA)

110805020-10

-40

VCC = 5.5V

VCC = 3.3V

VCC = 2.5V

OUTPUT = LOW V

PORT

= 0.6V

PORT INPUT PULLUP CURRENT

vs. TEMPERATURE

MAX6955 toc08

TEMPERATURE (°C)

KEY-SCAN SOURCE CURRENT (mA)

110805020-10

0.1

0.2

0.3

0.4

0.5

-40

VCC = 5.5V

VCC = 3.3V

VCC = 2.5V

OUTPUT = HIGH V

PORT

= 1.4V

400µs/div

KEY_A: 1V/div

IRQ: 2V/div

MAX6954 toc09

KEY_A

IRQ

KEY-SCAN OPERATION

(KEY_A AND IRQ)

MAX6955

Detailed Description

The MAX6955 is a serially interfaced display driver that can drive up to 16 digits 7-segment, 8 digits 14-segment, 8 digits 16-segment, 128 discrete LEDs, or a combination of these display types. Table 1 shows the drive capability of the MAX6955 for monocolor and bicolor displays.

The MAX6955 includes 104-character ASCII font maps for 14-segment and 16-segment displays, as well as the hexadecimal font map for 7-segment displays. The characters follow the standard ASCII font, with the addition of the following common symbols: £, A€ , ¥, °, µ, ±, ↑, and ↓. Seven bits represent the 104-character font map; an 8th bit is used to select whether the decimal

point (DP) is lit. Seven-segment LED digits can be controlled directly or use the hexadecimal font. Direct segment control allows the MAX6955 to be used to drive bar graphs and discrete LED indicators.

Tables 2, 3, and 4 list the connection schemes for 16-, 14-, and 7-segment digits, respectively. The letters in Tables 2, 3, and 4 correspond to the segment labels shown in Figure 1. (For applications that require mixed display types, see Tables 38–41.)

Serial Interface

Serial Addressing

The MAX6955 operates as a slave that sends and receives data through an I2C-compatible 2-wire interface. The interface uses a serial data line (SDA) and a

2-Wire Interfaced, 2.7V to 5.5V LED Display Driver with I/O Expander and Key Scan

6 _______________________________________________________________________________________

Pin Description

SSOP

NAME FUNCTION

1, 2,

34, 35, 36

36, 37,

P0–P4

General-Purpose I/O Ports (GPIOs). GPIO can be configured as logic inputs or open-drain outputs. Enabling key scanning configures some or all ports P0–P3 as key-switch matrix inputs with internal pullup and port P4 as IRQ output.

3 38 AD0

Address Input 0. Sets device slave address. Connect to GND, V+, SCL, or SDA to give four logic combinations. See Table 5.

4 39 SDA I2C-Compatible Serial Data I/O

5 40 SCL I2C-Compatible Serial Clock Input

6 1 AD1

Address Input 1. Sets device slave address. Connect to GND, V+, SCL, or SDA to give four logic combinations. See Table 5.

7–15,

22–31

2–10,

21–30

Digit/Segment Drivers. When acting as digit drivers, outputs O0 to O7 sink current from the display common cathodes. When acting as segment drivers, O0 to O18 source current to the display anodes. O0 to O18 are high impedance when not being used as digit or segment drivers.

16, 18

GND Ground

17 14 ISET

Segment Current Setting. Connect ISET to GND through series resistor R

SET

to set the peak

current.

19, 21

V+

Positive Supply Voltage. Bypass V+ to GND with a 47µF bulk capacitor and a 0.1µF ceramic capacitor.

20 17 OSC

Multiplex Clock Input. To use internal oscillator, connect capacitor C

SET

from OSC to GND.

To use external clock, drive OSC with a 1MHz to 8MHz CMOS clock.

32 31 BLINK Blink Clock Output. Output is open drain.

33 32

Clock Output. OSC_OUT is a buffered clock output to allow easy blink synchronization of multiple MAX6955s. Output is push-pull.

—

N.C. Not Internally Connected

—EP EP

Exposed Paddle. Internally connected to GND. Connect to a large ground plane to improve thermal performance.

TQFN

33, 34, 35

O0–O18

12, 13, 15

16, 18, 19

11, 20

OSC_OUT

MAX6955

2-Wire Interfaced, 2.7V to 5.5V LED Display

Driver with I/O Expander and Key Scan

_______________________________________________________________________________________ 7

serial clock line (SCL) to achieve bidirectional communication between master(s) and slave(s). A master (typically a microcontroller) initiates all data transfers to and from the MAX6955, and generates the SCL clock that synchronizes the data transfer (Figure 2).

The MAX6955 SDA line operates as both an input and an open-drain output. A pullup resistor, typically 4.7kΩ, is required on the SDA. The MAX6955 SCL line operates only as an input. A pullup resistor, typically 4.7kΩ, is required on SCL if there are multiple masters on the 2-wire interface, or if the master in a single-master system has an open-drain SCL output.

Each transmission consists of a START condition (Figure 3) sent by a master, followed by the MAX6955 7-bit slave address plus R/W bit (Figure 4), a register

address byte, 1 or more data bytes, and finally a STOP condition (Figure 3).

Start and Stop Conditions

Both SCL and SDA remain high when the interface is not busy. A master signals the beginning of a transmission with a START (S) condition by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave, it issues a STOP (P) condition by transitioning the SDA from low to high while SCL is high. The bus is then free for another transmission (Figure 3).

Bit Transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain stable while SCL is high (Figure 5).

Acknowledge

The acknowledge bit is a clocked 9th bit that the recipient uses to handshake receipt of each byte of data (Figure 6). Thus, each byte transferred effectively requires 9 bits. The master generates the 9th clock pulse, and the recipient pulls down SDA during the acknowledge clock pulse, such that the SDA line is stable low during the high period of the clock pulse. When the master is transmitting to the MAX6955, the MAX6955 generates the acknowledge bit because the MAX6955 is the recipient. When the MAX6955 is transmitting to the master, the master generates the acknowledge bit because the master is the recipient.

Slave Address

The MAX6955 has a 7-bit-long slave address (Figure

4). The eighth bit following the 7-bit slave address is the R/W bit. It is low for a write command, high for a read command.

The first 3 bits (MSBs) of the MAX6955 slave address are always 110. Slave address bits A3, A2, A1, and A0 are selected by the address input pins AD1 and AD0. These two input pins can be connected to GND, V+, SDA, or SCL. The MAX6955 has 16 possible slave addresses (Table 5) and therefore a maximum of 16 MAX6955 devices can share the same interface.

DISPLAY TYPE

7 SEGMENT

(16-CHARACTER

HEXADECIMAL FONT)

14 SEGMENT/

16 SEGMENT

(104-CHARACTER ASCII FONT MAP)

DISCRETE LEDs

(DIRECT CONTROL)

Monocolor 16 8 128

Bicolor 8 4 64

Table 1. MAX6955 Drive Capability

1dp

2dp

g1 g2

dp dp

1e 1c

2f 2b

2e 2c

g1 g2

Figure 1. Segment Labeling for 7-Segment Display, 14-Segment Display, and 16-Segment Display

MAX6955

2-Wire Interfaced, 2.7V to 5.5V LED Display Driver with I/O Expander and Key Scan

8 _______________________________________________________________________________________

Message Format for Writing

A write to the MAX6955 comprises the transmission of the MAX6955’s slave address with the R/W bit set to zero, followed by at least 1 byte of information. The first byte of information is the command byte, which determines which register of the MAX6955 is to be written by the next byte, if received. If a STOP condition is detected after the command byte is received, then the MAX6955 takes no further action (Figure 7) beyond storing the command byte.

Any bytes received after the command byte are data bytes. The first data byte goes into the internal register of the MAX6955 selected by the command byte (Figure 8).

If multiple data bytes are transmitted before a STOP condition is detected, these bytes are generally stored in subsequent MAX6955 internal registers because the command byte address generally autoincrements (Table 6) (Figure 9).

DIGIT

O18

Table 2. Connection Scheme for Eight 16-Segment Digits

Table 3. Connection Scheme for Eight 14-Segment Digits

DIGIT

O18

0, 0a

2dp

1, 1a

2dp

2, 2a

2dp

3, 3a

2dp

4, 4a

2dp

5, 5a

2dp

6, 6a

2dp

7, 7a

2dp

Table 4. Connection Scheme for Sixteen 7-Segment Digits

O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15 O16 O17

CCO — a1 a2 b c d1 d2 e

— CC1 a1 a2 b c d1 d2 e

a1 a2 CC2 — b c d1 d2 e

a1 a2 — CC3 b c d1 d2 e

a1 a2 b c CC4 — d1 d2 e

a1 a2 b c — CC5 d1 d2 e

a1 a2 b c d1 d2 CC6 — e

a1 a2 b c d1 d2 — CC7 e

DIGIT O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15 O16 O17 O18

0 CCO — a — b c d — e f g1 g2 h i j k l m dp

1 — CC1 a — b c d — e f g1 g2 h i j k l m dp

2 a — CC2 — b c d — e f g1 g2 h i j k l m dp

3 a — — CC3 b c d — e f g1 g2 h i j k l m dp

4 a—b cCC4—d—e fg1g2h i j k l mdp

5 a — b c — CC5 d — e f g1 g2 h i j k l m dp

6 a—b c d—CC6—e fg1g2h i j k l mdp

7 a — b c d — — CC7 e f g1 g2 h i j k l m dp

g1 g2 h

O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15 O16 O17

CC0 — 1a — 1b 1c 1d 1dp 1e 1f 1g 2a 2b 2c 2d 2e 2f 2g

— CC1 1a — 1b 1c 1d 1dp 1e 1f 1g 2a 2b 2c 2d 2e 2f 2g

1a — CC2 — 1b 1c 1d 1dp 1e 1f 1g 2a 2b 2c 2d 2e 2f 2g

1a — — CC3 1b 1c 1d 1dp 1e 1f 1g 2a 2b 2c 2d 2e 2f 2g

1a — 1b 1c CC4 — 1d 1dp 1e 1f 1g 2a 2b 2c 2d 2e 2f 2g

1a — 1b 1c — CC5 1d 1dp 1e 1f 1g 2a 2b 2c 2d 2e 2f 2g

1a—1b1c1d1dpCC6— 1e 1f 1g2a2b2c2d2e2f 2g

1a — 1b 1c 1d 1dp — CC7 1e 1f 1g 2a 2b 2c 2d 2e 2f 2g

MAX6955

2-Wire Interfaced, 2.7V to 5.5V LED Display

Driver with I/O Expander and Key Scan

_______________________________________________________________________________________ 9

SDA

START CONDITION STOP CONDITION

SCL

Figure 3. Start and Stop Conditions

Figure 4. Slave Address

SDA

LOW

BUF

SU, DAT

SU, STA

HD, STA

SU, STO

HD, DAT

HIGH

SCL

START

CONDITION

START

CONDITION

STOP

CONDITION

REPEATED START

CONDITION

HD, STA

Figure 2. 2-Wire Serial Interface Timing Details

SDA

SCL

MSBSTART

A1 A0

LSB

R/W

ACK

MAX6955

2-Wire Interfaced, 2.7V to 5.5V LED Display Driver with I/O Expander and Key Scan

10 ______________________________________________________________________________________

Message Format for Reading

The MAX6955 is read using the MAX6955’s internally stored command byte as address pointer, the same way the stored command byte is used as address pointer for a write. The pointer generally autoincrements after each data byte is read using the same rules as for a write (Table 6). Thus, a read is initiated by first configuring the MAX6955’s command byte by performing a write (Figure 7). The master can now read n consecutive bytes from the MAX6955, with the first data byte being read from the register addressed by the initialized command byte (Figure 9). When performing read-after-write verification, reset the command byte’s address because the stored byte address generally is autoincremented after the write (Table 6).

Operation with Multiple Masters

If the MAX6955 is operated on a 2-wire interface with multiple masters, a master reading the MAX6955 should use a repeated start between the write, which sets the MAX6955’s address pointer, and the read(s) that takes the data from the location(s). This is because it is possible for master 2 to take over the bus after master 1 has set up the MAX6955’s address pointer but before master 1 has read the data. If master 2 subsequently changes the MAX6955’s address pointer, then master 1’s delayed read may be from an unexpected location.

Command Address Autoincrementing

Address autoincrementing allows the MAX6955 to be configured with the shortest number of transmissions by minimizing the number of times the command byte needs to be sent. The command address or the font pointer address stored in the MAX6955 generally increments after each data byte is written or read (Table 6). To utilize the autoincrement read cycle feature, the master clocks SCL after the first data byte is read, and the MAX6955 continues sending data, incrementing the pointer after each byte is sent. A not-acknowledge or stop condition halts autoincrement.

Digit Type Registers

The MAX6955 uses 32 digit registers to store the characters that the user wishes to display. These digit registers are implemented with two planes, P0 and P1. Each digit is represented by 2 bytes of memory, 1 byte in plane P0 and the other in plane P1. The digit registers are mapped so that a digit’s data can be updated in plane P0, plane P1, or both planes at the same time (Table 7).

If the blink function is disabled through the Blink Enable Bit E (Table 20) in the configuration register, then the digit register data in plane P0 is used to multiplex the display. The digit register data in P1 is not used. If the blink function is enabled, then the digit register data in both plane P0 and plane P1 are alternately used to multiplex the display. Blinking is achieved by multiplexing the LED display using data plane P0 and plane P1 on alternate phases of the blink clock (Table 21).

COMMAND BYTE

ADDRESS RANGE

AUTOINCREMENT BEHAVIOR

x0000000 to x0001100 Command byte address autoincrements after byte read or written.

x0001101 Factory reserved; do not write this register.

x0001111 to x1111110 Command byte address autoincrements after byte read or written.

x1111111 Command byte address remains at x1111111 after byte read or written.

Table 5. MAX6955 Address Map

Table 6. Command Address Autoincrement Rules

PIN CONNECTION

DEVICE ADDRESS

AD1

GND

GND V+

GND

V+

V+ V+

V+

SDA

SDA V+

SDA

SCL

SCL V+

SCL

AD0 A6A5A4A3A2A1

GND110000

110000

SDA110001

SCL 110001

GND110010

110010

SDA110011

SCL 110011

GND110100

110100

SDA110101

SCL 110101

GND110110

110110

SDA110111

SCL 110111

MAX6955

2-Wire Interfaced, 2.7V to 5.5V LED Display

Driver with I/O Expander and Key Scan

______________________________________________________________________________________ 11

The data in the digit registers does not control the digit segments directly for 14- and 16-segment displays. Instead, the register data is used to address a character generator that stores the data for the 14- and 16segment fonts (Tables 8 and 9). The lower 7 bits of the digit data (D6 to D0) select the character from the font. The most significant bit of the register data (D7) controls the DP segment of the digits; it is set to 1 to light DP, and to zero to leave DP unlit (Table 10).

For 7-segment displays, the digit plane data register can be used to address a character generator, which contains the data of a 16-character font containing the hexadecimal font. The decode mode register can be used to disable the character generator and allow the segments to be controlled directly. Table 11 shows the one-to-one pairing of each data bit to the appropriate segment line in the digit plane data registers. The hexadecimal font is decoded according to Table 12.

The digit-type register configures the display driver for various combinations of 14-segment digits, 16-segment digits, and/or pairs, or 7-segment digits. The function of this register is to select the appropriate font for each digit and route the output of the font to the appropriate MAX6955 driver output pins. The MAX6955 has four digit drive slots. A slot can be filled with various combinations of monocolor and bicolor 16-segment displays, 14-segment displays, or two 7-segment displays. Each pair of bits in the register corresponds to one of the four digit drive slots, as shown in Table 13. Each bit also corresponds to one of the eight common-cathode digit drive outputs, CC0 to CC7. When using bicolor digits, the anode connections for the two digits within a slot are always the same. This means that a slot correctly drives two monocolor or one bicolor 14- or 16-segment digit. The digit type register can be written, but cannot be read. Examples of configuration settings required for some display digit combinations are shown in Table 14.

7-Segment Decode-Mode Register

In 7-segment mode, the hexadecimal font can be disabled (Table 15). The decode-mode register selects between hexadecimal code or direct control for each of eight possible pairs of 7-segment digits. Each bit in the register corresponds to one pair of digits. The digit pairs are {digit 0, digit 0a} through {digit 7, digit 7a}. Disabling decode mode allows direct control of the 16 LEDs of a dual 7-segment display. Direct control mode can also be used to drive a matrix of 128 discrete LEDs.

A logic high selects hexadecimal decoding, while a logic low bypasses the decoder. When direct control is selected, the data bits D7 to D0 correspond to the segment lines of the MAX6955. Write x0010000 to blank all segments in hexadecimal decode mode.

Display Blink Mode

The display blinking facility, when enabled, makes the driver flip automatically between displaying the digit register data in planes P0 and P1. If the digit register data for any digit is different in the two planes, then that digit appears to flip between two characters. To make a character appear to blink on or off, write the character to one plane, and use the blank character (0x20) for the other plane. Once blinking has been configured, it continues automatically without further intervention.

Blink Speed

The blink speed is determined by the frequency of the multiplex clock, OSC, and by the setting of the Blink Rate Selection Bit B (Table 19) in the configuration register. The Blink Rate Selection Bit B sets either fast or slow blink speed for the whole display.

Initial Power-Up

On initial power-up, all control registers are reset, the display is blanked, intensities are set to minimum, and shutdown is enabled (Table 16).

Configuration Register

The configuration register is used to enter and exit shutdown, select the blink rate, globally enable and disable the blink function, globally clear the digit data, select between global or digit-by-digit control of intensity, and reset the blink timing (Tables 17–20 and 22–25).

The configuration register contains 7 bits:

• S bit selects shutdown or normal operation (read/write).

• B bit selects the blink rate (read/write).

• E bit globally enables or disables the blink function (read/write).

• T bit resets the blink timing (data is not stored—transient bit).

• R bit globally clears the digit data for both planes P0 and P1 for ALL digits (data is not stored—transient bit).

• I bit selects between global or digit-by-digit control of intensity (read/write).

• P bit returns the current phase of the blink timing (read only—a write to this bit is ignored).

Character Generator Font Mapping

The font is composed of 104 characters in ROM. The lower 7 bits of the 8-bit digit register represent the character selection. The most significant bit, shown as x in the ROM map of Tables 8 and 9, is 1 to light the DP segment and zero to leave the DP segment unlit.

The character map follows the standard ASCII font for 96 characters in the x0101000 through x1111111

MAX6955

2-Wire Interfaced, 2.7V to 5.5V LED Display Driver with I/O Expander and Key Scan

12 ______________________________________________________________________________________

range. The first 16 characters of the 16-segment ROM map cover 7-segment displays. These 16 characters are numeric 0 to 9 and characters A to F (i.e., the hexadecimal set).

Multiplex Clock and Blink Timing

The OSC pin can be fitted with capacitor C

SET

to GND to use the internal RC multiplex oscillator, or driven by an external clock to set the multiplex clock frequency and blink rate. The multiplex clock frequency determines the frequency that the complete display is updated. With OSC at 4MHz, each display digit is enabled for 200µs.

The internal RC oscillator uses an external resistor, R

SET

, and an external capacitor, C

SET

, to set the oscil-

lator frequency. The suggested values of R

SET

(56kΩ)

and C

SET

(22pF) set the oscillator at 4MHz, which

makes the blink frequency 0.5Hz or 1Hz.

The external clock is not required to have a 50:50 duty cycle, but the minimum time between transitions must be 50ns or greater and the maximum time between transitions must be 750ns.

The on-chip oscillator may be accurate enough for applications using a single device. If an exact blink rate is required, use an external clock ranging between 1MHz and 8MHz to drive OSC. The OSC inputs of multiple MAX6955s can be connected to a common external clock to make the devices blink at the same rate. The relative blink phasing of multiple MAX6955s can be synchronized by setting the T bit in the control register for all the devices in quick succession. If the serial interfaces of multiple MAX6955s are daisy-chained by connecting the DOUT of one device to the DIN of the next, then synchronization is achieved automatically by updating the configuration register for all devices simultaneously. Figure 10 is the multiplex timing diagram.

OSC_OUT Output

The OSC_OUT output is a buffered copy of either the internal oscillator clock or the clock driven into the OSC pin if the external clock has been selected. The feature is useful if the internal oscillator is used, and the user wishes to synchronize other MAX6955s to the same blink frequency. The oscillator is disabled while the MAX6955 is in shutdown.

Scan-Limit Register

The scan-limit register sets how many 14-segment digits or 16-segment digits or pairs of 7-segment digits are displayed, from 1 to 8. A bicolor digit is connected as two monocolor digits. The scan register also limits the number of keys that can be scanned.

Since the number of scanned digits affects the display brightness, the scan-limit register should not be used to

blank portions of the display (such as leading-zero suppression). Table 26 shows the scan-limit register format.

Intensity Registers

Digital control of display brightness is provided and can be managed in one of two ways: globally or individually. Global control adjusts all digits together. Individual control adjusts the digits separately.

The default method is global brightness control, which is selected by clearing the global intensity bit (I data bit D6) in the configuration register. This brightness setting applies to all display digits. The pulse-width modulator is then set by the lower nibble of the global intensity register, address 0x02. The modulator scales the average segment current in 16 steps from a maximum of 15/16 down to 1/16 of the peak current. The minimum interdigit blanking time is set to 1/16 of a cycle. When using bicolor digits, 256 color/brightness combinations are available.

Individual brightness control is selected by setting the global intensity bit (I data bit D6) in the configuration register. The pulse-width modulator is now no longer set by the lower nibble of the global intensity register, address 0x02, and the data is ignored. Individual digital control of display brightness is now provided by a separate pulse-width modulator setting for each digit. Each digit is controlled by a nibble of one of the four intensity registers: intensity10, intensity32, intensity54, and intensity76 for all display types, plus intensity10a, intensity32a, intensity54a, and intensity76a for the extra eight digits possible when 7-segment displays are used. The data from the relevant register is used for each digit as it is multiplexed. The modulator scales the average segment current in 16 steps in exactly the same way as global intensity adjustment.

Table 27 shows the global intensity register format. Table 28 shows individual segment intensity registers. Table 29 shows the even individual segment intensity format. Table 30 shows the odd individual segment intensity format.

GPIO and Key Scanning

The MAX6955 features five general-purpose input/output (GPIO) ports: P0 to P4. These ports can be individually enabled as logic inputs or open-drain logic outputs. The GPIO ports are not debounced when configured as inputs. The ports can be read and the outputs set using the 2-wire interface.

Some or all of the five ports can be configured to perform key scanning of up to 32 keys. Ports P0 to P4 are renamed Key_A, Key_B, Key_C, Key_D, and IRQ, respectively, when used for key scanning. The full keyscanning configuration is shown in Figure 11. Table 31 is the GPIO data register.

MAX6955

2-Wire Interfaced, 2.7V to 5.5V LED Display

Driver with I/O Expander and Key Scan

______________________________________________________________________________________ 13

ADDRESS (COMMAND BYTE)

HEX CODE

No-Op X 0 0 0 0 0 0 0 0x00

Decode Mode X 0 0 0 0 0 0 1 0x01

Global Intensity X 0 0 0 0 0 1 0 0x02

Scan Limit X 0 0 0 0 0 1 1 0x03

Configuration X 0 0 0 0 1 0 0 0x04

GPIO Data X 0 0 0 0 1 0 1 0x05

Port Configuration X 0 0 0 0 1 1 0 0x06

Display Test X 0 0 0 0 1 1 1 0x07

Write KEY_A Mask Read KEY_A Debounce

X 0 0 0 1 0 0 0 0x08

Write KEY_B Mask Read KEY_B Debounce

X 0 0 0 1 0 0 1 0x09

Write KEY_C Mask Read KEY_C Debounce

X 0 0 0 1 0 1 0 0x0A

Write KEY_D Mask Read KEY_D Debounce

X 0 0 0 1 0 1 1 0x0B

Write Digit Type Read KEY_A Pressed

X 0 0 0 1 1 0 0 0x0C

Read KEY_B Pressed* X 0 0 0 1 1 0 1 0x0D Read KEY_C Pressed* X 0 0 0 1 1 1 0 0x0E Read KEY_D Pressed* X 0 0 0 1 1 1 1 0x0F Intensity 10 X 0 0 1 0 0 0 0 0x10 Intensity 32 X 0 0 1 0 0 0 1 0x11 Intensity 54 X 0 0 1 0 0 1 0 0x12 Intensity 76 X 0 0 1 0 0 1 1 0x13 Intensity 10a (7 Segment Only) X 0 0 1 0 1 0 0 0x14 Intensity 32a (7 Segment Only) X 0 0 1 0 1 0 1 0x15 Intensity 54a (7 Segment Only) X 0 0 1 0 1 1 0 0x16 Intensity 76a (7 Segment Only) X 0 0 1 0 1 1 1 0x17 Digit 0 Plane P0 X 0 1 0 0 0 0 0 0x20 Digit 1 Plane P0 X 0 1 0 0 0 0 1 0x21 Digit 2 Plane P0 X 0 1 0 0 0 1 0 0x22 Digit 3 Plane P0 X 0 1 0 0 0 1 1 0x23 Digit 4 Plane P0 X 0 1 0 0 1 0 0 0x24 Digit 5 Plane P0 X 0 1 0 0 1 0 1 0x25 Digit 6 Plane P0 X 0 1 0 0 1 1 0 0x26 Digit 7 Plane P0 X 0 1 0 0 1 1 1 0x27 Digit 0a Plane P0 (7 Segment Only) X 0 1 0 1 0 0 0 0x28 Digit 1a Plane P0 (7 Segment Only) X 0 1 0 1 0 0 1 0x29 Digit 2a Plane P0 (7 Segment Only) X 0 1 0 1 0 1 0 0x2A Digit 3a Plane P0 (7 Segment Only) X 0 1 0 1 0 1 1 0x2B

Table 7. Register Address Map

*Do NOT write to register.

D15 D14 D13 D12 D11 D10 D9 D8

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