The MAX6950/MAX6951 are compact common-cathode
display drivers that interface microprocessors to individual 7-segment numeric LED digits, bar graph, or discrete
LEDs through an SPI™-, QSPI™-, MICROWIRE™-compatible serial interface. The supply voltage can be as low
as 2.7V.
The MAX6950 drives up to five 7-segment digits or 40
discrete LEDs. The MAX6951 drives up to eight 7-segment digits or 64 discrete LEDs.
Included on-chip are hexadecimal character decoders
(0–9, A–F), multiplex scan circuitry, segment and digit
drivers, and a static RAM that stores each digit. The
user may select hexadecimal decoding or no-decode
for each digit to allow any mix of 7-segment digits, bar
graph, or discrete LEDs to be driven. The segment current for the LEDs is set by an internal digital brightness
control. The segment drivers are slew-rate limited to
reduce EMI.
Individual digits may be addressed and updated without rewriting the entire display. The devices include a
low-power shutdown mode, digital brightness control, a
scan-limit register that allows the user to display from
one to eight digits, segment blinking that can be synchronized across drivers, and a test mode that forces
all LEDs on.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage (with Respect to GND)
V+………………………………. ...................................-0.3V to 6V
All Other Pins................................................-0.3V to (V+ + 0.3V)
(Typical operating circuit, scan limit set to eight digits, V+ = +3.3V, V
LED
= 2.4V, TA = +25°C, unless otherwise noted.)
INTERNAL OSCILLATOR FREQUENCY
vs. TEMPERATURE
4.40
4.30
4.20
4.10
4.00
3.90
3.80
OSCILLATOR FREQUENCY (MHz)
3.70
3.60
-40020-20
V+ = 2.7V
V+ = 3.3V
V+ = 5V
40
TEMPERATURE (°C)
INTERNAL OSCILLATOR WAVEFORM
AT OSC (PIN 9)
3.0
2.5
2.0
1.5
VOLTAGE AT OSC (V)
1.0
0.5
0
0400200600800
TIMELINE (ns)
6080
MAX6950/1 toc01
MAX6950/1 toc03
INTERNAL OSCILLATOR FREQUENCY
vs. SUPPLY VOLTAGE
4.40
4.30
4.20
4.10
4.00
3.90
3.80
OSCILLATOR FREQUENCY (MHz)
3.70
3.60
23456
SUPPLY VOLTAGE (V)
DEAD CLOCK OSCILLATOR FREQUENCY
vs. SUPPLY VOLTAGE
80
79
78
77
76
75
74
73
OSCILLATOR FREQUENCY (kHz)
72
71
70
2.03.0 3.52.54.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V)
MAX6950/1 toc02
MAX6950/1 toc04
SEGMENT SOURCE CURRENT
vs. SUPPLY VOLTAGE
1.01
1.00
0.99
0.98
0.97
CURRENT NORMALIZED TO 40mA
0.96
0.95
2.03.02.53.5 4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V)
MAX6950/1 toc05
WAVEFORM AT SEGO/DIGO (PIN 6)
V+ = 3.3V, 8 DIGITS SCANNED, 8/16 INTENSITY
3.5
3.0
2.5
2.0
1.5
VOLTAGE (V)
1.0
0.5
0
DIGIT 0 MULTIPLEX TIMESLOT
0500100015002000
TIMELINE (ns)
MAX6950/1 toc06
Detailed Description
Differences Between
MAX6950 and MAX6951
The MAX6950 is a five-digit common-cathode display
driver. It drives five digits, with each digit comprising
eight LEDs with cathodes connected to a common
cathode. The display limit is therefore 40 LEDs or digit
segments.
The MAX6951 is an eight-digit common-cathode display driver. It drives eight digits, with each digit comprising eight LEDs. The only difference between the
MAX6950 and MAX6951 is that the MAX6950 is missing
three digit drivers. The MAX6950 can be configured to
scan eight digits, but if the last three digits are wired
up, they do not light.
The MAX6950/MAX6951 use a unique multiplexing
scheme to minimize the connections between the driver
and LED display. The scheme requires that the segment connections are different to each of the five
(MAX6950) or eight (MAX6951) digits (Table 1). This is
shown in the Typical Application Circuit, which uses
single-digit type displays. The MAX6950/MAX6951 are
not intended to drive multidigit display types, which
have the segments internally wired together, unless the
segments are wired with the common cathodes to follow Table 1. The MAX6950/MAX6951 can drive multidigit LED displays that have the segments individually
pinned for each digit because then the digits can be
connected together correctly externally, just as if individual digits were used.
Serial-Addressing Modes
The microprocessor interface on the MAX6950/
MAX6951 is a SPI-compatible 3-wire serial interface
using three input pins (Figure 1). This interface is used
to write configuration and display data to the MAX6950/
MAX6951. The serial interface data word length is 16
bits, which are labeled D15–D0 (Table 2). D15–D8 contain the command address, and D7–D0 contain the
data. The first bit received is D15, the most-significant
bit (MSB). The three input pins are:
•CLK is the serial clock input, and may idle low or
high at the start and end of a write sequence.
•CS is the MAX6950/MAX6951s’ chip-select input,
and must be low to clock data into the MAX6950/
MAX6951.
•DIN is the serial data input, and must be stable
when it is sampled on the rising edge of the clock.
1DINSerial Data Input. Data is loaded into the internal 16–bit Shift register on CLK’s rising edge.
2CLK
3–6, 10–14DIGX, SEGX
7I
8GNDGround
9OSC
15CS
16V+Positive Supply Voltage. Bypass to GND with a 0.1µF capacitor.
PADE xposed p adExposed pad on package underside. Connect to GND.
SET
Serial-Clock Input. On CLK’s rising edge, data is shifted into the Internal Shift register. On CLK’s
falling edge, data is clocked out of DOUT. CLK input is active only while CS is low.
Digit X outputs sink current from the display common cathode when acting as digit drivers.
Segment X drivers source current to the display. Segment/digit drivers are high impedance when
turned off.
Current Setting. Connect to GND through a resistor (R
together with capacitor C
Multiplexer Clock Input. A capacitor (C
multiplex clock is used. Resistor R
together set the multiplex clock frequency. When the external clock is used, OSC should be driven
by a 1MHz to 8MHz clock.
Chip-Select Input. Serial data is loaded into the Shift register while CS is low. The last 16 bits of
serial data are latched on CS’s rising edge.
, also sets the multiplex clock frequency.
SET
) is connected to GND when the internal RC oscillator
SET
(also used to set the peak current) and capacitor C
SET
) to set the peak current. This resistor,
SET
SET
MAX6950/MAX6951
The serial interface comprises a 16-bit shift register into
which DIN data is clocked on the rising edge of CLK
when CS is low. When CS is high, transitions on CLK do
not clock data into the shift register. When CS goes
high, the 16 bits in the shift register are parallel loaded
into a 16-bit latch. The 16 bits in the latch are then
decoded to determine and execute the command.
The MAX6950/MAX6951 are written to using the following sequence (Figure 2):
1) Take CLK low.
2) Take CS low. This enables the internal 16-bit shift
register.
3) Clock 16 bits of data in order, D15 first to D0 last,
into DIN, observing the setup and hold times.
4) Take CS high.
CLK and DIN may well be used to transmit data to other
peripherals. The MAX6950/MAX6951 ignore all activity
on CLK and DIN except when CS is low. Data cannot
be read from the MAX6950/MAX6951.
If fewer or greater than 16 bits are clocked into the
MAX6950/MAX6951 between taking CS low and taking
CS high again, the MAX6950/MAX6951 store the last 16
bits received, including the previous transmission(s).
The general case is when n bits (where n > 16) are
transmitted to the MAX6950/MAX6951. The last bits
comprising bits {n-15} to {n} are retained and are parallel loaded into the 16-bit latch as bits D15 to D0,
respectively (Figure 3).
Digit and Control Registers
Table 3 lists the addressable Digit and Configuration
registers. The digit registers are implemented by two
planes of 8-byte dual-port SRAM, P0 and P1.
Initial Power-Up
On initial power-up, all control registers are reset, the
display is blanked, and the MAX6950/MAX6951 enter
shutdown mode. Program the display driver prior to display use. Otherwise, it is initially set to scan five digits, it
does not decode data in the data registers, and the
Intensity register is set to its minimum value. Table 4
lists the register status after power-up.
Configuration Register
The configuration register is used to enter and exit shutdown, select the blink rate, globally enable and disable
the blink function, globally clear the digit data, and
reset the blink timing. Bit position D1 should always be
written with a zero when the configuration register is
updated. See Table 5 for configuration register format.
The S bit selects shutdown or normal operation.
The B bit selects the blink rate.
The E bit globally enables or disables the blink function.
The T bit resets the blink timing.
The R bit globally clears the digit data for both planes
P0 and P1 for all digits.
When the MAX6950/MAX6951 are in shutdown mode
(Table 6), the scan oscillator is halted; all segment and
digit drivers are high impedance. Data in the digit and
Serially Interfaced, +2.7V to +5.5V,
5- and 8-Digit LED Display Drivers