The MAX6620 controls the speeds of up to four fans
using four independent linear voltage outputs. The
drive voltages for the fans are controlled directly over
the I
2
C interface. Each output drives the base of an
external bipolar transistor or the gate of a FET in highside drive configuration. Voltage feedback at the fan’s
power-supply terminal is used to force the correct output voltage.
The MAX6620 offers two methods for fan control. In
RPM mode, the MAX6620 monitors four fan tachometer
logic outputs for precise (±1%) control of fan RPM and
detection of fan failure. In DAC mode, each fan is driven with a voltage resolution of 9 bits and the tachometer outputs of the fans are monitored for failure.
The DAC_START input selects the fan power-supply
voltage at startup to ensure appropriate fan drive when
power is first applied. A watchdog feature turns the
fans fully on to protect the system if there are no valid
I
2
C communications within a preset timeout period.
The MAX6620 operates from a 3.0V to 5.5V power supply with low 250µA supply current, and the I
2
C-compatible interface makes it ideal for fan control in a wide
range of cooling applications. The MAX6620 is available in a 28-pin TQFN package and operates over the
-40°C to +125°C automotive temperature range.
Applications
Consumer Products
Servers
Communications Equipment
Storage Equipment
Features
♦ Controls Up to Four Independent Fans With
Linear (DC) Drive
♦ Uses Four External Low-Cost Pass Transistors
♦ 1% Accuracy Precision RPM Control
♦ Controlled Voltage Rate-Of-Change for Best
Acoustics
♦ I
2
C Bus Interface
♦ 3.0V to 5.5V Supply Voltage Range
♦ 250µA (typ) Operating Supply Current
♦ 3µA (typ) Shutdown Supply Current
♦ Small 5mm x 5mm Footprint
(TA= -40°C to +125°C, VCC= 3.0V to 5.5V, unless otherwise noted. Typical values are at TA= +25°C, VCC= 3.3V.) (Note 3)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCC to GND ..........................................................-0.3V to +6.0V
FAN_FAIL, SDA, SCL to GND ...............................-0.3V to +6.0V
ADDR, SPINUP_START, DAC_START, WD_START,
X1, X2 to GND ........................................-0.3V to (V
CC
+ 0.3V)
All Other Pins to GND..........................................-0.3V to +13.5V
Input Current at DACOUT_ Pins (Note 1) ...............+5mA/-50mA
Input Current at Any Pin (Note 1)..........................................5mA
ESD Protection (all pins, Human Body Model) (Note 2) ...±2000V
(TA= -40°C to +125°C, VCC= 3.0V to 5.5V, unless otherwise noted. Typical values are at TA= +25°C, VCC= 3.3V.) (Note 3)
Note 3: All parts will operate properly over the VCCsupply voltage range of 3.0V to 5.5V.
Note 4: Guaranteed by design and characterization.
Note 5: All timing specifications are guaranteed by design.
Note 6: A master device must provide a hold time of at least 300ns for the SDA signal to bridge the undefined region of SCL’s falling edge.
Note 7: C
B
= total capacitance of one bus line in pF. Tested with CB= 400pF.
Note 8: Input filters on SDA and SCL suppress noise spikes less than 50ns.
Note 9: Holding the SDA line low for a time greater than t
TIMEOUT
will cause the devices to reset SDA to the idle state of the serial
1SCLI2C Serial-Clock Input. Can be pulled up to 5.5V regardless of VCC. Open circuit when VCC = 0V.
2SDA
3WD_START
4, 10, 11, 18,
25
5ADDR
6DAC_START
7S P IN U P _S TART
8, 9X1, X2
12, 17, 19, 24
13, 16, 20, 23
14, 15, 21, 22 TACH4–TACH1 Fan Tachometer Logic Inputs. These inputs accept input voltages up to V
26FAN
27VCCPower-Supply Input. 3.3V nominal. Bypass VCC to GND with a 0.1µF capacitor.
28FAN_FAIL
—EP
GNDGround
DACOUT4–
DACOUT1
DACFB4–
DACFB1
Open-Drain, I
circuit when V
Startup Watchdog Set Input. This input is sampled when power is first applied and sets the initial
2
C watchdog behavior. When connected to GND, the watchdog function is disabled. When
I
connected to V
fan drive goes to 100%.
2
C Address Set Input. This input is sampled when power is first applied and sets the I2C slave
I
address. When connected to GND, the slave address will be 0x50. When unconnected, the slave
address will be 0x52. When connected to V
Startup Fan Drive DAC Set Input. This input is sampled when power is first applied and sets the
power-up value for the fan drive voltage. When connected to GND, the fan drive voltage will be
0%. When unconnected, the fan drive voltage will be 75%. When connected to V
voltage will be 100%.
Startup Spin-Up Set Input. This input is sampled when power is first applied and sets the initial
spin-up behavior. When connected to GND, spin-up is disabled. When connected to V
power-up, the fan is driven with a full-scale drive voltage until two tachometer pulses have been
detected, or 1s has elapsed. When unconnected, the fan is driven with a full-scale drive voltage
until two tachometer pulses have been detected, or 0.5s has elapsed. Spin-up behavior may be
modified by writing appropriate settings to the MAX6620’s registers.
Crystal Oscillator Inputs. Connections for a standard 32.768kHz quartz crystal. The internal
oscillator circuitry is designed for operation with a crystal having a specified load capacitance
(CL) of 12pF. Connect an external 32.768kHz oscillator across X1 and X2 for operation with the
external oscillator. If no crystal or external oscillator is connected, the MAX6620 will use its
internal oscillator.
Fan Drive DAC Outputs. Connect to the gate of a p-channel MOSFET or base of a PNP bipolar
transistor.
D AC Feed b ack Inp uts. C onnect a 0.1µF cap aci tor b etw een these p i ns and GN D . C onnect to the
sup p l y p i n of the fan and to the d r ai n of a p - channel M O S FE T or col l ector of a P N P b i p ol ar tr ansi stor .
Fan Power-Supply Voltage Input. Connect to the fan power supply (V
capacitor to GND.
Active-Low, Open-Drain Fan Failure Output. Active only when fault is present; open-circuit when
= 0V. This pin can be pulled up to 5.5V regardless of VCC.
V
CC
Exposed Paddle. Internally connected to GND. Connect to a large ground plane to maximize
thermal performance. Not intended as an electrical connection point.
2
C Serial-Data Input/Output. Can be pulled up to 5.5V regardless of VCC. Open
= 0V.
CC
, the MAX6620 monitors SDA. If 10s elapse without a valid I2C transaction, the
Slave Address: equivalent to chip-select line of
a 3-wire interface
Command Byte: selects which
register you are writing to
Data Byte: data goes into the register
set by the command byte (to set
thresholds, configuration masks, and
sampling rate)
Slave Address: equivalent to chip-select line
Command Byte: selects
which register you are
reading from
Slave Address: repeated
due to change in dataflow direction
Data Byte: reads from
the register set by the
command byte
Command Byte: sends command with no data, usually
used for one-shot command
Data Byte: reads data from
the register commanded
by the last read byte or
write byte transmission;
also used for SMBus alert
response return address
S = START CONDITIONSHADED = SLAVE TRANSMISSION
P = STOP CONDITIONA = NOT ACKNOWLEDGED
Figure 2. I2C Protocols
SADDRESSRDADATA
A
P
7 bits8 bits
WRSACOMMANDAP
8 bits
ADDRESS
7 bits
P
1
ADATA
8 bits
ACOMMAND
8 bits
AWRADDRESS
7 bits
S
SADDRESSWRACOMMANDASADDRESS
7 bits8 bits7 bits
RDADATA
8 bits
A
P
Detailed Description
The MAX6620 controls the speeds of up to four fans
using four independent linear voltage outputs. The
drive voltages for the fans are controlled directly over
the I
2
C interface. Each of the outputs (DACOUT1–
DACOUT4) drive the base of an external PNP or the
gate of a p-channel MOSFET. Voltage feedback at the
fan’s power-supply terminal is used to force the output
voltage.
The MAX6620 monitors fan tachometer logic outputs for
precise (1%) control of fan RPM and detection of fan
failure. When the MAX6620 is used with 2-wire fans,
these inputs are not used, and the fans can be driven
to the desired voltage without using tachometer feedback.
Three inputs set the fan drive status on application of
power. The DAC_START input selects the fan-supply
voltage (100%, 75%, or 0%) at startup to ensure appropriate fan drive when power is first applied. The
SPIN_START input selects whether spin-up will be
applied to the fans at power-up. WD_START selects
whether lack of I
2
C activity will force the fans to full
speed. When the watchdog function is enabled, the
fans will be driven to full speed if there is no I2C activity
for a period of 2s, 6s, or 10s.
Digital Interface
The MAX6620 features an I2C-compatible, 2-wire serial
interface consisting of a bidirectional serial data line
(SDA) and a serial clock line (SCL). SDA and SCL facilitate bidirectional communication between the MAX6620
and the master at rates up to 400kHz. The master (typically a microcontroller) initiates data transfer on the bus
and generates SCL. SDA and SCL require 4.7kΩ (typ)
pullup resistors.
Bit Transfer
One data bit is transferred during each SCL clock
cycle. Nine clock cycles are required to transfer the
data into or out of the MAX6620. The data on SDA must
remain stable during the high period of the SCL clock
pulse, as changes in SDA while SCL is high are control
signals (see the
The master initiates a transmission with a START condition (S), a high-to-low transition on SDA with SCL high.
The master terminates a transmission with a STOP condition (P), a low-to-high transition on SDA while SCL is high
(Figure 3). The STOP condition frees the bus and places
all devices in F/S mode (Figure 1). Use a repeated
START condition (Sr) in place of a STOP condition to
leave the bus active and in its current timing mode.
Acknowledge Bits
Successful data transfers are acknowledged with an
acknowledge bit (A) or a not-acknowledge bit (A). Both
the master and the MAX6620 (slave) generate acknowl-
edge bits. To generate an acknowledge, the receiving
device must pull SDA low before the rising edge of the
acknowledge-related clock pulse (9th pulse), and keep it
low during the high period of the clock pulse (Figure 4).
To generate a not acknowledge, the receiver allows
SDA to be pulled high before the rising edge of the
acknowledge-related clock pulse, and leaves it high
during the high period of the clock pulse. Monitoring
the acknowledge bits allows for detection of unsuccessful data transfers. An unsuccessful data transfer
happens if a receiving device is busy or if a system
fault has occurred. In the event of an unsuccessful data
transfer, the master should reattempt communication at
a later time.
A = START CONDITION
B = MSB OF ADDRESS CLOCKED INTO SLAVE
C = LSB OF ADDRESS CLOCKED INTO SLAVE
D = R/W BIT CLOCKED INTO SLAVE
E = SLAVE PULLS SMBDATA LINE LOW
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER
G = MSB OF DATA CLOCKED INTO SLAVE
H = LSB OF DATA CLOCKED INTO SLAVE
I = MASTER PULLS DATA LINE LOW
J = ACKNOWLEDGE CLOCKED INTO SLAVE
K = ACKNOWLEDGE CLOCK PULSE
L = STOP CONDITION
M = NEW START CONDITION
SCL
AB CDEFG HIJ
K
SDA
t
SU:STA
t
HD:STA
t
LOWtHIGH
t
SU:DAT
t
HD:DAT
t
SU:STO
t
BUF
L
M
Figure 3. I2C Write Timing Diagram
A = START CONDITION
B = MSB OF ADDRESS CLOCKED INTO SLAVE
C = LSB OF ADDRESS CLOCKED INTO SLAVE
D = R/W BIT CLOCKED INTO SLAVE
E = SLAVE PULLS SMBDATA LINE LOW
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER
G = MSB OF DATA CLOCKED INTO MASTER
H = LSB OF DATA CLOCKED INTO MASTER
I = MASTER PULLS DATA LINE LOW
J = ACKNOWLEDGE CLOCKED INTO SLAVE
K = ACKNOWLEDGE CLOCK PULSE
L = STOP CONDITION
M = NEW START CONDITION
SCL
ABCDEFG
HIJ
SDA
t
SU:STAtHD:STA
t
LOW
t
HIGH
t
SU:DAT
t
SU:STOtBUF
LMK
Figure 4. I2C Read Timing Diagram
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