The MAX6301/MAX6302/MAX6303/MAX6304* lowpower microprocessor (µP) supervisory circuits provide
maximum adjustability for reset and watchdog functions.
The reset threshold can be adjusted to any voltage
above 1.22V, using external resistors. In addition, the
reset and watchdog timeout periods are adjustable
using external capacitors. A watchdog select pin
extends the watchdog timeout period to 500x. The reset
function features immunity to power-supply transients.
These four devices differ only in the structure of their reset
outputs (see
Selector Guide
). The MAX6301–MAX6304
are available in the space-saving 8-pin µMAX package,
as well as 8-pin DIP/SO.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
CC
CC
+ 0.3V)
+ 0.3V)
ELECTRICAL CHARACTERISTICS
(VCC= +2V to +5.5V, TA= T
MIN
to T
, unless otherwise noted. Typical values are at VCC= +5V and TA= +25°C.)
MAX
MAX6301–MAX6304
Operating Voltage Range
(Note 1)
Supply Current (Note 2)
RESET TIMER
Reset Input Threshold Voltage
Reset Input Hysteresis
Reset Input Leakage Current
Reset Output Voltage High
(MAX6302/MAX6303/MAX6304)
Reset Output Voltage Low
(MAX6301/MAX6303/MAX6304)
Reset Input. High-impedance input to the reset comparator. Connect this pin to the center point of an
RESET IN
external resistor voltage-divider network to set the reset threshold voltage. The reset threshold voltage
is calculated as follows: V
Set Reset-Timeout Input. Connect a capacitor between this input and ground to select the reset timeout
period (tRS). Determine the period as follows: tRP= 2.67 x C
Typical Operating Circuit
Set Watchdog-Timeout Input. Connect a capacitor between this input and ground to select the basic
watchdog timeout period (tWD). Determine the period as follows: tWD= 2.67 x C
and tWDin µs. The watchdog function can be disabled by connecting this pin to ground.
Watchdog-Select Input. This input selects the watchdog mode. Connect to ground to select normal mode
and the basic watchdog timeout period. Connect to VCCto select extended mode, multiplying the basic
timeout period by a factor of 500. A change in the state of this pin resets the watchdog timer to zero.
Watchdog Input. A rising or falling transition must occur on this input within the selected watchdog
timeout period, or a reset pulse will occur. The capacitor value selected for SWT and the state of WDS
determine the watchdog timeout period. The watchdog timer clears and restarts when a transition
occurs on WDI or WDS. The watchdog timer is cleared when reset is asserted and restarted after reset
deasserts. In the extended watchdog mode (WDS = VCC), the watchdog function can be disabled by
driving WDI with a three-stated driver or by leaving WDI unconnected.
= 1.22 x (R1 + R2) / R2 (see
RST
).
Typical Operating Circuit
SRT
, with C
in pF and tRPin µs (see
SRT
SWT
).
, with C
SWT
in pF
MAX6301–MAX6304
7
8
RESET
(MAX6301/3)
RESET
(MAX6302/4)
V
CC
Open-Drain, Active-Low Reset
Output (MAX6301)
Push/Pull, Active-Low Reset
Output (MAX6303)
Open-Drain, Active-High Reset
Output (MAX6302)
Push/Pull, Active-High Reset
Output (MAX6304)
Supply Voltage
RESET changes from high to low whenever the monitored voltage
) drops below the selected reset threshold (V
(V
IN
remains low as long as V
RESET remains low for the reset timeout period and then goes high.
The watchdog timer triggers a reset pulse (t
dog timeout period (tWD) is exceeded.
RESET changes from low to high whenever the monitored voltage
(VIN) drops below the selected reset threshold (V
remains high as long as VINis below V
RESET remains high for the reset timeout period and then goes low.
The watchdog timer triggers a reset pulse (tRP) whenever the watchdog timeout period (tWD) is exceeded.
+5V, Low-Power µP Supervisory Circuits
with Adjustable Reset/Watchdog
_______________Detailed Description
Reset Function/Output
The reset output is typically connected to the reset
input of a microprocessor (µP). A µP’s reset input starts
or restarts the µP in a known state. The MAX6301–
MAX6304 µP supervisory circuits provide the reset
logic to prevent code-execution errors during powerup, power-down, and brownout conditions (see
Operating Circuit
For the MAX6301/MAX6303, RESET changes from high
to low whenever the monitored voltage (VIN) drops
below the reset threshold voltage (V
remains low as long as VINis below V
exceeds V
period, then goes high. When a reset is asserted due to
a watchdog timeout condition, RESET stays low for the
reset timeout period. Anytime reset asserts, the watchdog timer clears. At the end of the reset timeout period,
MAX6301–MAX6304
RESET goes high and the watchdog timer is restarted
from zero. If the watchdog timeout period is exceeded
again, then RESET goes low again. This cycle continues unless WDI receives a transition.
On power-up, once VCCreaches 1V, RESET is guaranteed to be a logic low. For information about applications where VCCis less than 1V, see the section
Ensuring a Valid RESET/RESET Output Down to VCC=
0V (MAX6303/MAX6304)
low. When VINrises above V
and RESET remains low. When the reset timeout period
ends, RESET goes high.
On power-down, once VINgoes below V
goes low and is guaranteed to be low until VCCdroops
below 1V. For information about applications where
VCCis less than 1V, see the section
RESET/RESET Output Down to VCC= 0V (MAX6303/
MAX6304)
The MAX6302/MAX6304 active-high RESET output is
the inverse of the MAX6301/MAX6303 active-low
RESET output, and is guaranteed valid for VCC> 1.31V.
These supervisors monitor the voltage on RESET IN.
The MAX6301–MAX6304 have an adjustable reset
threshold voltage (V
voltage divider (Figure 1). Use the following formula to
calculate V
age triggers a reset):
where V
VTHis the reset input threshold (1.22V). Resistors R1 and
RST
).
). RESET
RST
. Once V
, RESET remains low for the reset timeout
RST
. As VCCrises, RESET remains
, the reset timer starts
RST
RST
RST
, RESET
Ensuring a Valid
.
Reset Threshold
) set with an external resistor
RST
(the point at which the monitored volt-
RST
VR1R2
×+
()
V
RST
is the desired reset threshold voltage and
TH
=
R2
V
()
Typical
IN
V
IN
R1
RESET IN
R2
Figure 1. Calculating the Reset Threshold Voltage (V
R2 can have very high values to minimize current consumption. Set R2 to some conveniently high value (1MΩ,
for example) and calculate R1 based on the desired
reset threshold voltage, using the following formula:
MAX6301
MAX6302
MAX6303
MAX6304
R1 R2
=× −
V
V
V
CC
RST
TH
V
RST
1
Ω
()
0.1µF
= 1.22
R1 + R2
(
)
R2
)
RST
Watchdog Timer
The watchdog circuit monitors the µP’s activity. If the µP
does not toggle the watchdog input (WDI) within t
(user selected), reset asserts. The internal watchdog
timer is cleared by reset, by a transition at WDI (which
can detect pulses as short as 30ns), or by a transition
at WDS. The watchdog timer remains cleared while
reset is asserted; as soon as reset is released, the timer
starts counting (Figure 2).
The MAX6301–MAX6304 feature two modes of watchdog timer operation: normal mode and extended mode.
In normal mode (WDS = GND), the watchdog timeout
period is determined by the value of the capacitor connected between SWT and ground (see the section
WD
Selecting the Reset and Watchdog Timeout Capacitor
In extended mode (WDS = VCC), the watchdog timeout
period is multiplied by 500. For example, in the extended mode, a 1µF capacitor gives a watchdog timeout
period of 22 minutes (see the graph Extended-Mode
Watchdog Timeout Period vs. C
Operating Characteristics
In extended mode, the watchdog function can be disabled by leaving WDI unconnected or by three-stating
the driver connected to WDI. In this mode, the watchdog input is internally driven low during the watchdog
timeout period, then momentarily pulses high, resetting
the watchdog counter. When WDI is left unconnected,
the watchdog timer is cleared by this internal driver just
before the timeout period is reached (the internal driver
pulls WDI high at about 94% of tWD). When WDI is
three-stated, the maximum allowable leakage current of
the device driving WDI is 10µA.
In normal mode (WDS = GND), the watchdog timer
cannot be disabled by three-stating WDI. WDI is a
high-impedance input in this mode. Do not leave WDI
unconnected in normal mode.
+5V, Low-Power µP Supervisory Circuits
with Adjustable Reset/Watchdog
V
IN
R1
RESET IN
R2
Figure 4. Monitoring a Voltage Other than V
MAX6301
MAX6302
MAX6303
MAX6304
V
CC
V
CC
0.1µF
= 1.22
CC
R1 + R2
(
R2
V
RST
MAX6301–MAX6304
__________Applications Information
Selecting the Reset and
Watchdog Timeout Capacitor
The reset timeout period is adjustable to accommodate
a variety of µP applications. Adjust the reset timeout
period (tRS) by connecting a specific value capacitor
(C
) between SRT and ground (Figure 3). Calculate
SRT
the reset timeout capacitor as follows:
C
= tRP⁄ 2.67
SRT
with C
age (<10nA) type capacitor. Ceramic is recommended.
The watchdog timeout period is adjustable to accommodate a variety of µP applications. With this feature,
the watchdog timeout can be optimized for software
execution. The programmer can determine how often
the watchdog timer should be serviced. Adjust the
watchdog timeout period (tWD) by connecting a specific value capacitor (C
(Figure 3). For normal-mode operation, calculate the
watchdog timeout capacitor as follows:
where C
low leakage (<10nA) type capacitor. Ceramic is recommended.
The
monitoring other voltages is simple, and Figure 4 shows
a circuit that accomplishes this. Calculate V
shown in the
in pF and tRPin µs. C
SRT
C
SWT
is in pF and tWDis in µs. C
SWT
) between SWT and ground
SWT
= tWD⁄ 2.67
must be a low-leak-
SRT
SRT
Monitoring Voltages Other than V
Typical Operating Circuit
Reset Threshold
monitors VCC. However,
section.
must be a
)
RST
CC
as
MAX6302
* THREE-STATE LEAKAGE MUST BE <10µA.
Figure 5. Wake-Up Timer
GND
V
RESET
WDI
WDS
CC
V
CC
80C51
RST
*
I/O
I/O
I/O
GND
V
CC
V
CC
Wake-Up Timer
In some applications, it is advantageous to put a µP
into sleep mode, periodically “wake it up” to perform
checks and/or tasks, then put it back into sleep mode.
The MAX6301 family supervisors can easily accommodate this technique. Figure 5 illustrates an example
using the MAX6302 and an 80C51.
In Figure 5, just before the µC puts itself into sleep
mode, it pulls WDS high. The µC’s I/O pins maintain
their logic levels while in sleep mode and WDS remains
high. This places the MAX6302 in extended mode,
increasing the watchdog timeout 500 times. When the
watchdog timeout period ends, a reset is applied on
the 80C51, “waking it up” to perform tasks. While the µP
is performing tasks, the 80C51 pulls WDS low (selecting normal mode), and the MAX6302 monitors the µP
for hang-ups. When the µP finishes its tasks, it puts
itself back into sleep mode, drives WDS high, and
starts the cycle over again. This is a power-saving technique, since the µP is operating only part of the time
and the MAX6302 has very low quiescent current.
Adding a Manual Reset Function
A manual reset option can easily be implemented by
connecting a normally open momentary switch in parallel with R2 (Figure 6). When the switch is closed, the
voltage on RESET IN goes to zero, initiating a reset.
When the switch is released, reset remains asserted for
the reset timeout period and then is cleared. The pushbutton switch is effectively debounced by the reset
timer.
Since RESET is open-drain, the MAX6301 interfaces
easily with µPs that have bidirectional reset pins, such
as the Motorola 68HC11 (Figure 7). Connecting RESET
directly to the µP’s reset pin with a single pull-up allows
either device to assert reset.
RESET TO
OTHER SYSTEM
COMPONENTS
V
CC
MAX6301
V
CC
0.1µF
GND
RESET
Figure 7. Interfacing to µPs with Bidirectional Reset I/O Pins
WDI
4.7k
WATCHDOG
TIMER
V
CC
µP
RESET
TO RESET
GENERATOR
MAX6301–MAX6304
Negative-Going VCCTransients
In addition to issuing a reset to the µP during power-up,
power-down, and brownout conditions, these supervisors
are relatively immune to short-duration negative-going
transients (glitches). The graph Maximum Transient
Duration vs. Reset Threshold Overdrive in the
Operating Characteristics
shows this relationship.
Typical
The area below the curves of the graph is the region in
which these devices typically do not generate a reset
pulse. This graph was generated using a negativegoing pulse applied to VIN, starting above the actual
reset threshold (V
) and ending below it by the mag-
RST
nitude indicated (reset-threshold overdrive). As the
magnitude of the transient increases (farther below the
reset threshold), the maximum allowable pulse width
decreases. Typically, a VCCtransient that goes 100mV
below the reset threshold and lasts 50µs or less will not
cause a reset pulse to be issued.
Watchdog Input Current
Extended Mode
In extended mode (WDS = VCC), the WDI input is internally driven through a buffer and series resistor from
the watchdog counter (Figure 8). When WDI is left
unconnected, the watchdog timer is serviced within the
MAX6301
MAX6302
WDS
Figure 8. Watchdog Input Structure
TO MODE
CONTROL
MAX6303
MAX6304
watchdog timeout period by a very brief low-high-low
pulse from the counter chain. For minimum watchdog
input current (minimum overall power consumption),
leave WDI low for the majority of the watchdog timeout
period, pulsing it low-high-low (>30ns) once within the
period to reset the watchdog timer. If instead WDI is
externally driven high for the majority of the timeout
period, typically 70µA can flow into WDI.
Normal Mode
In normal mode (WDS = GND), the internal buffer that
drives WDI is disabled. In this mode, WDI is a standard
CMOS input and leakage current is typically 100pA,
regardless of whether WDI is high or low.
+5V, Low-Power µP Supervisory Circuits
with Adjustable Reset/Watchdog
V
CC
MAX6303
Figure 9. Ensuring RESET Valid to VCC= 0V
MAX6301–MAX6304
Ensuring a Valid
Down to V
CC
V
CC
0.1µF
RESET
GND
RESET
100k
/RESET Output
= 0V (MAX6303/MAX6304)
When VCCfalls below 1V, RESET/RESET current sinking (sourcing) capabilities decline drastically. In the
case of the MAX6303, high-impedance CMOS-logic
inputs connected to RESET can drift to undetermined
voltages. This presents no problem in most applications, since most µPs and other circuitry do not operate
with VCCbelow 1V.
In those applications where RESET must be valid down
to 0V, adding a pull-down resistor between RESET and
ground sinks any stray leakage currents, holding
RESET low (Figure 9). The value of the pull-down resistor is not critical; 100kΩ is large enough not to load
RESET and small enough to pull RESET to ground. For
applications using the MAX6304, a 100kΩ pull-up resistor between RESET and VCCwill hold RESET high when
VCCfalls below 1V (Figure 10).
V
CC
MAX6304
Figure 10. Ensuring RESET Valid to VCC= 0V
V
CC
RESET
GND
START
SET WDI
LOW
SUBROUTINE OR
PROGRAM LOOP
SET WDI HIGH
RETURN
END
0.1µF
100k
Watchdog-Software Considerations
To help the watchdog timer monitor software execution
more closely, set and reset the watchdog input at different points in the program, rather than “pulsing” the
watchdog input high-low-high or low-high-low. This
technique avoids a “stuck” loop in which the watchdog
timer would continue to be reset within the loop, keeping the watchdog from timing out.
Figure 11 shows an example of a flow diagram where
the I/O driving the watchdog input is set high at the
beginning of the program, set low at the beginning of
every subroutine or loop, then set high again when the
program returns to the beginning. If the program should
“hang” in any subroutine the problem would quickly be
corrected, since the I/O is continually set low and the
watchdog timer is allowed to time out, causing a reset
or interrupt to be issued. When using extended mode,
as described in the
Watchdog Input Current
this scheme does result in higher average WDI input
current than does the method of leaving WDI low for the
majority of the timeout period and periodically pulsing it
low-high-low.
section,
+5V, Low-Power µP Supervisory Circuits
with Adjustable Reset/Watchdog
_____________Layout Considerations
SRT and SWT are precision current sources. When
developing the layout for the application, be careful to
minimize board capacitance and leakage currents
around these pins. Traces connected to these pins
should be kept as short as possible. Traces carrying
high-speed digital signals and traces with large voltage
potentials should be routed as far from these pins as
possible. Leakage currents and stray capacitance (e.g.,
a scope probe) at these pins could cause errors in the
reset and/or watchdog timeout period. When evaluating
these parts, use clean prototype boards to ensure accurate reset and watchdog timeout periods.
RESET IN is a high-impedance input which is typically
driven by a high-impedance resistor-divider network
(e.g., 1MΩ to 10MΩ). Minimize coupling to transient
signals by keeping the connections to this input short.
Any DC leakage current at RESET IN (e.g., a scope
probe) causes errors in the programmed reset threshold. Note that sensitive pins are located on the GND
side of the device, away from the digital I/O, to simplify
board layout.
__Ordering Information (continued)
PART
MAX6302CPA
MAX6302CSA
MAX6302CUA0°C to +70°C
MAX6302EPA
MAX6302ESA-40°C to +85°C
MAX6303CPA
MAX6303CSA0°C to +70°C8 SO
MAX6303CUA0°C to +70°C8 µMAX
MAX6303EPA-40°C to +85°C8 Plastic DIP
MAX6303ESA-40°C to +85°C8 SO
MAX6304CPA
MAX6304CSA0°C to +70°C8 SO
MAX6304CUA0°C to +70°C8 µMAX
MAX6304EPA-40°C to +85°C8 Plastic DIP
MAX6304ESA-40°C to +85°C8 SO
+5V, Low-Power µP Supervisory Circuits
with Adjustable Reset/Watchdog
________________________________________________________Package Information
C
A
0.101mm
e
MAX6301–MAX6304
D
EH
0.004 in
A1B
D
A
0.101mm
e
A1
B
0.004in.
DIM
α
L
A1
8-PIN µMAX
MICROMAX SMALL-OUTLINE
PACKAGE
DIM
A1
0°-8°
C
L
INCHESMILLIMETERS
A
0.036
0.004
B
0.010
C
0.005
D
0.116
E
0.116
e
H
0.188
L
0.016
α
A
0.053
0.004
B
0.014
C
0.007
E
0.150
e
H
0.228
L
0.016
MAX
MIN
0.044
0.008
0.014
0.007
0.120
0.120
0°
MIN
0.198
0.026
6°
INCHESMILLIMETERS
MAX
0.069
0.010
0.019
0.010
0.157
0.244
0.050
MIN
0.91
0.10
0.25
0.13
2.95
2.95
4.78
0.41
0°
MIN
1.35
0.10
0.35
0.19
3.80
5.80
0.40
MAX
1.11
0.20
0.36
0.18
3.05
3.05
0.650.0256
1.270.050
5.03
0.66
6°
21-0036D
MAX
1.75
0.25
0.49
0.25
4.00
6.20
1.27
PINS
Narrow SO
HE
SMALL-OUTLINE
PACKAGE
(0.150 in.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12
__________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
12
__________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600