MAXIM MAX5898 Technical data

General Description

The MAX5898 programmable interpolating, modulating,
500Msps, dual digital-to-analog converter (DAC) offers
superior dynamic performance and is optimized for high­performance wideband, single- and multicarrier transmit
applications. The device integrates a selectable 2x/4x/8x
interpolating filter, a digital quadrature modulator, and
dual 16-bit, high-speed DACs on a single integrated cir­cuit. At 30MHz output frequency and 500Msps update
rate, the in-band SFDR is 81dBc, while only consuming

1.2W. The device also delivers 71dB ACLR for four­carrier WCDMA at a 61.44MHz output frequency.

The selectable interpolating filters allow lower input data
rates while taking advantage of the high DAC update
rates. These linear-phase interpolation filters ease recon­struction filter requirements and enhance the passband
dynamic performance. Each channel includes offset and
gain programmability, allowing the user to calibrate out
local oscillator (LO) feedthrough and sideband suppres­sion errors generated by analog quadrature modulators.

The MAX5898 features a f

IM

/ 4 digital image-reject
modulator. This modulator generates a quadrature-mod­ulated IF signal that can be presented to an analog I/Q
modulator to complete the upconversion process. A
second digital modulation mode allows the signal to be
frequency-translated with image pairs at fIM/ 2 or fIM/ 4.

The MAX5898 features a standard LVDS interface for
low electromagnetic interference (EMI). Interleaved
data is applied through a single 16-bit bus. A 3.3V
SPI™ port is provided for mode configuration. The pro­grammable modes include the selection of 2x/4x/8x
interpolating filters, fIM/ 2, fIM/ 4 or no digital quadra­ture modulation with image rejection, individual channel
gain and offset adjustment, and offset binary or two’s­complement data interface.

Compatible versions with CMOS interfaces and 12-, 14-,
and 16-bit resolutions are also available. Refer to the
MAX5893 data sheet for 12-bit CMOS, MAX5894 for 14­bit CMOS, and the MAX5895 for 16-bit CMOS versions.

Applications

Base Stations: 3G Multicarrier UMTS, CDMA, and GSM

Broadband Wireless Transmitters

Broadband Cable Infrastructure

Instrumentation and Automatic Test Equipment (ATE)

Analog Quadrature Modulation Architectures

Features

o 71dB ACLR at f

OUT

= 61.44MHz (Four-Carrier

WCDMA)

o Meets Multicarrier UMTS, cdma2000

®

, GSM

Spectral Masks (f

OUT

= 122MHz)

o Noise Spectral Density = -160dBFS/Hz at

f

OUT

= 16MHz

o 90dBc SFDR at Low-IF Frequency (10MHz)
o 88dBc SFDR at High-IF Frequency (50MHz)
o Low Power: 831mW (f

CLK

= 250MHz)

o User Programmable

Selectable 2x, 4x, or 8x Interpolating Filters

< 0.01dB Passband Ripple

> 95dB Stopband Rejection
Selectable Real or Complex Modulator Operation
Selectable Modulator LO Frequency: OFF, fIM/ 2,
or fIM/ 4
Selectable Output Filter: Lowpass or Highpass
Per Channel Gain and Offset Adjustment

o EV Kit Available (Order the MAX5898EVKIT)

MAX5898

16-Bit, 500Msps, Interpolating and Modulating

Dual DAC with Interleaved LVDS Inputs

________________________________________________________________

Maxim Integrated Products

1

Selector Guide

Ordering Information

Simplified Diagram

19-3756; Rev 2; 8/10

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.

Pin Configuration appears at end of data sheet.

SPI is a trademark of Motorola, Inc.
cdma2000 is a registered trademark of Telecommunications
Industry Association.

+

Denotes a lead(Pb)-free/RoHS-compliant package.

*

EP = Exposed paddle.

D = Dry pack

EVALUATION KIT

AVAILABLE

PART TEMP RANGE PIN-PACKAGE

M AX 5898E GK+ D -40°C to +85°C

M AX 5898E GK- D -40°C to +85°C

68 QFN-EP*
(10mm x 10mm)

68 QFN-EP*
(10mm x 10mm)

PART

MAX5893 12 500 CMOS

MAX5894 14 500 CMOS

MAX5895 16 500 CMOS

MAX5898 16 500 LVDS

RESOLUTION

(BITS)

DAC UPDATE

RATE (Msps)

FILTERS

INTERPOLATING

1x/2x/4x

DATA SYNCH

DATA PORT

DATACLK

AND DEMUX

MODULATOR

FILTERS

INTERPOLATING

DAC

2x

DAC

INPUT

LOGIC

OUTI

OUTQ

MAX5898

16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(DV

DD1.8

= AV

DD1.8

= 1.8V, AV

CLK

= AV

DD3.3

= DV

DD3.3

= 3.3V, modulator off, 2x interpolation, DATACLK output mode, output is

50Ω double-terminated, external reference at 1.25V, T

A

= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C,

unless otherwise noted.) (Note 2)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

DV

DD1.8

, AV

DD1.8

to GND, DACREF ..................-0.3V to +2.16V

AV

DD3.3

, AV

CLK

, DV

DD3.3

to GND, DACREF........-0.3V to +3.9V

DATACLKP, DATACLKN, D0P–D15P,

D0N–D15N, SELIQP, SELIQN to GND,

DACREF ..........................................-0.3V to (DV

DD1.8

+ 0.3V)

CS, RESET, SCLK, DIN, DOUT to

GND, DACREF ................................-0.3V to (DV

DD3.3

+ 0.3V)

CLKP, CLKN to GND, DACREF..............-0.3V to (AV

CLK

+ 0.3V)

REFIO, FSADJ to GND, DACREF ........-0.3V to (AV

DD3.3

+ 0.3V)

OUTIP, OUTIN, OUTQP,

OUTQN to GND, DACREF..................-1V to (AV

DD3.3

+ 0.3V)

DOUT, DATACLKP, DATACLKN Continuous Current ..........8mA

Continuous Power Dissipation (T

A

= +70°C)
68-Pin QFN (derate 41.7mW/°C above +70°C)

(Note 1) ...................................................................3333.3mW

Junction Temperature......................................................+150°C

Operating Temperature Range ...........................-40°C to +85°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

Soldering Temperature (reflow) .......................................+260°C

Note 1: Thermal resistance based on a multilayer board with 4 x 4 via array in exposed paddle area.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

STATIC PERFORMANCE

Resolution 16 Bits

Differential Nonlinearity DNL ±1 LSB

Integral Nonlinearity INL ±3 LSB

Offset Error OS -0.02 ±0.003 +0.02 %FS

Offset Drift ±0.03 ppm/°C

Gain Error GE

(Note 3) -4 ±0.06 +4 %FS

FS

Gain-Error Drift ±110 ppm/°C

Full-Scale Output Current I

OUTFS

(Note 3) 2 20 mA

Output Compliance -0.5 +1.1 V

Output Resistance R

Output Capacitance C

OUT

OUT

DYNAMIC PERFORMANCE

Maximum Clock Frequency f

Minimum Clock Frequency f

Maximum DAC Update Rate f

Minimum DAC Update Rate f

Maximum Data Clock Frequency f

Maximum Input Data Rate f

CLK

CLK

DAC

DAC

DATACLK

DATA

f

= f

DAC

CLK

f

= f

DAC

CLK

Interleaved data 250 MHz

Per channel 125 MWps

f

= 125Mwps,

DATA

= 16MHz, f

f

OUT

= 10MHz, -12dBFS

Noise Spectral Density

= 125Mwps,

f

DATA

f

= 16MHz, f

OUT

= 10MHz, 0dBFS

1MΩ

5pF

500 MHz

or f

or f

DAC

DAC

= f

/ 2 500 Msps

CLK

= f

/ 2 10 Msps

CLK

No interpolation -156

OFFSET

2x interpolation -157

4x interpolation -157

OFFSET

4x interpolation -154

10 MHz

dBFS/

Hz

MAX5898

16-Bit, 500Msps, Interpolating and Modulating

Dual DAC with Interleaved LVDS Inputs

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(DV

DD1.8

= AV

DD1.8

= 1.8V, AV

CLK

= AV

DD3.3

= DV

DD3.3

= 3.3V, modulator off, 2x interpolation, DATACLK output mode, output is

50Ω double-terminated, external reference at 1.25V, T

A

= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C,

unless otherwise noted.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

In-Band SFDR
(DC to f

DATA

/ 2)

SFDR

Two-Tone IMD TTIMD

f

DATA

= 125Mwps,

interpolation off,

-0.1dBFS

f

= 125Mwps,

DATA

2x interpolation,

-0.1dBFS

f

= 125Mwps,

DATA

4x interpolation,

-0.1dBFS

f

= 125Mwps,

DATA

f

= 9MHz, f

OUT1

10MHz, -6.1dBFS

f

= 125Mwps,

DATA

= 79MHz,

f

OUT1

f

= 80MHz,

OUT2

-6.1dBFS

f

= 62.5Mwps,

DATA

= 9MHz, f

f

OUT1

10MHz, -6.1dBFS

OUT2

OUT2

f

= 10MHz 90

OUT

f

= 30MHz 84

OUT

f

= 50MHz 77

OUT

f

= 10MHz 79 89

OUT

f

= 30MHz 83

OUT

= 50MHz 92

f

OUT

f

= 10MHz 89

OUT

f

= 30MHz 83

OUT

f

= 50MHz 89

OUT

No interpolation -96

=

2x interpolation -99

4x interpolation -95

2x interpolation,

/ 4 complex

f

IM

modulation

4x interpolation,
f

/ 4 complex

IM

modulation

=

8x interpolation -94

dBc

-81

-71

dBc

Four-Tone IMD FTIMD

ACLR for WCDMA
(Note 4)

ACLR

f

= 62.5Mwps,

DATA

f

= 69MHz, f

OUT1

OUT2

= 70MHz, -6.1dBFS

f

= 62.5Mwps,

DATA

f

= 179MHz, f

OUT1

= 180MHz, -6.1dBFS

= 125Mwps, f

f

DATA

OUT2

spaced 1MHz

OUT

8x interpolation,
f

/ 4 complex

IM

modulation

8x, highpass
interpolation,
f

/ 4 complex

IM

modulation

apart from 32MHz, -12dBFS, 2x
interpolation

f

= 61.44Mwps,

DATA

= baseband

f

OUT

f

= 122.88Mwps,

DATA

= 61.44MHz

f

OUT

f

= 122.88Mwps,

DATA

f

= 122.88MHz

OUT

4x interpolation 79

8x interpolation 79

2x interpolation,

/ 4 complex

f

IM

modulation

4x interpolation,
f

/ 4 complex

IM

modulation

-71

-71

-89 dBc

76

dB

68

MAX5898

16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(DV

DD1.8

= AV

DD1.8

= 1.8V, AV

CLK

= AV

DD3.3

= DV

DD3.3

= 3.3V, modulator off, 2x interpolation, DATACLK output mode, output is

50Ω double-terminated, external reference at 1.25V, T

A

= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C,

unless otherwise noted.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output Propagation Delay t

Output Rise Time t

Output Fall Time t

PD

RISE

FALL

1x interpolation (Note 5) 2.9 ns

10% to 90% (Note 6) 0.75 ns

10% to 90% (Note 6) 1 ns

Output Settling Time To 0.5% (Note 6) 11 ns

Output Bandwidth -1dB bandwidth (Note 7) 240 MHz

Passband Width Ripple < -0.01dB

Stopband Rejection

0.604 x f

0.604 x f

0.604 x f

, 2x interpolation 100

DATA

, 4x interpolation 100

DATA

, 8x interpolation 100

DATA

0.4 x

f

DATA

1x interpolation 22

Data Latency

2x interpolation 70

4x interpolation 146

8x interpolation 311

DAC INTERCHANNEL MATCHING

Gain Match ∆Gain f

Gain-Match Tempco ∆Gain/°C I

Phase Match ∆Phase f

Phase-Match Tempco ∆Phase/°C I

DC Gain Match I

Crosstalk f

= DC - 80MHz, I

OUT

= 20mA ±0.02 ppm/°C

OUTFS

= 60MHz, I

OUT

= 20mA ±0.006 Deg/°C

OUTFS

= 20mA (Note 3) -0.2 ±0.04 +0.2 dB

OUTFS

= 50MHz, f

OUT

OUTFS

DAC

= 20mA ±0.1 dB

OUTFS

= 20mA ±0.13 Deg

= 250MHz -95 dB

REFERENCE

Reference Input Range 0.12 1.32 V

Reference Output Voltage V

Reference Input Resistance R

REFIO

REFIO

Internal reference 1.14 1.2 1.28 V

10 kΩ

Reference Voltage Drift ±50 ppm/°C

CMOS LOGIC INPUTS (SCLK, CS, RESET, DIN)

Input High Voltage V

Input Low Voltage V

Input Current I

Input Capacitance C

IH

IL

IN

IN

0.7 x

DV

DD3.3

0.3 x

DV

DD3.3

-10 ±0.1 +10 µA

3pF

CMOS LOGIC OUTPUT (DOUT)

Output High Voltage V

Output Low Voltage V

OH

OL

I

LOAD

I

SINK

= 200µA

= 200µA

DV

0.8 x

DD3.3

DV

0.2 x

DD3.3

Output Leakage Current Tri-state 1 µA

dB

Clock

Cycles

V

V

V

V

MAX5898

16-Bit, 500Msps, Interpolating and Modulating

Dual DAC with Interleaved LVDS Inputs

_______________________________________________________________________________________ 5

ELECTRICAL CHARACTERISTICS (continued)

(DV

DD1.8

= AV

DD1.8

= 1.8V, AV

CLK

= AV

DD3.3

= DV

DD3.3

= 3.3V, modulator off, 2x interpolation, DATACLK output mode, output is

50Ω double-terminated, external reference at 1.25V, T

A

= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C,

unless otherwise noted.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Rise/Fall Time C

= 10pF, 20% to 80% 1.5 ns

LOAD

LVDS LOGIC INPUTS (D15P–D0P, D15N–D0N, SELIQP, SELIQN)

Differential Input Logic High V

Differential Input Logic Low V

Input Common-Mode Voltage V

Differential Input Resistance R

Input Capacitance C

IH

IL

ICM

IN

IN

100 mV

-100 mV

1.125 1.25 1.375 V

110 Ω

2.5 pF

LVDS CLOCK INPUT/OUTPUT (DATACLKP, DATACLKN)

Differential Input Amplitude High V

Differential Input Amplitude Low V

IH

IL

D i ffer enti al Outp ut Am p l i tud e H i g hVOHR

Differential Output Amplitude Low V

Output Common-Mode Voltage V

OL

OCM

Output Rise/Fall Time

= 100Ω d i ffer enti al ( N ote 3) 250 340 mV

LOAD

R

= 100Ω d i ffer enti al ( N ote 3) -340 -250 mV

LOAD

R

= 100Ω d i ffer enti al , C

LOAD

LOAD

= 8pF,

20% to 80%

250 mV

-250 mV

1.25 V

0.9 ns

CLOCK INPUTS (CLKP, CLKN) (Note 8)

Differential Input Voltage Swing V

DIFF

Sine-wave input > 1.5

Square-wave input > 0.5

Differential Input Slew Rate > 100 V/µs

AV

/

Common-Mode Voltage V

Differential Input Resistance R

Differential Input Capacitance C

COM

CLK

CLK

AC-coupled

CLK

2

5kΩ

5pF

Minimum Clock Duty Cycle 45 %

Maximum Clock Duty Cycle 55 %

CLKP/CLKN, DATACLK TIMING (Figure 4) (Note 9)

CLK to DATACLK Delay t

Data Hold Time t

Data Setup Time t

D

DH

DS

DATACLK output mode 1.4 ns

1.65 ns

-0.65 ns

SERIAL-PORT INTERFACE TIMING (Figure 3) (Note 9)

SCLK Frequency f
CS Setup Time t

Input Hold Time t

Input Setup Time t

Data Valid Duration t

SCLK

SS

SDH

SDS

SDV

2.5 ns

0ns

4.5 ns

6.5 16.5 ns

10 MHz

POWER SUPPLIES

Digital Supply Voltage DV

Digital I/O Supply Voltage DV

DD1.8

DD3.3

1.71 1.8 1.89 V

3.0 3.3 3.6 V

V

P-P

V

MAX5898

16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs

6 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(DV

DD1.8

= AV

DD1.8

= 1.8V, AV

CLK

= AV

DD3.3

= DV

DD3.3

= 3.3V, modulator off, 2x interpolation, DATACLK output mode, output is

50Ω double-terminated, external reference at 1.25V, T

A

= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C,

unless otherwise noted.) (Note 2)

Note 2: All specifications are 100% tested at T

A

≥ +25°C. Specifications at TA< +25°C are guaranteed by design and characterization.

Note 3: Specification is 100% production tested at T

A

≥ +25°C.

Note 4: 3.84MHz bandwidth, single carrier.
Note 5: Excludes data latency.
Note 6: Measured single-ended into a 50Ω load.
Note 7: Excludes sin(x)/x rolloff.
Note 8: Differential voltage swing defined as

I

V

P

I+ I

V

N

I

.

Note 9: Guaranteed by design and characterization.
Note 10:Parameter defined as the change in midscale output caused by a ±5% variation in the nominal supply voltage.

V(CLKN)

V(CLKP)

V

P

V

N

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Clock Supply Voltage AV

Analog Supply Voltage

AV

AV

I

AVDD3.3

Analog Supply Current

I

AVDD1.8

Digital Supply Current I

Digital I/O Supply Current I

Clock Supply Current I

DVDD1.8

DVDD3.3

AVCLK

Total Power Dissipation P

Power-Down Current

AV
Ratio

Power-Supply Rejection

DD3.3

PSRR

CLK

DD3.3

DD1.8

TOTAL

3.135 3.3 3.465 V

3.135 3.3 3.465

1.71 1.8 1.89

f

= 250MHz, 2x interpolation, 0dBFS,

CLK

= 10MHz

f

OUT

f

= 250MHz, 2x interpolation, 0dBFS,

CLK

= 10MHz

f

OUT

f

= 250MHz, 2x interpolation, 0dBFS,

CLK

= 10MHz

f

OUT

f

= 250MHz, 2x interpolation, 0dBFS,

CLK

= 10MHz

f

OUT

f

= 250MHz, 2x interpolation, 0dBFS,

CLK

f

= 10MHz

OUT

f

= 250MHz, 2x interpolation, 0dBFS,

CLK

f

= 10MHz

OUT

AV

DD3.3

AV

DV

DV

AV

DD1.8

DD1.8

DD3.3

CLK

All I/O are static high or
low, bit 2 to bit 4 of
address 00h are set high

(Note 10) 0.125 %FS/V

A

111 130

27 32

229 250 mA

912mA

2.3 4 mA

831 mW

530

1

26

350

2

V

mA

µA

MAX5898

16-Bit, 500Msps, Interpolating and Modulating

Dual DAC with Interleaved LVDS Inputs

_______________________________________________________________________________________

7

Typical Operating Characteristics

(DV

DD1.8

= AV

DD1.8

= 1.8V, AV

CLK

= AV

DD3.3

= DV

DD3.3

= 3.3V, DATACLK output mode, external reference, V

REFIO

= +1.25V,

R

LOAD

= 50Ω double-terminated, I

OUTFS

= 20mA, TA= +25°C, unless otherwise noted.)

SFDR vs. OUTPUT FREQUENCY

= 125Mwps, NO INTERPOLATION

f

DATA

120

-0.1dBFS

100

80

60

SFDR (dBc)

40

20

0

060

10 20 30 40 50

OUTPUT FREQUENCY (MHz)

IN-BAND SFDR vs. OUTPUT FREQUENCY

= 125Mwps, 2x INTERPOLATION

f

DATA

90

80

70

60

50

40

SFDR (dBc)

30

20

10

0

62.5 112.5

-6dBFS

-12dBFS

UPPER SIDEBAND MODULATION
SPURS MEASURED BETWEEN

62.5MHz AND 125MHz

OUTPUT FREQUENCY (MHz)

-12dBFS

-0.1dBFS

-6dBFS

-0.1dBFS

-0.1dBFS

102.592.582.572.5

IN-BAND SFDR vs. OUTPUT FREQUENCY

= 125Mwps, 2x INTERPOLATION

f

DATA

120

-0.1dBFS

100

MAX5898 toc01

80

60

SFDR (dBc)

40

20

-12dBFS

SPURS MEASURED BETWEEN
0MHz AND 62.5MHz

0

050

OUTPUT FREQUENCY (MHz)

-6dBFS

IN-BAND SFDR vs. OUTPUT FREQUENCY

= 125Mwps, 4x INTERPOLATION

f

DATA

MAX5898 toc04

120

100

SFDR (dBc)

-0.1dBFS

80

60

40

20

SPURS MEASURED BETWEEN
0MHz AND 62.5MHz

0

050

OUTPUT FREQUENCY (MHz)

-6dBFS

-12dBFS

0UT-OF-BAND SFDR vs. OUTPUT FREQUENCY

= 125Mwps, 2x INTERPOLATION

f

DATA

100

90

MAX5898 toc02

80

70

60

50

SFDR (dBc)

40

30

20

SPURS MEASURED BETWEEN

10

62.5MHz AND 125MHz

0

40302010

050

-6dBFS

-0.1dBFS

OUTPUT FREQUENCY (MHz)

OUT-OF-BAND SFDR vs. OUTPUT FREQUENCY

= 125Mwps, 4x INTERPOLATION

f

DATA

90

80

MAX5898 toc05

70

60

50

-12dBFS

40

SFDR (dBc)

30

20

SPURS MEASURED BETWEEN

10

62.5MHz AND 250MHz

0

40302010

050

OUTPUT FREQUENCY (MHz)

-0.1dBFS

-6dBFS

-12dBFS

MAX5898 toc03

40302010

MAX5898 toc06

40302010

IN-BAND SFDR vs. OUTPUT FREQUENCY

= 125Mwps, 4x INTERPOLATION

f

DATA

100

90

80

-6dBFS

70

60

50

SFDR (dBc)

40

30

20

LOWER SIDEBAND MODULATION
SPURS MEASURED BETWEEN

10

62.5MHz AND 125MHz

0

70 120

OUTPUT FREQUENCY (MHz)

-0.1dBFS

-12dBFS

IN-BAND SFDR vs. OUTPUT FREQUENCY

= 125Mwps, 4x INTERPOLATION

f

DATA

100

-0.1dBFS

90

MAX5898 toc07

80

70

60

50

SFDR (dBc)

40

30

20

LOWER SIDEBAND MODULATION
SPURS MEASURED BETWEEN

10

125MHz AND 187.5MHz

0

1101009080

70 120

-12dBFS

MAX5898 toc08

-6dBFS

1101009080

OUTPUT FREQUENCY (MHz)

TWO-TONE IMD vs. OUTPUT FREQUENCY

= 125Mwps, NO INTERPOLATION

f

DATA

0

1MHz CARRIER SPACING

-20

-40

-60

-80

TWO-TONE IMD (dBc)

-100

-120

-12dBFS

-9dBFS

10 40

15 20 25 30 35

CENTER FREQUENCY (MHz)

MAX5898 toc09

-6dBFS

MAX5898

16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs

8 _______________________________________________________________________________________

Typical Operating Characteristics (continued)

(DV

DD1.8

= AV

DD1.8

= 1.8V, AV

CLK

= AV

DD3.3

= DV

DD3.3

= 3.3V, DATACLK output mode, external reference, V

REFIO

= +1.25V,

R

LOAD

= 50Ω double-terminated, I

OUTFS

= 20mA, TA= +25°C, unless otherwise noted.)

TWO-TONE IMD vs. OUTPUT FREQUENCY

= 125Mwps, 2x INTERPOLATION

f

DATA

0

1MHz CARRIER SPACING
COMPLEX MODULATION FOR

-20

OUTPUT FREQUENCIES
GREATER THAN 50MHz

-40

-60

-12dBFS

-80

TWO-TONE IMD (dBc)

-100

-6dBFS

-120
10 100

25 40 55 70 85

CENTER FREQUENCY (MHz)

-6dBFS

-9dBFS

TWO-TONE IMD vs. OUTPUT FREQUENCY

= 125Mwps, 4x INTERPOLATION

f

DATA

0

1MHz CARRIER SPACING
COMPLEX MODULATION FOR

-20

MAX5898 toc10

OUTPUT FREQUENCIES
GREATER THAN 50MHz

-40

-60

-12dBFS

-80

TWO-TONE IMD (dBc)

-100

-6dBFS

-120
10 160

35 60 85 110 135

-9dBFS

CENTER FREQUENCY (MHz)

-6dBFS

-12dBFS

0.100

MAX5898 toc11

0.075

0.050

GAIN MISMATCH (dB)

0.025

CHANNEL-TO-CHANNEL

GAIN MISMATCH vs. TEMPERATURE

= 125Mwps, 2x INTERPOLATION

f

DATA

f

= 22.7MHz

OUT

= -6dBFS

A

OUT

0

-40 85
TEMPERATURE (°C)

MAX5898 toc12

603510-15

EIGHT-TONE POWER RATIO PLOT

= 125Mwps, 2x INTERPOLATION

f

DATA

-20

-30

-40

-50

-60

-70

-80

-90

OUTPUT POWER (dBm)

-100

-110

-120
f

= 35.7MHz, 1MHz TONE SPACING

CENTER

SPAN = 12.5MHz, A

THROUGH A

OUT1

SUPPLY CURRENT vs. DAC UPDATE RATE

2x INTERPOLATION, f

500

450

400

350

300

250

200

150

SUPPLY CURRENT (mA)

100

50

0

100 300

f

DAC

OUT

1.8V TOTAL

3.3V TOTAL

(MHz)

= -18dBFS

OUT8

= 5MHz

250200150

3.0

2.5

MAX5898 toc13

2.0

1.5

1.0

DNL (LSB)

0.5

0

-0.5

-1.0

500

450

MAX5898 toc16

400

350

300

250

200

150

SUPPLY CURRENT (mA)

100

50

0

DIFFERENTIAL NONLINEARITY

vs. DIGITAL INPUT CODE

0 65,536

DIGITAL INPUT CODE

49,15232,76816,384

SUPPLY CURRENT vs. DAC UPDATE RATE

(MHz)

OUT

= 5MHz

400300200

4x INTERPOLATION, f

1.8V TOTAL

3.3V TOTAL

100 500

f

DAC

5.0

4.0

MAX5898 toc14

3.0

2.0

1.0

INL (LSB)

-1.0

-2.0

-3.0

-4.0

-5.0

500

450

MAX5898 toc17

400

350

300

250

200

150

SUPPLY CURRENT (mA)

100

50

INTEGRAL NONLINEARITY

vs. DIGITAL INPUT CODE

0

0 65,536

DIGITAL INPUT CODE

49,15232,76816,384

SUPPLY CURRENT vs. DAC UPDATE RATE

(MHz)

OUT

= 5MHz

400300200

8x INTERPOLATION, f

1.8V TOTAL

3.3V TOTAL

0

100 500

f

DAC

MAX5898 toc15

MAX5898 toc18

MAX5898

16-Bit, 500Msps, Interpolating and Modulating

Dual DAC with Interleaved LVDS Inputs

_______________________________________________________________________________________

9

Typical Operating Characteristics (continued)

(DV

DD1.8

= AV

DD1.8

= 1.8V, AV

CLK

= AV

DD3.3

= DV

DD3.3

= 3.3V, DATACLK output mode, external reference, V

REFIO

= +1.25V,

R

LOAD

= 50Ω double-terminated, I

OUTFS

= 20mA, TA= +25°C, unless otherwise noted.)

NOISE DENSITY vs. DAC UPDATE RATE

= 16MHz, A

f

OUT

-100

-110

-120

-130

4x INTERPOLATION

-140

-150

NOISE DENSITY (dBFS/Hz)

-160

2x INTERPOLATION

-170

-180

100 200 300 400 500

= -12dBFS, 10MHz OFFSET

OUT

8x INTERPOLATION

f

(MHz)

DAC

WCDMA ACLR SPECTRAL PLOT

= 61.44Mwps, 8x INTERPOLATION

f

DATA

-20

-30

-40

-50

-60

-70

-80

-90

OUTPUT POWER (dBm)

-100

-110

-120

ACLR2 = 78dB

ACLR1 = 77dB

f

CENTER

SPAN = 25.5MHz

= 61.44MHz

ACLR1 = 76dB

CARRIER = -11dBm

ACLR2 = 77dB

WCDMA ACLR vs. OUTPUT FREQUENCY

= 122.88Mwps, 4x INTERPOLATION

f

DATA

100

ONE-CARRIER
ALTERNATE CHANNEL

90

MAX5898 toc19

80

70

ACLR (dB)

FOUR-CARRIER

60

ALTERNATE CHANNEL

50

40

0 30.72 61.44 92.16 122.88 153.60

ONE-CARRIER
ADJACENT CHANNEL

FOUR-CARRIER
ADJACENT CHANNEL

f

(MHz)

CENTER

FOUR-CARRIER WCDMA ACLR SPECTRAL PLOT

= 61.44Mwps, 8x INTERPOLATION

f

DATA

-20

-30

MAX5898 toc22

-40

-50

-60

-70

-80

-90

OUTPUT POWER (dBm)

-100

-110

-120

ACLR2 = 74dB

ACLR1 = 72dB

f

CENTER

CARRIER = -17dBm

= 61.44MHz

SPAN = 40.6MHz

MAX5898 toc20

MAX5898 toc23

ACLR2 = 71dB

ACLR1 = 71dB

WCDMA ACLR vs. OUTPUT FREQUENCY

= 76.8Mwps, 4x INTERPOLATION

f

DATA

100

ONE-CARRIER
ALTERNATE CHANNEL

90

80

70

ACLR (dB)

FOUR-CARRIER

60

ALTERNATE CHANNEL

50

40

0 15.36 30.72 46.08 61.44 76.80 92.16 107.50

ONE-CARRIER
ADJACENT CHANNEL

FOUR-CARRIER
ADJACENT CHANNEL

f

(MHz)

CENTER

WCDMA ACLR SPECTRAL PLOT
= 122.88Mwps, 4x INTERPOLATION

f

DATA

-20

-30

-40

-50

-60

-70

-80

-90

OUTPUT POWER (dBm)

-100

-110

-120

ACLR2 = 70dB

ACLR1 = 68dB

f

CENTER

SPAN = 25.5MHz

CARRIER = -12dBm

= 122.88MHz

ACLR2 = 70dB

ACLR1 = 68dB

MAX5898 toc21

MAX5898 toc24

FOUR-CARRIER WCDMA ACLR SPECTRAL PLOT

= 122.88Mwps, 4x INTERPOLATION

f

DATA

-20

-30

-40

-50

-60

-70

-80

-90

OUTPUT POWER (dBm)

-100

-110

-120

ACLR2 = 65dB

ACLR1 = 64dB

CARRIER = -20dBm

f

= 122.88MHz

CENTER

SPAN = 40.6MHz

MAX5898 toc25

ACLR2 = 63dB

ACLR1 = 63dB

MAX5898

16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs

10 ______________________________________________________________________________________

Pin Description

PIN NAME FUNCTION

1 CLKP Noninverting Differential Clock Input. Internally biased to AV

2 CLKN Inverting Differential Clock Input. Internally biased to AV

3 N.C. Internally Connected. Do not connect.
4 DATACLKP LVDS Data Clock Input/Output. External 100Ω termination to DATACLKN required.
5 DATACLKN Complementary LVDS Data Clock Input/Output. External 100Ω termination to DATACLKP required.

6, 21, 30, 37 DV

7 SELIQN

DD1.8

Digital Power Supply. Accepts a 1.71V to 1.89V supply range. Bypass each pin to ground with a

0.1µF capacitor as close to the pin as possible.

Complementary LVDS Channel Select Input. Set SELIQN low and SELIQP high to direct data to
the channel. Set SELIQP low and SELIQN high to direct data to the channel. Internal 110Ω
termination to SELIQP.

CLK

CLK

/ 2.

/ 2.

8 SELIQP

9 D15N Complementary LVDS Data Bit 15 (MSB). Internal 110Ω termination to D15P.
10 D15P LVDS Data Bit 15 (MSB). Internal 110Ω termination to D15N.
11 D14N Complementary LVDS Data Bit 14. Internal 110Ω termination to D14P.
12 D14P LVDS Data Bit 14. Internal 110Ω termination to D14N.
13 D13N Complementary LVDS Data Bit 13. Internal 110Ω termination to D13P.
14 D13P LVDS Data Bit 13. Internal 110Ω termination to D13N.
15 D12N Complementary LVDS Data Bit 12. Internal 110Ω termination to D12P.
16 D12P LVDS Data Bit 12. Internal 110Ω termination to D12N.
17 D11N Complementary LVDS Data Bit 11. Internal 110Ω termination to D11P.
18 D11P LVDS Data Bit 11. Internal 110Ω termination to D11N.
19 D10N Complementary LVDS Data Bit 10. Internal 110Ω termination to D10P.
20 D10P LVDS Data Bit 10. Internal 110Ω termination to D10N.
22 D9N Complementary LVDS Data Bit 9. Internal 110Ω termination to D9P.
23 D9P LVDS Data Bit 9. Internal 110Ω termination to D9N.
24 D8N Complementary LVDS Data Bit 8. Internal 110Ω termination to D8P.
25 D8P LVDS Data Bit 8. Internal 110Ω termination to D8N.
26 D7N Complementary LVDS Data Bit 7. Internal 110Ω termination to D7P.
27 D7P LVDS Data Bit 7. Internal 110Ω termination to D7N.
28 D6N Complementary LVDS Data Bit 6. Internal 110Ω termination to D6P.
29 D6P LVDS Data Bit 6. Internal 110Ω termination to D6N.
31 D5N Complementary LVDS Data Bit 5. Internal 110Ω termination to D5P.
32 D5P LVDS Data Bit 5. Internal 110Ω termination to D5N.
33 D4N Complementary LVDS Data Bit 4. Internal 110Ω termination to D4P.
34 D4P LVDS Data Bit 4. Internal 110Ω termination to D4N.

LVDS Channel Select Input. Set SELIQN low and SELIQP high to direct data to the channel. Set
SELIQP low and SELIQN high to direct data to the channel. Internal 110Ω termination to SELIQN.

MAX5898

16-Bit, 500Msps, Interpolating and Modulating

Dual DAC with Interleaved LVDS Inputs

______________________________________________________________________________________ 11

Pin Description (continued)

PIN NAME FUNCTION

35 D3N Complementary LVDS Data Bit 3. Internal 110Ω termination to D3P.
36 D3P LVDS Data Bit 3. Internal 110Ω termination to D3N.
38 D2N Complementary LVDS Data Bit 2. Internal 110Ω termination to D2P.
39 D2P LVDS Data Bit 2. Internal 110Ω termination to D2N.
40 D1N Complementary LVDS Data Bit 1. Internal 110Ω termination to D1P.
41 D1P LVDS Data Bit 1. Internal 110Ω termination to D1N.
42 D0N Complementary LVDS Data Bit 0 (LSB). Internal 110Ω termination to D0P.
43 D0P LVDS Data Bit 0 (LSB). Internal 110Ω termination to D0N.

44 DV

45 DOUT Serial-Port Data Output

46 DIN Serial-Port Data Input

47 SCLK Serial-Port Clock Input. Data on DIN is latched on the rising edge of SCLK.
48 CS Serial-Port Interface Select. Drive CS low to enable serial-port interface.
49 RESET Reset Input. Hold RESET low during power-up.

50 REFIO Reference Input/Output. Bypass to ground with a 1µF capacitor as close to the pin as possible.

51 DACREF

52 FSADJ

53, 67 AV

54, 56, 59, 61,

64, 66

55, 60, 65 AV

57 OUTQN Inverting Differential DAC Current Output for Q Channel

58 OUTQP Noninverting Differential DAC Current Output for Q Channel

62 OUTIN Inverting Differential DAC Current Output for I Channel

63 OUTIP Noninverting Differential DAC Current Output for I Channel

68 AV

— EP Exposed Paddle. Must be connected to GND through a low-impedance path.

DD3.3

DD1.8

GND Ground

DD3.3

CLK

I/O Power Supply. Accepts a 3.0V to 3.6V supply range. Bypass with a 0.1µF capacitor as close to
the pin as possible.

C ur r ent- S et Resi stor Retur n P ath. For a 20m A ful l - scal e outp ut cur r ent, use a 1.25V exter nal r efer ence
and connect a 2kΩ r esi stor b etw een FS AD J and D AC RE F. Inter nal l y connected to GN D . D O NO T U SE

A S AN EXT ER N A L GR O U N D C O N N EC T IO N .

Full-Scale Adjust Input. For a 20m A ful l - scal e outp ut cur r ent, use a 1.25V exter nal r efer ence and
connect a 2kΩ r esi stor b etw een FS AD J and D AC RE F.

Low Analog Power Supply. Accepts a 1.71V to 1.89V supply range. Bypass each pin to GND with
a 0.1µF capacitor as close to the pin as possible.

Analog Power Supply. Accepts a 3.135V to 3.465V supply range. Bypass each pin to GND with a

0.1µF capacitor as close to the pin as possible.

Clock Power Supply. Accepts a 3.135V to 3.465V supply range. Bypass to ground with a 0.1µF
capacitor as close to the pin as possible.

MAX5898

16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs

12 ______________________________________________________________________________________

Detailed Description

The MAX5898 dual, 500Msps, high-speed, 16-bit, cur­rent-output DAC provides superior performance in com­munication systems requiring low-distortion analog-signal
reconstruction. The MAX5898 combines two DAC cores
with 8x/4x/2x programmable digital interpolation filters, a
digital quadrature modulator, an SPI-compatible serial
interface for programming the device, and an on-chip

1.2V reference. Individual DAC channel gain and offset
adjustments are available to compensate for downstream
signal-path imbalances. The full-scale output current
range is adjustable from 2mA to 20mA to optimize power
dissipation and gain control.

Each channel contains three selectable interpolating fil­ters making the MAX5898 capable of 2x, 4x, 8x, or no
interpolation, which allows for low input data rates and
high DAC update rates. When operating in 8x interpola­tion mode, the interpolator increases the DAC conversion

rate by a factor of eight, providing an eight-fold increase
in separation between the reconstructed waveform spec­trum and its first image. The MAX5898 accepts either
two’s complement or offset binary input data format on a
single interleaved LVDS input bus.

The MAX5898 includes modulation modes at fIM/ 2 and
fIM/ 4, where fIMis the data rate at the input of the mod­ulator. If 2x interpolation is used, this data rate is 2x the
input data rate. If 4x or 8x interpolation is used, this data
rate is 4x the input data rate. Table 1 summarizes the
modulator operating data rates.

The power-down modes can be used to turn off each
DAC’s output current or the entire digital section.
Programming both DACs into power-down simultane­ously powers down the digital interpolation filters. Note
that the SPI section is always active.

The analog and digital sections of the MAX5898 have
separate power-supply inputs (AV

DD3.3

, AV

DD1.8

,

Functional Diagram

D0–D15

DATACLK

SELIQ

RESET

DATA SYNCH

AND DEMUX

MODULATOR

INTERPOLATING

FILTER

2x

INTERPOLATING

FILTER

2x

MUX

CONTROL REGISTERS

SERIAL INTERFACE

DOUT DIN CS SCLK DACREF FSADJ REFIO

FILTER

FILTER

MUX

INTERPOLATING

INTERPOLATING

2x

MUX

I

Q

f

/ 2, f

/ 4

IM

IM

I

MUX

2x

/2/2

Q

REFERENCE

DIGITAL

INTERPOLATING

FILTER

MUX

2x

∑

MAX5898

INTERPOLATING

MUX

MUX

FILTER

2x

CLOCK BUFFERS

AND DIVIDERS

∑

OFFSET

ADJUST

MUX

∑

DIGITAL

OFFSET

ADJUST

MUX

∑

MUX

/2/2

f

CLK

CLKPCLKN

IDAC

QDAC

DIGITAL
GAIN
ADJUST

OUTIP

OUTIN

f

DAC

DIGITAL
GAIN
ADJUST

OUTQP

OUTQN

f

DAC

MAX5898

16-Bit, 500Msps, Interpolating and Modulating

Dual DAC with Interleaved LVDS Inputs

______________________________________________________________________________________ 13

AV

CLK

, DV

DD3.3

, and DV

DD1.8

), which minimize noise

coupling from one supply to the other. AV

DD1.8

and

DV

DD1.8

operate from a typical 1.8V supply, and all

other supply inputs operate from a typical 3.3V supply.

Serial Interface

The SPI-compatible serial interface programs the
MAX5898 registers. The serial interface consists of CS,
DIN, SCLK, and DOUT. Data is shifted into DIN on the
rising edge of SCLK when CS is low. When CS is high,
data presented at DIN is ignored and DOUT is in high­impedance mode. Note: CS must transition high
after each read/write operation. DOUT is the serial
data output for reading registers to facilitate easy
debugging during development. DIN and DOUT can
be connected together to form a 3-wire serial interface
bus or remain separate and form a 4-wire SPI bus.

The serial interface supports two-byte transfer in a
communication cycle. The first byte is a control byte
written to the MAX5898 only. The second byte is a data
byte and can be written to or read from the MAX5898.
When writing to the MAX5898, data is shifted into DIN;
data is shifted out of DOUT in a read operation. Bits 0 to
3 of the control byte are the address bits. These bits set
the address of the register to be written to or read from.
Bits 4 to 6 of the control byte must always be set to 0.
Bit 7 is a read/write bit: 0 for write operation and 1 for
read operation. The most significant bit (MSB) is shifted
in first in default mode. If the serial port is set to LSB-first
mode, both the control byte and data byte are shifted LSB
first. Figures 1 and 2 show the SPI serial-interface opera­tion in the default write and read mode, respectively.
Figure 3 is a timing diagram for the SPI serial interface.

Table 1. Quadrature Modulator Operating Data Rates (fIMis the Data Rate at the Input of
the Modulator)

Figure 1. SPI Serial-Interface Write Cycle, MSB-First Mode

INTERPOLATION RATE MODULATION MODE (fLO)

1x

2x

4x

8x

fIM / 2 f

f

/ 4 f

IM

fIM / 2 f

f

/ 4 f

IM

fIM / 2 f

/ 4 f

f

IM

fIM / 2 f

/ 4 f

f

IM

MODULATION FREQUENCY

RELATIVE TO f

DAC

DAC

DAC

DAC

DAC

DAC

DAC

DAC

DAC

/ 2 f

/ 4 f

/ 2 f

/ 4 f

/ 2 2 x f

/ 4 f

/ 4 2 x f

/ 8 f

MODULATION FREQUENCY

RELATIVE TO f

DATA

DATA

DATA

DATA

/ 2

/ 4

DATA

/ 2

DATA

DATA

DATA

DATA

CS

SCLK

DIN

DOUT

0 0 0 0 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

HIGH IMPEDANCE

MAX5898

16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs

14 ______________________________________________________________________________________

Figure 2. SPI Serial-Interface Read Cycle, MSB-First Mode

Figure 3. SPI Serial-Interface Timing Diagram

CS

SCLK

DIN

DOUT

READ CYCLE N - 1

ADDRESS DATA

10003210

HIGH

IMPEDANCE

IGNORED

DATA N - 2

t

SS

CS

SCLK

t

SDS

DIN

READ CYCLE N

ADDRESS DATA

10003210

HIGH

IMPEDANCE

t

SDH

IGNORED

DATA N - 1

READ CYCLE N + 1

ADDRESS DATA

10003210

HIGH

IMPEDANCE

IGNORED

DATA N

t

SDV

DOUT

MAX5898

16-Bit, 500Msps, Interpolating and Modulating

Dual DAC with Interleaved LVDS Inputs

______________________________________________________________________________________ 15

Programming Registers

Programming its registers with the SPI serial interface
sets the MAX5898 operation modes. Table 2 shows all

of the registers. The following are descriptions of each
register.

Table 2. MAX5898 Programmable Registers

Conditions in bold are power-up defaults.

ADD BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

00h Unused

Interpolation Rate
(Bit 7, Bit 6)
00 = No interpolation

01h

01 = 2x interpolation
10 = 4x interpolation

11 = 8x interpolation

0 = Two’s­complement
input data

02h

1 = Offset
binary input
data

03h Unused

04h 8-Bit IDAC Fine-Gain Adjustment (see the Gain Adjustment section). Bit 7 is MSB and bit 0 is LSB. Default: 00h

05h Unused

10-Bit IDAC Offset Adjustment (see the Offset Adjustment section). Bits 7 to 0 of the 06h register are the MSB bits. Bit 1 and bit 0 are the LSB

06h

bits in the 07h register. Default: 000h

IDAC IOFFSET
Direction

0 = Current on

07h

OUTIN

1 = Current on
OUTIP

08h 8-Bit QDAC Fine-Gain Adjustment (see the Gain Adjustment section). Bit 7 is MSB and bit 0 is LSB. Default: 00h

09h Unused

10-Bit QDAC Offset Adjustment (see the Offset Adjustment section). Bits 7 to 0 of the 0Ah register are the MSB bits. Bit 1 and bit 0 are the

0Ah

LSB bits in the 0Bh register. Default: 000h

QDAC
IOFFSET
Direction

0 = Current on

0Bh

OUTQN

1 = Current on
OUTQP

0Ch Reserved, do not write to these bits.

0Dh Reserved, do not write to these bits.

0Eh Reserved, do not write to these bits.

0 = MSB first

1 = LSB first

Unused Unused

Unused

Unused

Software Reset

0 = Normal

1 = Reset all
registers

Third
Interpolation
Filter
Configuration

0 = Lowpass

1 = Highpass

Interpolator
Power-Down

0 = Normal

1 = Power-down

Modulation Mode
(Bit 4, Bit 3)
00 = Modulation off
01 = f

/ 2

IM

/ 4

10 = f

IM

11 = f

/ 4

IM

0 = Input data
latched on
rising clock
edge

1 = Input data
latched on falling
clock edge

IDAC Power­Down

0 = Normal

1 = Power-down

0 = Data clock
output disabled

1 = Data clock
output enabled

4-Bit IDAC Coarse-Gain Adjustment (see the Gain Adjustment
section). Bit 3 is MSB and bit 0 is LSB. Default: Fh

4-Bit QDAC Coarse-Gain Adjustment (see the Gain Adjustment
section). Bit 3 is MSB and bit 0 is LSB. Default: Fh

QDAC Power­Down

0 = Normal

1 = Power-down

Mixer Modulation
Mode
0 = Complex

1 = Real

Data
Synchronizer
Disable

0 = Enabled

1 = Disabled

Unused

Modulation
Sign

-jω

0 = e

+jω

1 = e

Unused

IDAC Offset
Adjustment
Bit 1
(see the 06h
register)

QDAC Offset
Adjustment
Bit 1
(see the 0Ah
register)

Unused

IDAC Offset
Adjustment
Bit 0
(see the 06h
register)

QDAC Offset
Adjustment
Bit 0
(see the 0Ah
register)

MAX5898

16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs

16 ______________________________________________________________________________________

Address 00h

Bit 6 Logic 0 (default) causes the serial port to use

MSB first address/data format. When set to a
logic 1, the serial port uses LSB first address/
data format.

Bit 5 When set to a logic 1 (default = 0), all registers

reset to their default state (this bit included).

Bit 4 Logic 1 (default = 0) stops the clock to the

digital interpolators. DAC outputs hold last
value prior to interpolator power-down.

Bit 3 IDAC power-down mode. A logic 1 (default = 0)

to this bit shuts down the output current from
the IDAC.

Bit 2 QDAC power-down mode. A logic 1 (default = 0)

to this bit shuts down the output current from
the QDAC.

Note: If both bit 2 and bit 3 are 1, the MAX5898 is in
full-power-down mode, leaving only the serial interface
active.

Address 01h

Bits 7, 6 Configure the interpolation filters according

to the following:

00 1x (no interpolation)

01 2x

10 4x

11 8x (default)

Bit 5 Logic 0 configures FIR3 as a lowpass digital

filter (default). A logic 1 configures FIR3 as a
highpass digital filter.

Bits 4, 3 Configure the modulation frequency accord-

ing to the following:

00 No modulation

01 fIM/ 2 modulation

10 fIM/ 4 modulation (default)

11 fIM/ 4 modulation

where fIMis the data rate at the input of the
modulator.

Bit 2 Configures the modulation mode for either

real or complex (image reject) modulation.
Logic 1 sets the modulator to the real mode
(default). Complex modulation is only avail­able for f

IM

/ 4 modulation.

Bit 1 Quadrature modulator sign inversion. With I-

channel data leading Q-channel data by 90°,
logic 0 sets the complex modulation to be
e

-jw

(default), cancelling the upper image. A
logic 1 sets the complex modulation to be
e

+jw

, cancelling the lower image.

Address 02h

Bit 7 Logic 0 (default) configures the data port for

two’s complement. A logic 1 configures the
data ports for offset binary.

Bit 4 Logic 0 (default) sets the internal latches to

latch the data on the rising edge of DATACLK.
A logic 1 sets the internal latches to latch the
data on the falling edge of DATACLK.

Bit 3 Logic 0 (default) configures the DATACLK

pin (pin 4 or pin 5) to be an input. A logic 1
configures the DATACLK pin to be an output.

Bit 2 Logic 0 (default) enables the data synchro-

nizer circuitry. A logic 1 disables the data
synchronizer circuitry.

Address 04h

Bits 7–0 These 8 bits define the binary number for

fine-gain adjustment of the IDAC full-scale
current (see the

Gain Adjustment

section). Bit

7 is the MSB. Default is all zeros.

Address 05h

Bits 3–0 These four bits define the binary number for

the coarse-gain adjustment of the IDAC full­scale current (see the

Gain Adjustment

sec-

tion). Bit 3 is the MSB. Default is all ones.

Address 06h, Bits 7–0; Address 07h, Bit 1 and Bit 0

These 10 bits represent a binary number that
defines the magnitude of the offset added to
the IDAC output (see the

Offset Adjustment

section). Default is all zeros.

MAX5898

16-Bit, 500Msps, Interpolating and Modulating

Dual DAC with Interleaved LVDS Inputs

______________________________________________________________________________________ 17

Address 07h

Bit 7 Logic 0 (default) adds the 10 bits offset cur-

rent to OUTIN. A logic 1 adds the 10 bits off­set current to OUTIP.

Address 08h

Bits 7–0 These 8 bits define the binary number for

fine-gain adjustment of the QDAC full-scale
current (see the

Gain Adjustment

section). Bit

7 is the MSB. Default is all zeros.

Address 09h

Bits 3–0 These four bits define the binary number for

the coarse-gain adjustment of the QDAC full­scale current (see the

Gain Adjustment

sec-

tion). Bit 3 is the MSB. Default is all ones.

Address 0Ah, Bits 7–0; Address 0Bh, Bit 1 and Bit 0

These 10 bits represent a binary number that
defines the magnitude of the offset added to
the QDAC output (see the

Offset Adjustment

section). Default is all zeros.

Address 0Bh

Bit 7 Logic 0 (default) adds the 10 bits offset to

OUTQN. A logic 1 adds the 10 bits offset to
OUTQP.

Offset Adjustment

Offset adjustment is achieved by adding a digital code to
the DAC inputs. The code OFFSET (see equation below),
as stored in the relevant control registers, has a range
from 0 to 1023 and a sign bit. The applied DAC offset
is four times the code stored in the register, providing an
offset adjustment range of ±4092 LSB codes. The resolu­tion is 4 LSB.

Gain Trim

Gain adjustment is peformed by varying the full-scale
current according to the following formula:

where I

REF

is the reference current (see the

Reference

Input/Output

section). COARSE is the register content
of registers 05h and 09h for the I and Q channel,
respectively. FINE is the register content of register 04h
and 08h for the I and Q channel, respectively. The
range of COARSE is from 0 to 15, with 15 being the

default. The range for FINE is from 0 to 255 with 0
being the default. The gain can be adjusted in steps of
approximately 0.01dB.

Data Input Port

The MAX5898 captures input data on a single LVDS
port (D15P/N–D0P/N). The channel for the input data is
determined through the state of SELIQP/SELIQN. When
SELIQP is set to logic-high and SELIQN is set to logic­low the input data is presented to the I channel. Setting
SELIQP to logic-low and SELIQN to logic-high presents
the input data to the Q channel.

The MAX5898 control registers can be programmed to
allow either signed or unsigned binary format (bit 7,
address 02h) data. Table 3 shows the corresponding DAC
output levels when using signed or unsigned data modes.

Data Synchronization Modes

Data synchronization circuitry is provided to allow oper­ation with an input data clock. The data clock must be
frequency locked to the DAC clock (f

DAC

), but can
have arbitrary phase with respect to the DAC clock.
The synchronization circuitry allows for phase jitter on
the input data clock of up to ±1 data clock cycles.
Synchronization is initially established when the reset
pin is asynchronously deasserted and the input data
clock has been running for at least four clock cycles.
Subsequently, the MAX5898 monitors the phase rela­tionship and detects if the phase drifts more than ±1
data clock cycle. If this occurs, the synchronizer auto­matically re-establishes synchronization. However, dur­ing the resynchronization phase, up to 8 data words
may be lost or repeated.

Bit 2 of register 02h disables or enables (default) the
automatic data clock phase detection. Disabling the
data synchronization circuitry requires the data clock
and the DAC clock phase to be locked.

Table 3. DAC Output Code Table

I

OFFSET OUTFS

=

××4

16

2

I

OFFSET

⎡
⎢
⎣

I

OUTFS

I

×

3

⎛
⎜

⎝

⎞

COARSE

⎛

REF REF

⎜

⎟

⎝

⎠

4

16

+

1

⎞
⎟

⎠

3

⎛

−

⎜
⎝

×

I

32 256

⎞
⎟

⎠

FINE

⎛
⎜

⎝

⎤

1024

⎛

⎞

=

⎜

⎟

⎥

⎝

⎠

24

⎦

⎞
⎟

⎠

D IG IT A L IN PU T C O D E

O F F SET
B IN A R Y

( U N SI G N ED )

0000 0000 0000 0000 1000 0000 0000 0000 0 I

0111 1111 1111 1111 0000 0000 0000 0000

1111 1111 1111 1111 0111 1111 1111 1111 I

T WO ' S

C O M PL EM EN T

( SI G N ED )

O U T _ PO U T _ N

OU T FS

I

/2I

OU T FS

OU T FS

OU T FS

2

0

/

MAX5898

16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs

18 ______________________________________________________________________________________

DATACLK Modes

The MAX5898 employs a differential LVDS DATACLK
located at pins 4 and 5. The DATACLK can be config­ured as either an input or as an output (bit 3, address
02h). If DATACLK is configured as an output, it is fre­quency-divided from the CLKP/CLKN input, depending
on the operating mode, see Table 4.

The MAX5898 can be configured to latch the input
data on either the rising edge or falling edge of the
DATACLK signal (bit 4, address 02h). Figure 4 shows
the timing requirements between the DATACLK signal
and the input data bus with latching on the rising edge.

Table 4. Clock Frequency Ratios in
Various Modes

Figure 4. Data-Input Timing Diagram

t

D

t

DS

CLKP–CLKN

DATACLKP–DATACLKN

SELIQ

D0–D15

t

DH

INTERPOLATION

RATE

1x 1:1 1:2

2x 1:1 1:1

4x 1:2 1:1

8x 1:4 1:1

f

DATA:fCLK

f

DAC:fCLK

MAX5898

16-Bit, 500Msps, Interpolating and Modulating

Dual DAC with Interleaved LVDS Inputs

______________________________________________________________________________________ 19

Interpolating Filter

The MAX5898 features three cascaded FIR half-band
filters. The interpolating filters are enabled or disabled
in combinations to support 1x (no interpolation), 2x, 4x,
or 8x interpolation. Bits 7 and 6 of register 01h set the
interpolation rate (see Table 2). The last interpolation fil-

ter is located after the modulator. In the 8x interpolation
mode, the last filter (FIR3) can be configured as low­pass or highpass (bit 5, address 01h) to select the
lower or upper sideband from the modulation output.
The frequency responses of these three filters are plot­ted in Figures 5–8.

Figure 5. Interpolation Filter Frequency Response, 2x
Interpolation Mode

Figure 6. Interpolation Filter Frequency Response, 4x
Interpolation Mode

Figure 7. Interpolation Filter Frequency Response, 8x
Interpolation Mode (FIR3 Lowpass Mode)

0

0234

f

OUT

- NORMALIZED TO INPUT DATA RATE

5678

-20

-40

-60

-80

-100

GAIN (dBFS)

-120
1

0

0.1

0.2

0.3

0.4

-0.0004

-0.0002

0

PASSBAND DETAIL

Figure 8. Interpolation Filter Frequency Response, 8x
Interpolation Mode (FIR3 Highpass Mode)

0

-20

-40

-60

-0.0002

-0.0004

GAIN (dBFS)

-80

-100

-120

0.2

0 0.4 0.6 0.8

f

- NORMALIZED TO INPUT DATA RATE

OUT

PASSBAND DETAIL

0

0.3

0.2

0.1

0

1.0 1.2 1.4 1.6 1.8 2.0

0.4

0

-20

-40

-60

-0.0002

-0.0004

GAIN (dBFS)

-80

-100

-120

0.5

0 1.0 1.5 2.0

- NORMALIZED TO INPUT DATA RATE

f

OUT

PASSBAND DETAIL

0

0.4

0.3

0

0.2

0.1

2.5 3.0 3.5 4.0

0

-20

-40

-60

GAIN (dBFS)

-0.0002

-0.0004

PASSBAND DETAIL

0

3.6 3.8 4.0 4.2 4.4

-80

-100

-120
1

0234

f

- NORMALIZED TO INPUT DATA RATE

OUT

5678

MAX5898

16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs

20 ______________________________________________________________________________________

The programmable interpolation filters multiply the
MAX5898 input data rate by a factor of 2x, 4x, or 8x to
separate the reconstructed waveform spectrum and the
DAC image. The original spectral images, appearing at
around multiples of the input data rate, are attenuated
by the internal digital filters. This feature provides three
benefits:

1) Image separation reduces complexity of analog
reconstruction filters.

2) Lower input data rates eliminate board-level high­speed data transmission.

3) Sin(x)/x rolloff is reduced over the effective bandwidth.

Figure 9 illustrates a practical example of the benefits
when using the MAX5898 in 2x, 4x, and 8x interpolation
modes with the third filter configured as a lowpass filter.
With no interpolation filter, the first image signal appears
in the second Nyquist zone between fS/ 2 and fS. The first
interpolating filter removes this image. In fact, all of the

Figure 9. Spectral Representation of Interpolating Filter Responses (Output Frequencies are Relative to the Data Input Frequency, fS)

FILTER

IMAGE

IMAGE

RESPONSE

3f

S

3f

S

3f

S

INPUT
SPECTRUM
AND FIRST
FILTER
RESPONSE

OUTPUT
SPECTRUM
OF THE
FIRST
FILTER

INPUT
SPECTRUM
AND
SECOND
FILTER
RESPONSE

SIGNAL

SIGNAL

SIGNAL

IMAGE

f

S

f

S

f

S

2f

S

2f

S

2f

S

NO INTERPOLATION

4f

S

4f

S

4f

S

5f

S

5f

S

5f

S

FILTER
RESPONSE

6f

S

6f

S

6f

S

7f

S

7f

S

7f

S

8f

S

2x INTERPOLATION

8f

S

8f

S

OUTPUT
SPECTRUM
OF THE
SECOND
FILTER

INPUT
SPECTRUM
AND THIRD
FILTER
RESPONSE

OUTPUT
SPECTRUM
OF THE
THIRD
FILTER

SIGNAL

SIGNAL

SIGNAL

IMAGE

f

S

f

S

f

S

2f

S

2f

S

2f

S

FILTER
RESPONSE

3f

S

3f

S

3f

S

4f

S

4f

S

4f

S

IMAGE

5f

S

5f

S

5f

S

6f

S

6f

S

6f

S

7f

S

7f

S

IMAGE

7f

S

4x INTERPOLATION

8f

S

8f

S

8x INTERPOLATION

8f

S

MAX5898

16-Bit, 500Msps, Interpolating and Modulating

Dual DAC with Interleaved LVDS Inputs

______________________________________________________________________________________ 21

images at odd numbers of fSare filtered. At the output of
the first filter, the images are at 2fS, 4fS, etc. This signal is
then passed to the second interpolating filter, which is
similar to the first filter and removes the images at 2fS, 6fS,

10fS, etc. Finally, the third filter removes images at 4fS,
12fS, 20fS, etc. Figures 10, 11, and 12 similarly illustrate
the spectral responses when using the interpolating filters
combined with the digital modulator.

Figure 10. Spectral Representation of 4x Interpolation Filter with fIM/ 4 Modulation (Output Frequencies are Relative to the Data Input
Frequency, f

S

)

INPUT
SPECTRUM
AND FIRST
FILTER
RESPONSE

OUTPUT
SPECTRUM
OF THE
FIRST
FILTER

INPUT
SPECTRUM
AND
SECOND
FILTER
RESPONSE

SIGNAL

SIGNAL

SIGNAL

f

f

f

IMAGE

S

S

FILTER
RESPONSE

S

FILTER

RESPONSE

2f

S

IMAGE

2f

S

IMAGE

2f

S

3f

S

3f

S

3f

S

NO INTERPOLATION

4f

S

2x INTERPOLATION

4f

S

4f

S

OUTPUT
SPECTRUM
OF THE
SECOND
FILTER

OUTPUT
SPECTRUM
OF THE
MODULATOR

SIGNAL

f

S

SIGNAL

LOWER

SIDEBAND

FOR COMPLEX MODULATION THE MODULATION SIGN (BIT 1, ADDRESS 01h) SELECTS UPPER OR LOWER SIDEBAND

UPPER
SIDEBAND

f

S

2f

S

2f

S

3f

S

IMAGE

3f

S

IMAGE

4x INTERPOLATION

4f

S

4f

S

MAX5898

16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs

22 ______________________________________________________________________________________

Figure 11. Spectral Representation of 8x Interpolation Filter with fIM/ 4 Modulation and Lowpass Mode Enabled (Output Frequencies
are Relative to the Data Input Frequency, f

S

)

INPUT

SIGNAL

SPECTRUM
AND FIRST
FILTER
RESPONSE

OUTPUT
SPECTRUM
OF THE
FIRST
FILTER

INPUT
SPECTRUM

SIGNAL

AND
SECOND
FILTER
RESPONSE

OUTPUT

SIGNAL

SPECTRUM
OF THE
SECOND
FILTER

SIGNAL

FILTER

IMAGE

f

S

2f

S

RESPONSE

3f

S

4f

S

5f

S

6f

S

7f

S

IMAGE

f

S

2f

S

3f

S

4f

S

5f

S

6f

S

7f

S

NO INTERPOLATION

8f

S

2x INTERPOLATION

8f

S

FILTER

4f

S

4f

S

RESPONSE

IMAGE

5f

S

6f

S

7f

S

8f

S

4x INTERPOLATION

5f

S

6f

S

7f

S

8f

S

IMAGE

f

S

f

S

2f

S

2f

S

3f

S

3f

S

SIGNAL

OUTPUT

LOWER

SIDEBAND

UPPER
SIDEBAND

IMAGE

SPECTRUM
OF THE
MODULATOR

f

S

2f

S

3f

S

4f

S

5f

S

6f

S

7f

S

8f

S

FOR COMPLEX MODULATION THE MODULATION SIGN (BIT 1, ADDRESS 01h) SELECTS UPPER OR LOWER SIDEBAND

FILTER RESPONSE

IMAGE

INPUT
SPECTRUM

SIGNAL

AND THIRD
FILTER
RESPONSE

OUTPUT
SPECTRUM

f

S

SIGNAL

2f

S

3f

S

4f

S

5f

S

6f

S

IMAGE

7f

S

8f

S

8x INTERPOLATION

OF THE
THIRD
FILTER

f

S

2f

S

3f

S

4f

S

5f

S

6f

S

7f

S

8f

S

MAX5898

16-Bit, 500Msps, Interpolating and Modulating

Dual DAC with Interleaved LVDS Inputs

______________________________________________________________________________________ 23

Figure 12. Spectral Representation of 8x Interpolation Filter with fIM/ 4 Modulation and Highpass Mode Enabled (Output Frequencies
are Relative to the Data Input Frequency, f

S

)

INPUT
SPECTRUM
AND FIRST
FILTER
RESPONSE

SIGNAL

FILTER

IMAGE

f

S

2f

S

RESPONSE

3f

S

4f

S

5f

S

6f

S

7f

S

NO INTERPOLATION

8f

S

OUTPUT
SPECTRUM
OF THE
FIRST
FILTER

INPUT
SPECTRUM
AND
SECOND
FILTER
RESPONSE

OUTPUT
SPECTRUM
OF THE
SECOND
FILTER

OUTPUT
SPECTRUM
OF THE
MODULATOR

SIGNAL

SIGNAL

SIGNAL

f

S

f

S

f

S

IMAGE

2f

S

3f

S

4f

S

IMAGE

2f

S

3f

S

4f

S

IMAGE

2f

S

3f

S

4f

S

SIGNAL

LOWER

SIDEBAND

f

S

UPPER
SIDEBAND

IMAGE

2f

S

3f

S

4f

S

MODULATION SIGN (BIT 1, ADDRESS 01h) SELECTS UPPER OR LOWER SIDEBAND

5f

5f

5f

5f

S

S

S

S

FILTER
RESPONSE

2x INTERPOLATION

6f

S

6f

S

7f

S

7f

S

8f

S

8f

S

4x INTERPOLATION

6f

S

6f

S

7f

S

7f

S

8f

S

8f

S

INPUT
SPECTRUM

SIGNAL

IMAGE

FILTER
RESPONSE

AND THIRD
FILTER
RESPONSE

OUTPUT
SPECTRUM

f

S

2f

S

3f

S

SIGNAL

4f

S

5f

S

IMAGE

6f

S

7f

S

8f

S

8x INTERPOLATION

OF THE
THIRD
FILTER

f

S

2f

S

3f

S

4f

S

5f

S

6f

S

7f

S

8f

S

MAX5898

16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs

24 ______________________________________________________________________________________

Digital Modulator

The MAX5898 features digital modulation at frequencies
of fIM/ 2 and fIM/ 4, where fIMis the data rate at the
input to the modulator. fIMequals f

DAC

in 1x, 2x, and 4x

interpolation modes. In 8x interpolation mode, f

IM

equals

f

DAC

/ 2. The output rate of the modulator is always the

same as the input data rate to the modulator, f

IM

.

In complex modulation mode, data from the second
interpolation filter is frequency-mixed with the on-chip
in-phase and quadrature (I/Q) local oscillator (LO).
Complex modulation provides the benefit of image
sideband rejection.

In the fLO= fIM/ 4 mode, real or complex modulation
can be used. The modulator multiplies successive input
data samples by the sequence [1, 0, -1, 0] for a cos(ωt).
The modulator modulates the input signal up to f

IM

/ 4,

creating upper and lower images around fIM/ 4. The
quadrature LO sin(ωt) is realized by delaying the cos(ωt)
sequence by one clock cycle. Using complex modula­tion, complex IF is generated. The complex IF combined
with an external quadrature modulator provides image
rejection. The sign of the LO can be changed to allow
the user to select whether the upper or the lower image
should be rejected (bit 1 of register 01h).

When fIM/ 2 is chosen as the LO frequency, the input
signal is multiplied by [-1, 1] on both channels. This pro­duces images around fIM/ 2. The complex image-reject
modulation mode is not available for this LO frequency.

The outputs of the modulator can be expressed as:

in complex modulation, e

+jwt

in complex modulation, e

-jwt

For real modulation, the outputs of the modulator can
be expressed as:

where ω = 2 x π x fLO.

If more than one MAX5898 is used, their LO phases
can be synchronized by simultaneously releasing
RESET. This sets the MAX5898 to its predefined initial
phase.

Device Reset

The MAX5898 can be reset by holding the RESET pin
low for 10ns. This will program the control registers to
their default values in Table 2. During power-on, RESET
must be held low until all power supplies have stabi­lized. Alternately, programming bit 5 of address 00h to
a logic-high also resets the MAX5898.

Figure 13. (a) Modulator in Complex Modulation Mode; (b) Modulator in Real Modulation Mode

II Q

tt t t t

()=()×() ()×()

OD ID ID

QI Q

=

tt t t t

()

OD ID ID

sin cos

()×()+()×()

II Q

tt t t t

()=()×()+()×()

OD ID ID

QI Q

()

OD ID ID

cos sin

=

tt t t t

sin cos

()×()+()×()

− cos sin

ωω

ωω

ωω

ωω

II

tt t

()=()×()

OD ID

QQ

()

OD ID

cos

=

tt t

cosωω

()×()

I-CHANNEL
INPUT DATA

cos(ωt)

sin(ωt)

sin(ωt)

Q-CHANNEL
INPUT DATA

cos(ωt)

(a)

∑

∑

I-CHANNEL
OUTPUT DATA

TO
FIR3

Q-CHANNEL
OUTPUT DATA

I-CHANNEL
INPUT DATA

Q-CHANNEL
INPUT DATA

cos(ωt)

sin(ωt)

sin(ωt)

cos(ωt)

I-CHANNEL

∑

OUTPUT DATA

TO
FIR3

Q-CHANNEL

∑

OUTPUT DATA

(b)

MAX5898

16-Bit, 500Msps, Interpolating and Modulating

Dual DAC with Interleaved LVDS Inputs

______________________________________________________________________________________ 25

Power-Down Mode

The MAX5898 features three power-saving modes.
Each DAC can be individually powered down through
bits 2 and 3 of address 00h. The interpolation filters can
also be powered down through bit 4 of address 00h,
preserving the output level of each DAC (the DACs
remain powered). Powering down both DACs automati­cally puts the MAX5898 into full power-down, including
the interpolation filters.

Applications Information

Frequency Planning

System designers need to take the DAC into account
during frequency-planning for high-performance appli­cations. Proper frequency planning can ensure that
optimal system performance is achieved. The
MAX5898 is designed to deliver excellent dynamic per­formance across wide bandwidths, as required for
communication systems. As with all DACs, some com­binations of output frequency and update rate produce
better performance than others.

Harmonics are often folded down into the band of inter­est. Specifically, if the DAC outputs a frequency close
to fS/ N, the Mth harmonic of the output signal will be
aliased down to:

Thus, if N ≈ (M + 1), the Mth harmonic will be close to
the output frequency. SFDR performance of a current­steering DAC is often dominated by 3rd-order harmonic
distortion. If this is a concern, placing the output signal
at a frequency other than fS/ 4 should be considered.

Common to interpolating DACs are images near the
divided clocks. In a DAC configured for 4x interpolation,
this applies to images around fS/ 4 and fS/ 2. In a DAC
configured for 8x interpolation, this applies to images
around fS/ 8, fS/ 4, and fS/ 2. Most of these images
are not part of the in-band (0 to f

DATA

/ 2) SFDR specifi­cation, though they are a consideration for out-of-band
(f

DATA

/ 2 to f

DAC

/ 2) SFDR and may depend on the
relationship of the DATACLK to DAC update clock (see
the

Data Clock

section). When specifying the output
reconstruction filter for other than baseband signals,
these images should not be ignored.

Data Clock

The MAX5898 features synchronizers that allow for arbi­trary phase alignment between DATACLK and
CLKP/CLKN. The DATACLK causes internal switching in
the MAX5898 and the phase between DATACLK (input
mode) to CLKP/CLKN influences the images at DATACLK.
Figure 14 shows the image level near DATACLK as a
function of the DATACLK (input mode) to CLKP/CLKN
phase at 500Msps, 4x interpolation for a 10MHz, -6dBFS
output signal.

Clock Interface

The MAX5898 features a flexible differential clock input
(CLKP, CLKN) with a separate supply (AV

CLK

) to
achieve optimum jitter performance. Use an ultra-low
jitter clock to achieve the required noise density. Clock
jitter must be less than 0.5ps

RMS

to meet the specified
noise density. For that reason, the CLKP/CLKN input
source must be designed carefully. The differential
clock (CLKN and CLKP) input can be driven from a sin­gle-ended or a differential clock source. Differential
clock drive is required to achieve the best dynamic
performance from the DAC. For single-ended opera­tion, drive CLKP with a low noise source and bypass
CLKN to GND with a 0.1µF capacitor.

The CLKP and CLKN pins are internally biased to
AV

CLK

/ 2. This allows the user to AC-couple clock

Figure 14. Effect of CLKP/CLKN to DATACLK Phase on fS/ 4
Images

−

NM

⎡

ff Mf f

=×=

−

S OUT S

⎤

⎢

⎥

N

⎣

⎦

fS / 4 IMAGES vs. CLKP/CLKN to DATACLK DELAY

= 125Mwps, 4x INTERPOLATION

f

DATA

-70
f

= 10MHz

OUT

= -6dBFS

A

OUT

-75

-80

fS / 4 + f

OUT

-85

-90

IMAGE LEVEL (dBc)

fS / 4 - f

OUT

-95

-100
08

CLKP/CLKN DELAY (s)

fS / 4 - f

fS / 4 + f

OUT

OUT

642

MAX5898

16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs

26 ______________________________________________________________________________________

sources directly to the device without external resistors
to define the DC level. The input resistance of CLKP
and CLKN is 5kΩ.

A convenient way to apply a differential signal is with a
balun transformer as shown in Figure 15. Alternatively,
these inputs may be driven from a CMOS-compatible
clock source, however it is recommended to use sine-

wave or AC-coupled differential ECL/PECL drive for best
dynamic performance.

Output Interface (OUTI, OUTQ)

The MAX5898 outputs complementary currents (OUTIP,
OUTIN, OUTQP, and OUTQN) that can be utilized in a
differential configuration. Load resistors convert these
two output currents into a differential output voltage.

The differential output between OUTIP (OUTQP) and
OUTIN (OUTQN) can be converted to a single-ended
output using a transformer or a differential amplifier.
Figure 16 shows a typical transformer-based applica­tion circuit for generation of IF output signals. In this
configuration, the MAX5898 operates in differential
mode, which reduces even-order harmonics, and
increases the available output power. Pay close atten­tion to the transformer core saturation characteristics
when selecting a transformer. Transformer core satura­tion can introduce strong second harmonic distortion,
especially at low output frequencies and high signal
amplitudes. It is recommended to connect the trans­former center tap to ground.

Figure 15. Single-Ended-to-Differential Clock Conversion Using
a Balun Transformer

Figure 16. Differential-to-Single-Ended Conversion Using Wideband RF Transformers

MINI-CIRCUITS

SINGLE-ENDED

IINPUT

ADTL1-12

1:1 RATIO

24.9

24.9

100nF

CLKP

Ω

MAX5898

Ω

100nF

CLKN

OUTIP

Ω

50

V

, SINGLE-ENDED

IOUT

1:1

IDAC

16

OUTIN

MAX5898

OUTQP

QDAC

16

OUTQN

100

50

50

100

50

Ω

1:1

Ω

Ω

1:1

Ω

1:1

Ω

, SINGLE-ENDED

V

QOUT

MAX5898

16-Bit, 500Msps, Interpolating and Modulating

Dual DAC with Interleaved LVDS Inputs

______________________________________________________________________________________ 27

If a transformer is not used, the outputs must have a
resistive termination to ground. Figure 17 shows the
MAX5898 output configured for differential DC-coupled
mode. The DC-coupled configuration can be used to
eliminate waveform distortion due to highpass filter
effects. Applications include communication systems
employing analog quadrature upconverters and requir­ing a high-speed DAC for baseband I/Q synthesis.

If a single-ended DC-coupled unipolar output is desir­able, OUTIP (OUTQP) should be selected as the out­put, and connect OUTIN (OUTQN) to ground. Using
the MAX5898 output single-ended is not recommended
because it introduces additional noise and distortion.

The distortion performance of the DAC also depends
on the load impedance. The MAX5898 is optimized for
a 50Ω double termination. It can be used with a trans­former output as shown in Figure 16 or just one 25Ω
resistor from each output to ground and one 50Ω resis­tor between the outputs (Figure 17). Higher output ter­mination resistors can be used, as long as each output
voltage does not exceed +1V with respect to GND, but
at the cost of degraded distortion performance and
increased output noise voltage.

Reference Input/Output

The MAX5898 supports operation with the on-chip 1.2V
bandgap reference or an external reference voltage
source. REFIO serves as the input for an external, low­impedance reference source, and as the output if the
DAC is operating with the internal reference.

For stable operation with the internal reference, REFIO
should be decoupled to GND with a 1µF capacitor.

REFIO must be buffered with an external amplifier,
if heavy loading is required, due to its 10kΩ output
resistance.

Alternatively, apply a temperature-stable external refer­ence to REFIO (Figure 18). The internal reference is over­driven by the external reference. For improved accuracy
and drift performance, choose a fixed output voltage ref­erence such as the MAX6520 bandgap reference.

The MAX5898’s reference circuit (Figure 19) employs a
control amplifier, designed to regulate the full-scale
current I

OUT

for the differential current outputs of the

DAC. The output current can be calculated as:

I

OUTFS

= 32 x I

REF

x 65,535 / 65,536

where I

REF

is the reference output current (I

REF

= V

REFIO

/

R

SET

) and I

OUTFS

is the full-scale output current of the

DAC. Located between FSADJ and DACREF, R

SET

is the
reference resistor, which determines the amplifier’s output
current for the DAC. See Table 5 for a matrix of different
I

OUTFS

and R

SET

selections.

Power Supplies, Bypassing,

Decoupling, and Layout

Grounding and power-supply decoupling strongly influ­ence the MAX5898 performance. Unwanted digital
crosstalk can couple through the input, reference,
power-supply, and ground connections, which can
affect dynamic specifications like signal-to-noise ratio
or spurious-free dynamic range. In addition, electro­magnetic interference (EMI) can either couple into or
be generated by the MAX5898. Observe the grounding
and power-supply decoupling guidelines for high­speed, high-frequency applications. Follow the power­supply and filter configuration guidelines to achieve
optimum dynamic performance.

Using a multilayer printed-circuit board (PCB) with sep­arate ground and power-supply planes, run high-speed
signals on lines directly above the ground plane. Since
the MAX5898 has separate analog and digital sections,
the PCB should include separate analog and digital

Figure 17. DC-Coupled Differential Output Configuration

Ω

25

OUTIP

IDAC

16

OUTIN

MAX5898

OUTQP

QDAC

16

OUTQN

Ω

50

Ω

25

Ω

25

Ω

50

Ω

25

MAX5898

16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs

28 ______________________________________________________________________________________

ground sections with only one point connecting the
three planes at the exposed paddle under the
MAX5898. Run digital signals above the digital ground
plane and analog/clock signals above the analog/clock
ground plane. Keep digital signals as far away from
sensitive analog inputs, reference lines, and clock
inputs as practical. Use a symmetric design of clock
input and the analog output lines to minimize 2nd-order
harmonic distortion components, thus optimizing the
dynamic performance of the DAC. Keep digital signal
paths short and run lengths matched to avoid propaga­tion delay and data skew mismatches.

The MAX5898 requires five separate power-supply
inputs for the analog (AV

DD1.8

and AV

DD3.3

), digital

(DV

DD1.8

and DV

DD3.3

), and clock (AV

CLK

) circuitry.

Decouple each voltage supply pin with a separate

0.1µF capacitor as close to the device as possible and
with the shortest possible connection to the appropriate
ground plane. Minimize the analog and digital load
capacitances for optimized operation. Decouple all
power-supply voltages at the point they enter the PCB
with tantalum or electrolytic capacitors. Ferrite beads
with additional decoupling capacitors forming a pi-net­work could also improve performance.

The exposed paddle MUST be soldered to the ground.

Use multiple vias, an array of at least 4 x 4 vias, directly
under the EP to provide a low thermal and electrical
impedance path for the IC.

Figure 18. Typical External Reference Circuit

Figure 19. Internal Reference Architecture

Table 5. I

OUTFS

and R

SET

Selection Matrix Based on a Typical 1.20V Reference Voltage

*

Terminated into a 50Ωload.

1.2V

REFERENCE

EXTERNAL

1.25V

REFERENCE

REFIO

1µF

FSADJ

I

REF

R

SET

DACREF

FULL-SCALE

CURRENT

I

OUTFS

2 62.50 19.2 19.1 100

5 156.26 7.68 7.5 250

10 312.50 3.84 3.83 500

15 468.75 2.56 2.55 750

20 625.00 1.92 1.91 1000

(mA)

REFERENCE

CURRENT

I

REF

1.2V

REFERENCE

10kΩ

MAX5898

CURRENT-

SOURCE

ARRAY DAC

1µF

10kΩ

REFIO

FSADJ

I

REF

R

SET

DACREF

MAX5898

CURRENT-

SOURCE

ARRAY DAC

R

(kΩ)

(µA)

SET

CALCULATED 1% EIA STD

OUTPUT VOLTAGE

V

IOUTP/N

* (mV

P-P

)

MAX5898

16-Bit, 500Msps, Interpolating and Modulating

Dual DAC with Interleaved LVDS Inputs

______________________________________________________________________________________ 29

Static Performance Parameter

Definitions

Integral Nonlinearity (INL)

Integral nonlinearity is the deviation of the values on an
actual transfer function from either a best-straight-line
fit (closest approximation to the actual transfer curve)
or a line drawn between the end points of the transfer
function, once offset and gain errors have been nulli­fied. For a DAC, the deviations are measured at every
individual step.

Differential Nonlinearity (DNL)

Differential nonlinearity is the difference between an
actual step height and the ideal value of 1 LSB. A DNL
error specification greater than -1 LSB guarantees a
monotonic transfer function.

Offset Error

The offset error is the difference between the ideal and
the actual offset current. For a DAC, the offset point is
the average value at the output for the two midscale
digital input codes with respect to the full scale of the
DAC. This error affects all codes by the same amount.

Gain Error

A gain error is the difference between the ideal and the
actual full-scale output voltage on the transfer curve,
after nullifying the offset error. This error alters the slope
of the transfer function and corresponds to the same
percentage error in each step.

Dynamic Performance

Parameter Definitions

Settling Time

The settling time is the amount of time required from the
start of a transition until the DAC output settles its new
output value to within the specified accuracy.

Noise Spectral Density

The DAC output noise is the sum of the quantization
noise and thermal noise. Noise spectral density is the
noise power in a 1Hz bandwidth, specified in dBFS/Hz.

Signal-to-Noise Ratio (SNR)

For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog output (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
maximum SNR can be derived from the DAC’s resolu­tion (N bits):

SNR

dB

= 6.02dBx N + 1.76

dB

However, noise sources such as thermal noise, refer­ence noise, clock jitter, etc., affect the ideal reading.
Therefore, SNR is computed by taking the ratio of the
RMS signal to the RMS noise, which includes all spec­tral components minus the fundamental, the first four
harmonics, and the DC offset.

Spurious-Free Dynamic Range (SFDR)

SFDR is the ratio of the RMS amplitude of the carrier
frequency (maximum signal components) to the RMS
value of their next largest distortion component. SFDR
is usually measured in dBc with respect to the carrier
frequency amplitude or in dBFS with respect to the
DAC’s full-scale range. Depending on its test condition,
SFDR is observed within a predefined window or
to Nyquist.

Two-/Four-Tone Intermodulation

Distortion (IMD)

The two-/four-tone IMD is the ratio expressed in dBc (or
dBFS) of the worst 3rd-order (or higher) IMD products to
any output tone.

Adjacent Channel Leakage

Power Ratio (ACLR)

Commonly used in combination with WCDMA, ACLR
reflects the leakage power ratio in dB between the
measured powers within a channel relative to its adja­cent channel. ACLR provides a quantifiable method of
determining out-of-band spectral energy and its influ­ence on an adjacent channel when a bandwidth-limited
RF signal passes through a nonlinear device.

MAX5898

16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs

30 ______________________________________________________________________________________

Pin Configuration

TOP VIEW

CLKP

CLKN

N.C.

DATACLKP

DATACLKN

D

VDD1.8

SELIQN

SELIQP

D15N

D15P

D14N

D14P

D13N

D13P

D12N

D12P

D11N 17

DD1.8

AV

D10N

GND

656667

D10P

DD3.3

GND

AV

OUTIP

64

2322212019 2726252418 2928 323130

D9P

D9N

DD1.8

DV

CLK

AV

68

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

EXPOSED PADDLE

D11P

OUTIN

GND

MAX5898

D8P

D8N

QFN

DD3.3

AV

D7N

GND

D7P

OUTQP

5859606162 5455565763

D6N

OUTQN

D6P

GND

DD1.8

DV

DD3.3

AV

D5N

GND

D5P

DD1.8

AV

D4N

5253

3433

FSADJ

D4P

51

50

49

48 CS

47

46

45

44

43

42

41

40

39

38

37

36

35

DACREF

REFIO

RESET

SCLK

DIN

DOUT

DV

DD3.3

D0P

D0N

D1P

D1N

D2P

D2N

DV

DD1.8

D3P

D3N

MAX5898

16-Bit, 500Msps, Interpolating and Modulating

Dual DAC with Interleaved LVDS Inputs

______________________________________________________________________________________ 31

Package Information

For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.

PACKAGE TYPE PACKAGE CODE OUTLINE NO.

LAND

PATTERN NO.

68 QFN (10mm x 10mm) G6800+4

21-0122

—

MAX5898

16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs

32 ______________________________________________________________________________________

Package Information (continued)

For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.

MAX5898

16-Bit, 500Msps, Interpolating and Modulating

Dual DAC with Interleaved LVDS Inputs

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________

33

© 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

Revision History

REVISION

NUMBER

0 8/05 Initial release —

1 7/07 Add note to EC Table, style edits

2 8/10 Update Absolute Maximum Ratings 1, 2, 32

REVISION

DATE

DESCRIPTION

PAGES

CHANGED

1, 2, 4, 5, 27,

28, 31