MAXIM MAX5898 Technical data

General Description

The MAX5898 programmable interpolating, modulating, 500Msps, dual digital-to-analog converter (DAC) offers superior dynamic performance and is optimized for highperformance wideband, single- and multicarrier transmit applications. The device integrates a selectable 2x/4x/8x interpolating filter, a digital quadrature modulator, and dual 16-bit, high-speed DACs on a single integrated circuit. At 30MHz output frequency and 500Msps update rate, the in-band SFDR is 81dBc, while only consuming

1.2W. The device also delivers 71dB ACLR for fourcarrier WCDMA at a 61.44MHz output frequency.

The selectable interpolating filters allow lower input data rates while taking advantage of the high DAC update rates. These linear-phase interpolation filters ease reconstruction filter requirements and enhance the passband dynamic performance. Each channel includes offset and gain programmability, allowing the user to calibrate out local oscillator (LO) feedthrough and sideband suppression errors generated by analog quadrature modulators.

The MAX5898 features a f

/ 4 digital image-reject modulator. This modulator generates a quadrature-modulated IF signal that can be presented to an analog I/Q modulator to complete the upconversion process. A second digital modulation mode allows the signal to be frequency-translated with image pairs at fIM/ 2 or fIM/ 4.

The MAX5898 features a standard LVDS interface for low electromagnetic interference (EMI). Interleaved data is applied through a single 16-bit bus. A 3.3V SPI™ port is provided for mode configuration. The programmable modes include the selection of 2x/4x/8x interpolating filters, fIM/ 2, fIM/ 4 or no digital quadrature modulation with image rejection, individual channel gain and offset adjustment, and offset binary or two’scomplement data interface.

Compatible versions with CMOS interfaces and 12-, 14-, and 16-bit resolutions are also available. Refer to the MAX5893 data sheet for 12-bit CMOS, MAX5894 for 14bit CMOS, and the MAX5895 for 16-bit CMOS versions.

Applications

Base Stations: 3G Multicarrier UMTS, CDMA, and GSM

Broadband Wireless Transmitters

Broadband Cable Infrastructure

Instrumentation and Automatic Test Equipment (ATE)

Analog Quadrature Modulation Architectures

Features

o 71dB ACLR at f

OUT

= 61.44MHz (Four-Carrier

WCDMA)

o Meets Multicarrier UMTS, cdma2000

, GSM

Spectral Masks (f

OUT

= 122MHz)

o Noise Spectral Density = -160dBFS/Hz at

OUT

= 16MHz

o 90dBc SFDR at Low-IF Frequency (10MHz) o 88dBc SFDR at High-IF Frequency (50MHz) o Low Power: 831mW (f

CLK

= 250MHz)

o User Programmable

Selectable 2x, 4x, or 8x Interpolating Filters

< 0.01dB Passband Ripple

> 95dB Stopband Rejection Selectable Real or Complex Modulator Operation Selectable Modulator LO Frequency: OFF, fIM/ 2, or fIM/ 4 Selectable Output Filter: Lowpass or Highpass Per Channel Gain and Offset Adjustment

o EV Kit Available (Order the MAX5898EVKIT)

MAX5898

16-Bit, 500Msps, Interpolating and Modulating

Dual DAC with Interleaved LVDS Inputs

________________________________________________________________

Maxim Integrated Products

Selector Guide

Ordering Information

Simplified Diagram

19-3756; Rev 2; 8/10

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Pin Configuration appears at end of data sheet.

SPI is a trademark of Motorola, Inc. cdma2000 is a registered trademark of Telecommunications Industry Association.

Denotes a lead(Pb)-free/RoHS-compliant package.

EP = Exposed paddle.

D = Dry pack

EVALUATION KIT

AVAILABLE

PART TEMP RANGE PIN-PACKAGE

M AX 5898E GK+ D -40°C to +85°C

M AX 5898E GK- D -40°C to +85°C

68 QFN-EP* (10mm x 10mm)

PART

MAX5893 12 500 CMOS

MAX5894 14 500 CMOS

MAX5895 16 500 CMOS

MAX5898 16 500 LVDS

RESOLUTION

(BITS)

DAC UPDATE

RATE (Msps)

FILTERS

INTERPOLATING

1x/2x/4x

DATA SYNCH

DATA PORT

DATACLK

AND DEMUX

MODULATOR

FILTERS

INTERPOLATING

DAC

INPUT

LOGIC

OUTI

OUTQ

MAX5898

16-Bit, 500Msps, Interpolating and Modulating Dual DAC with Interleaved LVDS Inputs

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(DV

DD1.8

= AV

DD1.8

= 1.8V, AV

CLK

= AV

DD3.3

= DV

DD3.3

= 3.3V, modulator off, 2x interpolation, DATACLK output mode, output is

50Ω double-terminated, external reference at 1.25V, T

= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C,

unless otherwise noted.) (Note 2)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

DD1.8

, AV

DD1.8

to GND, DACREF ..................-0.3V to +2.16V

DD3.3

, AV

CLK

, DV

DD3.3

to GND, DACREF........-0.3V to +3.9V

DATACLKP, DATACLKN, D0P–D15P,

D0N–D15N, SELIQP, SELIQN to GND,

DACREF ..........................................-0.3V to (DV

DD1.8

+ 0.3V)

CS, RESET, SCLK, DIN, DOUT to

GND, DACREF ................................-0.3V to (DV

DD3.3

+ 0.3V)

CLKP, CLKN to GND, DACREF..............-0.3V to (AV

CLK

+ 0.3V)

REFIO, FSADJ to GND, DACREF ........-0.3V to (AV

DD3.3

+ 0.3V)

OUTIP, OUTIN, OUTQP,

OUTQN to GND, DACREF..................-1V to (AV

DD3.3

+ 0.3V)

DOUT, DATACLKP, DATACLKN Continuous Current ..........8mA

Continuous Power Dissipation (T

= +70°C) 68-Pin QFN (derate 41.7mW/°C above +70°C)

(Note 1) ...................................................................3333.3mW

Junction Temperature......................................................+150°C

Operating Temperature Range ...........................-40°C to +85°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

Soldering Temperature (reflow) .......................................+260°C

Note 1: Thermal resistance based on a multilayer board with 4 x 4 via array in exposed paddle area.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

STATIC PERFORMANCE

Resolution 16 Bits

Differential Nonlinearity DNL ±1 LSB

Integral Nonlinearity INL ±3 LSB

Offset Error OS -0.02 ±0.003 +0.02 %FS

Offset Drift ±0.03 ppm/°C

Gain Error GE

(Note 3) -4 ±0.06 +4 %FS

Gain-Error Drift ±110 ppm/°C

Full-Scale Output Current I

OUTFS

(Note 3) 2 20 mA

Output Compliance -0.5 +1.1 V

Output Resistance R

Output Capacitance C

OUT

DYNAMIC PERFORMANCE

Maximum Clock Frequency f

Minimum Clock Frequency f

Maximum DAC Update Rate f

Minimum DAC Update Rate f

Maximum Data Clock Frequency f

Maximum Input Data Rate f

CLK

DAC

DATACLK

DATA

= f

DAC

CLK

= f

DAC

CLK

Interleaved data 250 MHz

Per channel 125 MWps

= 125Mwps,

DATA

= 16MHz, f

OUT

= 10MHz, -12dBFS

Noise Spectral Density

= 125Mwps,

DATA

= 16MHz, f

OUT

= 10MHz, 0dBFS

1MΩ

5pF

500 MHz

or f

DAC

= f

/ 2 500 Msps

CLK

= f

/ 2 10 Msps

CLK

No interpolation -156

OFFSET

2x interpolation -157

4x interpolation -157

OFFSET

4x interpolation -154

10 MHz

dBFS/

MAX5898

16-Bit, 500Msps, Interpolating and Modulating

Dual DAC with Interleaved LVDS Inputs

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(DV

DD1.8

= AV

DD1.8

= 1.8V, AV

CLK

= AV

DD3.3

= DV

DD3.3

= 3.3V, modulator off, 2x interpolation, DATACLK output mode, output is

50Ω double-terminated, external reference at 1.25V, T

= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C,

unless otherwise noted.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

In-Band SFDR (DC to f

DATA

/ 2)

SFDR

Two-Tone IMD TTIMD

DATA

= 125Mwps,

interpolation off,

-0.1dBFS

= 125Mwps,

DATA

2x interpolation,

-0.1dBFS

= 125Mwps,

DATA

4x interpolation,

-0.1dBFS

= 125Mwps,

DATA

= 9MHz, f

OUT1

10MHz, -6.1dBFS

= 125Mwps,

DATA

= 79MHz,

OUT1

= 80MHz,

OUT2

-6.1dBFS

= 62.5Mwps,

DATA

= 9MHz, f

OUT1

10MHz, -6.1dBFS

OUT2

= 10MHz 90

OUT

= 30MHz 84

OUT

= 50MHz 77

OUT

= 10MHz 79 89

OUT

= 30MHz 83

OUT

= 50MHz 92

OUT

= 10MHz 89

OUT

= 30MHz 83

OUT

= 50MHz 89

OUT

No interpolation -96

2x interpolation -99

4x interpolation -95

2x interpolation,

/ 4 complex

modulation

4x interpolation, f

/ 4 complex

modulation

8x interpolation -94

dBc

-81

-71

dBc

Four-Tone IMD FTIMD

ACLR for WCDMA (Note 4)

ACLR

= 62.5Mwps,

DATA

= 69MHz, f

OUT1

OUT2

= 70MHz, -6.1dBFS

= 62.5Mwps,

DATA

= 179MHz, f

OUT1

= 180MHz, -6.1dBFS

= 125Mwps, f

DATA

OUT2

spaced 1MHz

OUT

8x interpolation, f

/ 4 complex

modulation

8x, highpass interpolation, f

/ 4 complex

modulation

apart from 32MHz, -12dBFS, 2x interpolation

= 61.44Mwps,

DATA

= baseband

OUT

= 122.88Mwps,

DATA

= 61.44MHz

OUT

= 122.88Mwps,

DATA

= 122.88MHz

OUT

4x interpolation 79

8x interpolation 79

2x interpolation,

/ 4 complex

modulation

4x interpolation, f

/ 4 complex

modulation

-71

-89 dBc

MAX5898

16-Bit, 500Msps, Interpolating and Modulating Dual DAC with Interleaved LVDS Inputs

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(DV

DD1.8

= AV

DD1.8

= 1.8V, AV

CLK

= AV

DD3.3

= DV

DD3.3

= 3.3V, modulator off, 2x interpolation, DATACLK output mode, output is

50Ω double-terminated, external reference at 1.25V, T

= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C,

unless otherwise noted.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output Propagation Delay t

Output Rise Time t

Output Fall Time t

RISE

FALL

1x interpolation (Note 5) 2.9 ns

10% to 90% (Note 6) 0.75 ns

10% to 90% (Note 6) 1 ns

Output Settling Time To 0.5% (Note 6) 11 ns

Output Bandwidth -1dB bandwidth (Note 7) 240 MHz

Passband Width Ripple < -0.01dB

Stopband Rejection

0.604 x f

, 2x interpolation 100

DATA

, 4x interpolation 100

DATA

, 8x interpolation 100

DATA

0.4 x

DATA

1x interpolation 22

Data Latency

2x interpolation 70

4x interpolation 146

8x interpolation 311

DAC INTERCHANNEL MATCHING

Gain Match ∆Gain f

Gain-Match Tempco ∆Gain/°C I

Phase Match ∆Phase f

Phase-Match Tempco ∆Phase/°C I

DC Gain Match I

Crosstalk f

= DC - 80MHz, I

OUT

= 20mA ±0.02 ppm/°C

OUTFS

= 60MHz, I

OUT

= 20mA ±0.006 Deg/°C

OUTFS

= 20mA (Note 3) -0.2 ±0.04 +0.2 dB

OUTFS

= 50MHz, f

OUT

OUTFS

DAC

= 20mA ±0.1 dB

OUTFS

= 20mA ±0.13 Deg

= 250MHz -95 dB

REFERENCE

Reference Input Range 0.12 1.32 V

Reference Output Voltage V

Reference Input Resistance R

REFIO

Internal reference 1.14 1.2 1.28 V

10 kΩ

Reference Voltage Drift ±50 ppm/°C

CMOS LOGIC INPUTS (SCLK, CS, RESET, DIN)

Input High Voltage V

Input Low Voltage V

Input Current I

Input Capacitance C

0.7 x

DD3.3

0.3 x

DD3.3

-10 ±0.1 +10 µA

3pF

CMOS LOGIC OUTPUT (DOUT)

Output High Voltage V

Output Low Voltage V

LOAD

SINK

= 200µA

0.8 x

DD3.3

0.2 x

DD3.3

Output Leakage Current Tri-state 1 µA

Clock

Cycles

MAX5898

16-Bit, 500Msps, Interpolating and Modulating

Dual DAC with Interleaved LVDS Inputs

_______________________________________________________________________________________ 5

ELECTRICAL CHARACTERISTICS (continued)

(DV

DD1.8

= AV

DD1.8

= 1.8V, AV

CLK

= AV

DD3.3

= DV

DD3.3

= 3.3V, modulator off, 2x interpolation, DATACLK output mode, output is

50Ω double-terminated, external reference at 1.25V, T

= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C,

unless otherwise noted.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Rise/Fall Time C

= 10pF, 20% to 80% 1.5 ns

LOAD

LVDS LOGIC INPUTS (D15P–D0P, D15N–D0N, SELIQP, SELIQN)

Differential Input Logic High V

Differential Input Logic Low V

Input Common-Mode Voltage V

Differential Input Resistance R

Input Capacitance C

ICM

100 mV

-100 mV

1.125 1.25 1.375 V

110 Ω

2.5 pF

LVDS CLOCK INPUT/OUTPUT (DATACLKP, DATACLKN)

Differential Input Amplitude High V

Differential Input Amplitude Low V

D i ffer enti al Outp ut Am p l i tud e H i g hVOHR

Differential Output Amplitude Low V

Output Common-Mode Voltage V

OCM

Output Rise/Fall Time

= 100Ω d i ffer enti al ( N ote 3) 250 340 mV

LOAD

= 100Ω d i ffer enti al ( N ote 3) -340 -250 mV

LOAD

= 100Ω d i ffer enti al , C

LOAD

= 8pF,

20% to 80%

250 mV

-250 mV

1.25 V

0.9 ns

CLOCK INPUTS (CLKP, CLKN) (Note 8)

Differential Input Voltage Swing V

DIFF

Sine-wave input > 1.5

Square-wave input > 0.5

Differential Input Slew Rate > 100 V/µs

Common-Mode Voltage V

Differential Input Resistance R

Differential Input Capacitance C

COM

CLK

AC-coupled

CLK

5kΩ

5pF

Minimum Clock Duty Cycle 45 %

Maximum Clock Duty Cycle 55 %

CLKP/CLKN, DATACLK TIMING (Figure 4) (Note 9)

CLK to DATACLK Delay t

Data Hold Time t

Data Setup Time t

DATACLK output mode 1.4 ns

1.65 ns

-0.65 ns

SERIAL-PORT INTERFACE TIMING (Figure 3) (Note 9)

SCLK Frequency f CS Setup Time t

Input Hold Time t

Input Setup Time t

Data Valid Duration t

SCLK

SDH

SDS

SDV

2.5 ns

0ns

4.5 ns

6.5 16.5 ns

10 MHz

POWER SUPPLIES

Digital Supply Voltage DV

Digital I/O Supply Voltage DV

DD1.8

DD3.3

1.71 1.8 1.89 V

3.0 3.3 3.6 V

P-P

MAX5898

16-Bit, 500Msps, Interpolating and Modulating Dual DAC with Interleaved LVDS Inputs

6 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(DV

DD1.8

= AV

DD1.8

= 1.8V, AV

CLK

= AV

DD3.3

= DV

DD3.3

= 3.3V, modulator off, 2x interpolation, DATACLK output mode, output is

50Ω double-terminated, external reference at 1.25V, T

= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C,

unless otherwise noted.) (Note 2)

Note 2: All specifications are 100% tested at T

≥ +25°C. Specifications at TA< +25°C are guaranteed by design and characterization.

Note 3: Specification is 100% production tested at T

≥ +25°C.

Note 4: 3.84MHz bandwidth, single carrier. Note 5: Excludes data latency. Note 6: Measured single-ended into a 50Ω load. Note 7: Excludes sin(x)/x rolloff. Note 8: Differential voltage swing defined as

I+ I

Note 9: Guaranteed by design and characterization. Note 10:Parameter defined as the change in midscale output caused by a ±5% variation in the nominal supply voltage.

V(CLKN)

V(CLKP)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Clock Supply Voltage AV

Analog Supply Voltage

AVDD3.3

Analog Supply Current

AVDD1.8

Digital Supply Current I

Digital I/O Supply Current I

Clock Supply Current I

DVDD1.8

DVDD3.3

AVCLK

Total Power Dissipation P

Power-Down Current

AV Ratio

Power-Supply Rejection

DD3.3

PSRR

CLK

DD3.3

DD1.8

TOTAL

3.135 3.3 3.465 V

3.135 3.3 3.465

1.71 1.8 1.89