MAXIM MAX5895 Technical data

General Description

The MAX5895 programmable interpolating, modulating, 500Msps, dual digital-to-analog converter (DAC) offers superior dynamic performance and is optimized for high-performance, wideband single- and multicarrier transmit applications. The device integrates a selectable 2x/4x/8x interpolating filter, a digital quadrature modulator, and dual 16-bit high-speed DACs on a single IC. At 30MHz output frequency and 500Msps update rate, the in-band SFDR is 88dBc while consuming 1.1W. The device also delivers 71dB ACLR for four-carrier WCDMA at a 61.44MHz output frequency.

The selectable interpolating filters allow lower input data rates while taking advantage of the high DAC update rates. These linear-phase interpolation filters ease reconstruction filter requirements and enhance the passband dynamic performance. Individual offset and gain programmability allow the user to calibrate out local oscillator (LO) feedthrough and sideband suppression errors generated by analog quadrature modulators.

The MAX5895 features a f

/4 digital image-reject modulator. This modulator generates a quadrature-modulated IF signal that can be presented to an analog I/Q modulator to complete the upconversion process. A second digital modulation mode allows the signal to be frequency-translated with image pairs at fIM/2 or fIM/4.

The MAX5895 features a standard 1.8V CMOS, 3.3V tolerant data input bus for easy interface. A 3.3V SPI™ port is provided for mode configuration. The programmable modes include the selection of 2x/4x/8x interpolating filters, f

/2, fIM/4 or no digital quadrature modulation with image rejection, channel gain and offset adjustment, and offset binary or two’s complement data interface.

Pin-compatible 12- and 14-bit devices are also available. Refer to the MAX5894 data sheet for the 14-bit version and the MAX5893 data sheet for the 12-bit version.

Applications

Base Stations: 3G Multicarrier UMTS, CDMA, and GSM

Broadband Wireless Transmitters

Broadband Cable Infrastructure

Instrumentation and Automatic Test Equipment (ATE)

Analog Quadrature Modulation Architectures

Features

o 71dB ACLR at f

OUT

= 61.44MHz (Four-Carrier

WCDMA)

o Meets Multicarrier UMTS, cdma2000

, GSM

Spectral Masks (f

OUT

= 122MHz)

o Noise Spectral Density = -158dBFS/Hz at

OUT

= 16MHz

o 92dBc SFDR at Low-IF Frequency (10MHz)

o 90dBc SFDR at High-IF Frequency (50MHz)

o Low Power: 511mW (f

CLK

= 100MHz)

o User Programmable

Selectable 2x, 4x, or 8x Interpolating Filters

< 0.01dB Passband Ripple

> 99dB Stopband Rejection Selectable Real or Complex Modulator Operation Selectable Modulator LO Frequency: OFF, fIM/2, or f

/4 Selectable Output Filter: Lowpass or Highpass Channel Gain and Offset Adjustment

o EV Kit Available (Order the MAX5895 EV Kit)

MAX5895

16-Bit, 500Msps Interpolating and Modulating

Dual DAC with CMOS Inputs

________________________________________________________________

Maxim Integrated Products

Selector Guide

Ordering Information

Simplified Diagram

19-3545; Rev 2; 10/08

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Pin Configuration appears at end of data sheet.

SPI is a trademark of Motorola, Inc. cdma2000 is a registered trademark of the Telecommunications

Industry Association.

D = Dry pack.

EP = Exposed pad.

Denotes a lead-free/RoHS-compliant package.

EVALUATION KIT

AVAILABLE

PART TEMP RANGE PIN-PACKAGE

MAX5895EGK-D -40°C to +85°C 68 QFN-EP*

MAX5895EGK+D -40°C to +85°C 68 QFN-EP*

PART

MAX5893 12 500 CMOS

MAX5894 14 500 CMOS

MAX5895 16 500 CMOS

MAX5898 16 500 LVDS

RESOLUTION

(BITS)

DAC UPDATE

RATE (Msps)

INPUT

LOGIC

DATA

PORT A

DATACLK

DATA

PORT B

DATA SYNCH

AND DEMUX

FILTERS

INTERPOLATING

1x/2x/4x

MODULATOR

FILTERS

INTERPOLATING

DAC

OUTI

OUTQ

MAX5895

16-Bit, 500Msps Interpolating and Modulating Dual DAC with CMOS Inputs

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(DV

DD1.8

= AV

DD1.8

= 1.8V, AV

CLK

= AV

DD3.3

= DV

DD3.3

= 3.3V, modulator off, 2x interpolation, DATACLK input mode, dual-port

mode, 50Ω double-terminated outputs, external reference at 1.25V, T

= -40°C to +85°C, unless otherwise noted. Typical values are

at T

= +25°C, unless otherwise noted.) (Note 2)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

DD1.8

, AV

DD1.8

to GND, DACREF ..................-0.3V to +2.16V

DD3.3

, AV

CLK

, DV

DD3.3

to GND, DACREF........-0.3V to +3.9V

DATACLK, A0–A15, B0–B13,

SELIQ/B15, DATACLK/B14, CS, RESET, SCLK,

SDI and SDO to GND, DACREF......-0.3V to (DV

DD3.3

+ 0.3V)

CLKP, CLKN to GND, DACREF..............-0.3V to (AV

CLK

+ 0.3V)

REFIO, FSADJ to GND, DACREF ........-0.3V to (AV

DD3.3

+ 0.3V)

OUTIP, OUTIN, OUTQP,

OUTQN to GND, DACREF..................-1V to (AV

DD3.3

+ 0.3V)

SDO, DATACLK, DATACLK/B14 Continuous Current ..........8mA

Continuous Power Dissipation (TA= +70°C)

68-Pin QFN (derate 41.7mW/°C above +70°C)

(Note 1) ...................................................................3333.3mW

Junction Temperature......................................................+150°C

Operating Temperature Range ...........................-40°C to +85°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

Thermal Resistance θ

(Note 1)....................................0.8°C/W

Note 1: Thermal resistance based on a multilayer board with 4 x 4 via array in exposed pad area.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

STATIC PERFORMANCE

Resolution 16 Bits

Differential Nonlinearity DNL ±1 LSB

Integral Nonlinearity INL ±3 LSB

Offset Error OS -0.025 ±0.003 +0.025 %FS

Offset Drift ±0.03 ppm/°C

Full-Scale Gain Error GE

Gain-Error Drift ±110 ppm/°C

Full-Scale Output Current I

OUTFS

Output Compliance -0.5 +1.1 V

Output Resistance R

Output Capacitance C

OUT

DYNAMIC PERFORMANCE

Maximum Clock Frequency f

Minimum Clock Frequency f

Maximum DAC Update Rate f

Minimum DAC Update Rate f

Maximum Input Data Rate f

CLK

DAC

DATA

= f

DAC

= f

DAC

DATACLK

= 16MHz, f

OUT

CLK

= 125MHz,

= 10MHz, -12dBFS

Noise Spectral Density

DATACLK

OUT

= 125MHz,

= 16MHz, f

= 10MHz, 0dBFS

-4 ±0.6 +4 %FS

220mA

1MΩ

5pF

500 MHz

or f

= f

/2 500 Msps

CLK

= f

/2 1 Msps

CLK

or f

DAC

125 MWps

No interpolation -157

OFFSET

2x interpolation -158

4x interpolation -157

OFFSET

4x interpolation -149

1 MHz

dBFS/

MAX5895

16-Bit, 500Msps Interpolating and Modulating

Dual DAC with CMOS Inputs

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(DV

DD1.8

= AV

DD1.8

= 1.8V, AV

CLK

= AV

DD3.3

= DV

DD3.3

= 3.3V, modulator off, 2x interpolation, DATACLK input mode, dual-port

mode, 50Ω double-terminated outputs, external reference at 1.25V, T

= -40°C to +85°C, unless otherwise noted. Typical values are

at T

= +25°C, unless otherwise noted.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

In-Band SFDR (DC to f

DATA

/2)

SFDR

Two-Tone IMD TTIMD

DATACLK

= 125MHz,

interpolation off, 0dBFS

DATACLK

= 125MHz,

2x interpolation, 0dBFS

DATACLK

= 125MHz,

4x interpolation, 0dBFS

DATACLK

OUT1

= 125MHz,

= 9MHz, f

OUT2

10MHz, -6.1dBFS

DATACLK

OUT1

= 125MHz,

= 79MHz, f

= 80MHz, -6.1dBFS

DATACLK

OUT1

= 62.5MHz,

= 9MHz, f

OUT2

10MHz, -6.1dBFS

= 10MHz 90

OUT

= 30MHz 85

OUT

= 50MHz 73

OUT

= 10MHz 77 90

OUT

= 30MHz 89

OUT

= 50MHz 86

OUT

= 10MHz 92

OUT

= 30MHz 88

OUT

= 50MHz 90

OUT

No interpolation -103

2x interpolation -103

4x interpolation -103

2x interpolation, f

/4 complex

-74

modulation

OUT2

4x interpolation,

/4 complex

-75

modulation

8x interpolation -100

dBc

Four-Tone IMD FTIMD

ACLR for WCDMA (Note 3)

ACLR

DATACLK

OUT1

= 70MHz, -6.1dBFS

DATACLK

OUT1

= 180MHz, -6.1dBFS

DATACLK

= 62.5MHz,

= 69MHz, f

= 62.5MHz,

= 179MHz, f

= 125MHz, f

OUT2

8x interpolation,

/4 complex

modulation

8x, highpass interpolation, f

/4 complex

modulation

spaced 1MHz

OUT

apart from 32MHz, -12dBFS, 2x interpolation

DATACLK

OUT

DATACLK

= 61.44MHz,

= baseband

122.88MHz, f

61.44MHz

DATACLK

122.88MHz, f

122.88MHz

OUT

4x interpolation 80

8x interpolation 79

2x interpolation, fIM/4 complex modulation

4x interpolation, fIM/4 complex modulation

-75

-65

-97 dBc

MAX5895

16-Bit, 500Msps Interpolating and Modulating Dual DAC with CMOS Inputs

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(DV

DD1.8

= AV

DD1.8

= 1.8V, AV

CLK

= AV

DD3.3

= DV

DD3.3

= 3.3V, modulator off, 2x interpolation, DATACLK input mode, dual-port

mode, 50Ω double-terminated outputs, external reference at 1.25V, T

= -40°C to +85°C, unless otherwise noted. Typical values are

at T

= +25°C, unless otherwise noted.) (Note 2)

Output Propagation Delay t

Output Rise Time t

Output Fall Time t

Output Settling Time To 0.5% (Note 5) 11 ns

Output Bandwidth -1dB bandwidth (Note 6) 240 MHz

Passband Width Ripple < -0.01dB

Stopband Rejection

Data Latency

DAC INTERCHANNEL MATCHING

Gain Match ∆Gain f Gain-Match Tempco ∆Gain/°C I Phase Match ∆Phase f Phase-Match Tempco ∆Phase/°C f

DC Gain Match I

Channel-to-Channel Crosstalk f

REFERENCE

Reference Input Range 0.125 1.250 V

Reference Output Voltage V

Reference Input Resistance R

Reference Voltage Drift ±50 ppm/°C

CMOS LOGIC INPUT/OUTPUT (A15–A0, SELIQ/B15, DATACLK/B14, B13–B0, DATACLK)

Input High Voltage V

Input Low Voltage V

Input Current I

Input Capacitance C

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

RISE

FALL

REFIO

1x interpolation (Note 4) 2.9 ns

10% to 90% (Note 5) 0.75 ns

10% to 90% (Note 5) 1.0 ns

0.604 x f

1x interpolation 22

2x interpolation 70

4x interpolation 146

8x interpolation 311

OUT

OUTFS

OUT

OUTFS

OUT

Internal reference 1.14 1.20 1.27 V

DATA

= DC - 80MHz, I

= 20mA ±0.02 ppm/°C

= 60MHz, I

= 20mA -0.2 ±0.04 +0.2 dB

= 50MHz, f

0.4 x

DATA

, 2x interpolation 100

, 4x interpolation 100

, 8x interpolation 100

= 20mA ±0.1 dB

OUTFS

= 20mA ±0.13 Deg

OUTFS

= 20mA ±0.006 Deg/°C

OUTFS

= 250MHz, 0dBFS -95 dB

DAC

10 kΩ

0.7 x

DD1.8

0.3 x

±1 ±20 µA

3pF

DD1.8

Clock

Cycles

MAX5895

16-Bit, 500Msps Interpolating and Modulating

Dual DAC with CMOS Inputs

_______________________________________________________________________________________ 5

ELECTRICAL CHARACTERISTICS (continued)

(DV

DD1.8

= AV

DD1.8

= 1.8V, AV

CLK

= AV

DD3.3

= DV

DD3.3

= 3.3V, modulator off, 2x interpolation, DATACLK input mode, dual-port

mode, 50Ω double-terminated outputs, external reference at 1.25V, T

= -40°C to +85°C, unless otherwise noted. Typical values are

at T

= +25°C, unless otherwise noted.) (Note 2)

Output High Voltage V

Output Low Voltage V

Output Leakage Current Three-state 1 µA

Rise/Fall Time C

CLOCK INPUT (CLKP, CLKN)

Differential Input Voltage Swing V

Differential Input Slew Rate > 100 V/µs

Common-Mode Voltage V

Input Resistance R

Input Capacitance C

Minimum Clock Duty Cycle 45 %

Maximum Clock Duty Cycle 55 %

CLKP/CLKN, DATACLK TIMING (Figure 4, Notes 7, 8)

CLK to DATACLK Delay t

Data Hold Time, DATACLK Input/Output (Pin 14)

Data Setup Time, DATACLK Input/Output (Pin 14)

Data Hold Time, DATACLK/B14 Input/Output (Pin 27)

Data Setup Time, DATACLK/B14 Input/Output (Pin 27)

SERIAL-PORT INTERFACE TIMING (Figure 3, Note 7)

SCLK Frequency f CS Setup Time t

Input Hold Time t

Input Setup Time t

Data Valid Duration t

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DIFF

COM

CLK

SCLK

SDH

SDS

SDV

200µA load

Sine-wave input > 1.5

Square-wave input > 0.5

AC-coupled AV

DATACLK output mode, C

Capturing rising edge 1.0

Capturing falling edge 2.1

Capturing rising edge 0.4

Capturing falling edge -0.7

Capturing rising edge 1.0

Capturing falling edge 2.3

Capturing rising edge 0.2

Capturing falling edge -0.4

= 10pF, 20% to 80% 1.5 ns

LOAD

0.8 x

D V

D D 3 .3

= 10pF 6.2 ns

LOAD

2.5 ns

0ns

4.5 ns

6.5 16.5 ns

0.2 x

D V

D D 3.3

/2 V

CLK

5kΩ

3pF

10 MHz

P-P

MAX5895

16-Bit, 500Msps Interpolating and Modulating Dual DAC with CMOS Inputs

6 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(DV

DD1.8

= AV

DD1.8

= 1.8V, AV

CLK

= AV

DD3.3

= DV

DD3.3

= 3.3V, modulator off, 2x interpolation, DATACLK input mode, dual-port

mode, 50Ω double-terminated outputs, external reference at 1.25V, T

= -40°C to +85°C, unless otherwise noted. Typical values are

at T

= +25°C, unless otherwise noted.) (Note 2)

Note 2: All specifications are 100% tested at T

≥ +25°C. Specifications at TA< +25°C are guaranteed by design and

characterization data.

Note 3: 3.84MHz bandwidth, single carrier. Note 4: Excludes data latency. Note 5: Measured single-ended into a 50Ω load. Note 6: Excludes sin(x)/x rolloff. Note 7: Guaranteed by design and characterization. Note 8: Setup and hold time specifications characterized with 3.3V CMOS logic levels. Note 9: Parameter defined as the change in midscale output caused by a ±5% variation in the nominal supply voltage.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

POWER SUPPLIES

Digital Supply Voltage DV

Digital I/O Supply Voltage DV

Clock Supply Voltage AV

Analog Supply Voltage

AVDD3.3

Analog Supply Current

AVDD1.8

Digital Supply Current I

Digital I/O Supply Current I

Clock Supply Current I

DVDD1.8

DVDD3.3

AVCLK

Total Power Dissipation P

Power-Down Current

AV Ratio

Power-Supply Rejection

DD3.3

PSRR

DD1.8

DD3.3

CLK

DD3.3

DD1.8

TOTAL

1.71 1.8 1.89 V

3.0 3.3 3.6 V

3.135 3.3 3.465 V

3.135 3.3 3.465

1.71 1.8 1.89

= 250MHz, 2x interpolation, 0dBFS,

CLK

= 10MHz, DATACLK output mode

OUT

= 250MHz, 2x interpolation, 0dBFS,

CLK

= 10MHz, DATACLK output mode

OUT

= 250MHz, 2x interpolation, 0dBFS,

CLK

= 10MHz, DATACLK output mode

OUT

= 250MHz, 2x interpolation, 0dBFS,

CLK

= 10MHz, DATACLK output mode

OUT

= 250MHz, 2x interpolation, 0dBFS,

CLK

= 10MHz, DATACLK output mode

OUT

110 130

27 32

225 250 mA

21 32 mA

35mA

511 mW

DD3.3

DD1.8

DD3.3

CLK

All I/O are static high or low, bit 2 to bit 4 of address 00h are set high

(Note 9) 0.125 %FS/V

450

100

µA

MAX5895

16-Bit, 500Msps Interpolating and Modulating

Dual DAC with CMOS Inputs

_______________________________________________________________________________________

Typical Operating Characteristics

(DV

DD1.8

= AV

DD1.8

= 1.8V, AV

CLK

= AV

DD3.3

= DV

DD3.3

= 3.3V, modulator off, 2x interpolation, output is transformer-coupled to

50Ω load, T

= +25°C, unless otherwise noted.)

SFDR vs. OUTPUT FREQUENCY

= 125MWps, NO INTERPOLATION

DATA

120

100

SFDR (dBc)

-12dBFS

060

-0.1dBFS

OUTPUT FREQUENCY (MHz)

IN-BAND SFDR vs. OUTPUT FREQUENCY

= 125MWps, 2x INTERPOLATION

DATA

SFDR (dBc)

62.5 112.5

-6dBFS

-0.1dBFS -12dBFS

UPPER SIDEBAND MODULATION SPURS MEASURED BETWEEN

62.5MHz AND 125MHz

OUTPUT FREQUENCY (MHz)

-6dBFS

-0.1dBFS

102.592.582.572.5

5040302010

MAX5895 toc01

MAX5895 toc04

120

100

SFDR (dBc)

120

100

SFDR (dBc)

IN-BAND SFDR vs. OUTPUT FREQUENCY

= 125MWps, 2x INTERPOLATION

DATA

-6dBFS

SPURS MEASURED BETWEEN 0MHz AND 62.5MHz

050

-12dBFS

OUTPUT FREQUENCY (MHz)

-0.1dBFS

MAX5895 toc02

40302010

IN-BAND SFDR vs. OUTPUT FREQUENCY

= 125MWps, 4x INTERPOLATION

DATA

-6dBFS

SPURS MEASURED BETWEEN 0MHz AND 62.5MHz

050

OUTPUT FREQUENCY (MHz)

-0.1dBFS

MAX5895 toc05

-12dBFS

40302010

0UT-OF-BAND SFDR vs. OUTPUT FREQUENC

DATA

100

-6dBFS

SFDR (dBc)

SPURS MEASURED BETWEEN

62.5MHz AND 125MHz

050

OUT-OF-BAND SFDR vs. OUTPUT FREQUENCY

DATA

SFDR (dBc)

SPURS MEASURED BETWEEN

62.5MHz AND 250MHz

050

= 125MWps, 2x INTERPOLATION

-0.1dBFS

-12dBFS

40302010

OUTPUT FREQUENCY (MHz)

= 125MWps, 4x INTERPOLATION

-6dBFS

OUTPUT FREQUENCY (MHz)

-0.1dBFS

-12dBFS

40302010

MAX5895 toc03

MAX5895 toc06

IN-BAND SFDR vs. OUTPUT FREQUENCY

100

-6dBFS

SFDR (dBc)

LOWER SIDEBAND MODULATION SPURS MEASURED BETWEEN

62.5MHz AND 125MHz

75 125

OUTPUT FREQUENCY (MHz)

-0.1dBFS

-12dBFS

= 125MWps, 4x INTERPOLATION

DATA

IN-BAND SFDR vs. OUTPUT FREQUENCY

= 125MWps, 4x INTERPOLATION

DATA

-6dBFS

MAX5895 toc07

SFDR (dBc)

UPPER SIDEBAND MODULATION SPURS MEASURED BETWEEN

62.5MHz AND 187.5MHz

1151059585

125 175

OUTPUT FREQUENCY (MHz)

-0.1dBFS

MAX5895 toc08

-12dBFS

165155145135

TWO-TONE IMD vs. OUTPUT FREQUENCY

= 125MWps, NO INTERPOLATION

DATA

120

100

TWO-TONE IMD (-dBc)

1MHz CARRIER SPACING

050

-9dBFS

CENTER FREQUENCY (MHz)

-12dBFS

MAX5895 toc09

-6dBFS

40302010

MAX5895

16-Bit, 500Msps Interpolating and Modulating Dual DAC with CMOS Inputs

8 _______________________________________________________________________________________

Typical Operating Characteristics (continued)

(DV

DD1.8

= AV

DD1.8

= 1.8V, AV

CLK

= AV

DD3.3

= DV

DD3.3

= 3.3V, modulator off, 2x interpolation, output is transformer-coupled to

50Ω load, T

= +25°C, unless otherwise noted.)

TWO-TONE IMD vs. OUTPUT FREQUENCY

= 125MWps, NO INTERPOLATION

DATA

120

100

TWO-TONE IMD (-dBc)

1MHz CARRIER SPACING

050

-12dBFS

MAX5895 toc09

-9dBFS

-6dBFS

40302010

CENTER FREQUENCY (MHz)

TWO-TONE IMD vs. OUTPUT FREQUENCY

= 125MWps, 4x INTERPOLATION

DATA

120

TWO-TONE IMD (-dBc)

1MHz CARRIER SPACING COMPLEX MODULATION FOR OUTPUT FREQUENCIES GREATER THAN 50MHz

-6dBFS

-12dBFS

-9dBFS

CENTER FREQUENCY (MHz)

GAIN MISMATCH vs. TEMPERATURE

= 125MWps, 2x INTERPOLATION

DATA

0.100

= 22.7MHz

OUT

= -6dBFS

MAX5895 toc11

GAIN MISMATCH (dB)

150120906030

OUT

0.075

0.050

0.025

-40 85

TEMPERATURE (°C)

MAX5895 toc12

603510-15

MULTITONE POWER RATIO PLOT

-10

-20

-30

-40

-50

-60

-70

OUTPUT POWER (dBm)

-80

-90

-100

-110

THROUGH A

OUT1

SPAN = 25MHz

CENTER

OUT8

= 35.7MHz, 1MHz TONE SPACING

= -18dBFS,

= 125MWps, 2x INTERPOLATION

DATA

SUPPLY CURRENTS vs. DAC UPDATE RATE

2x INTERPOLATION, f

500

450

400

350

300

250

200

150

SUPPLY CURRENT (mA)

100

100 300

1.8V TOTAL

DAC

(MHz)

OUT

3.3V TOTAL

= 5MHz

250200150

MAX5895 toc13

DNL (LSB)

500

450

MAX5895 toc16

400

350

300

250

200

150

SUPPLY CURRENT (mA)

100

DIFFERENTIAL NONLINEARITY

vs. DIGITAL INPUT CODE

-1

0 65536

8192

16384

24586

DIGITAL INPUT CODE

32768

40960

49152

57344

SUPPLY CURRENTS vs. DAC UPDATE RATE

1.8V TOTAL

3.3V TOTAL

(MHz)

OUT

= 5MHz

400300200

4x INTERPOLATION, f

100 500

DAC

MAX5895 toc14

INL (LSB)

500

450

MAX5895 toc17

400

350

300

250

200

150

SUPPLY CURRENT (mA)

100

INTEGRAL NONLINEARITY

vs. DIGITAL INPUT CODE

-1

-2

-3

-4

-5

245768192

16384

DIGITAL INPUT CODE

40960

32768

57344

49152

SUPPLY CURRENTS vs. DAC UPDATE RATE

1.8V TOTAL

3.3V TOTAL

(MHz)

OUT

= 5MHz

400300200

8x INTERPOLATION, f

100 500

DAC

MAX5895 toc15

65536

MAX5895 toc18

MAX5895

16-Bit, 500Msps Interpolating and Modulating

Dual DAC with CMOS Inputs

_______________________________________________________________________________________

Typical Operating Characteristics (continued)

(DV

DD1.8

= AV

DD1.8

= 1.8V, AV

CLK

= AV

DD3.3

= DV

DD3.3

= 3.3V, modulator off, 2x interpolation, output is transformer-coupled to

50Ω load, T

= +25°C, unless otherwise noted.)

NOISE DENSITY vs. DAC UPDATE RATE

-100 2x, 4x, AND 8x INTERPOLATION

-110

OUT

-120

-130

-140

-150

NOISE DENSITY (dBFS/Hz)

-160

-170

-180

100 500

= 16MHz, 10MHz OFFSET

OUT

= -12dBFS

400300200

(MHz)

DAC

MAX5895 toc19

WCDMA ACLR SPECTRAL PLOT

= 61.44MWps, 8x INTERPOLATION

DATA

-20

-30

-40

-50

-60

-70

-80

OUTPUT POWER (dBm)

-90

-100

-110

-120

ACLR2 = 77dB

ACLR1 = 76dB

= 61.44MHz, SPAN = 25.5MHz

CENTER

CARRIER = -11dBm

100

ACLR (dB)

ACLR1 = 75dB

WCDMA ACLR vs. OUTPUT FREQUENCY

= 122.88MWps, 4x INTERPOLATION

DATA

SINGLE-CARRIER ALTERNATE CHANNEL

SINGLE-CARRIER ADJACENT CHANNEL

FOUR-CARRIER ALTERNATE CHANNEL

FOUR-CARRIER ADJACENT CHANNEL

0160

CENTER

1208040

(MHz)

MAX5895 toc20

WCDMA ACLR vs. OUTPUT FREQUENCY

= 76.8MWps, 4x INTERPOLATION

DATA

100

SINGLE-CARRIER

ACLR (dB)

ALTERNATE CHANNEL

FOUR-CARRIER ALTERNATE CHANNEL

CENTER

FOUR-CARRIER WCDMA ACLR SPECTRAL PLO

= 61.44MWps, 8x INTERPOLATION

DATA

-20

MAX5895 toc22

ACLR2 = 76dB

-30

-40

-50

-60

-70

-80

OUTPUT POWER (dBm)

-90 ACLR2 = 74dB

-100

-110

-120

ACLR1 = 73dB

CENTER

CARRIER = -17dBm

= 61.44MHz, SPAN = 40.6MHz

ACLR1 = 72dB

SINGLE-CARRIER ADJACENT CHANNEL

FOUR-CARRIER ADJACENT CHANNEL

8040

(MHz)

MAX5895 toc23

ACLR2 = 72dB

MAX5895 toc21

WCDMA ACLR SPECTRAL PLOT = 122.88MWps, 4x INTERPOLATION

DATA

-20

-30

-40

-50

-60

-70

-80

OUTPUT POWER (dBm)

-90

-100

-110

-120

ACLR2 = 73dB

CENTER

ACLR1 = 71dB

CARRIER = -14dBm

ACLR1 = 70dB

= 122.88MHz, SPAN = 25.5MHz

MAX5895 toc24

ACLR2 = 72dB

FOUR-CARRIER WCDMA ACLR SPECTRAL PLOT

= 122.88MWps, 4x INTERPOLATION

DATA

-20

-30

-40

-50

-60

-70

-80

OUTPUT POWER (dBm)

-90 ACLR2 = 67dB

-100

-110

-120

ACLR1 = 66dB

CENTER

CARRIER = -20dBm

= 122.88MHz, SPAN = 40.6MHz

ACLR1 = 66dB

MAX5895 toc25

ACLR2 = 67dB

MAX5895

16-Bit, 500Msps Interpolating and Modulating Dual DAC with CMOS Inputs

10 ______________________________________________________________________________________

Pin Description

PIN NAME FUNCTION

1 CLKP Noninverting Differential Clock Input

2 CLKN Inverting Differential Clock Input

3, 4, 5 N.C. Internally Connected. Do not connect.

6, 21, 30, 37 DV

7–12, 15–20,

22–25

DD1.8

A15–A0

Digital Power Supply. Accepts a 1.71V to 1.89V supply range. Bypass each pin to ground with a

0.1µF capacitor as close to the pin as possible.

A-Port Data Inputs. Dual-port mode: I-channel data input. Data is latched on the rising/falling edge (programmable) of the DATACLK. Single-port mode: I-channel and Q-channel data input, with SELIQ.

13, 44 DV

14 DATACLK Programmable Data Clock Input/Output. See the DATACLK Modes section for details.

26 SELIQ/B15

27 DATACLK/B14

28, 29, 31–36,

38–43

45 SDO Serial-Port Data Output

46 SDI Serial-Port Data Input

47 SCLK Serial-Port Clock Input. Data on SDI is latched on the rising edge of SCLK. 48 CS Serial-Port Interface Select. Drive CS low to enable serial-port interface. 49 RESET Reset Input. Set RESET low during power-up.

50 REFIO Reference Input/Output. Bypass to ground with a 1µF capacitor as close to the pin as possible.

51 DACREF

DD3.3

B13–B0

CMOS I/O Power Supply. Accepts a 3.0V to 3.6V supply range. Bypass each pin to ground with a

0.1µF capacitor as close to the pin as possible.

Select I/Q-Channel Input or B-Port MSB Input. Single-port mode: If SELIQ = LOW, data is latched into Q-channel on the rising/falling edge (programmable) of the DATACLK. If SELIQ = HIGH, data is latched into I-channel on the rising/falling edge (programmable) of the DATACLK. Dual-port mode: Q-channel MSB input.

Alternate DATACLK Input/Output or B-Port Bit 14 Input. Single-port mode: See the DATACLK Modes section for details. Dual-port mode: Q-channel bit 14 input. If unused connect to GND.

B-Port Data Bits 13–0. Dual-port mode: Q-channel inputs. Data is latched on the rising/falling (programmable) edge of the DATACLK. Single-port mode: Connect to GND.

Current-Set Resistor Return Path. For a 20mA full-scale output current, connect a 2kΩ resistor between FSADJ and DACREF. Internally connected to GND. Do not use as an external ground

connection.

52 FSADJ

Full-Scale Adjust Input. This input sets the full-scale output current of the DAC. For a 20mA fullscale output current, connect a 2kΩ resistor between FSADJ and DACREF.

MAX5895

16-Bit, 500Msps Interpolating and Modulating

Dual DAC with CMOS Inputs

______________________________________________________________________________________ 11

Pin Description (continued)

Functional Diagram

PIN NAME FUNCTION

53, 67 AV

54, 56, 59, 61,

64, 66

55, 60, 65 AV

DD1.8

GND Ground

DD3.3

57 OUTQN Inverting Differential DAC Current Output for Q-Channel

58 OUTQP Noninverting Differential DAC Current Output for Q-Channel

62 OUTIN Inverting Differential DAC Current Output for I-Channel

63 OUTIP Noninverting Differential DAC Current Output for I-Channel

68 AV

CLK

— EP Exposed Pad. Must be connected to GND through a low-impedance path.

FILTER

A0–A15

DATACLK

B0–B15

SELIQ

DATA SYNCH

AND DEMUX

FILTER

Low Analog Power Supply. Accepts a 1.71V to 1.89V supply range. Bypass each pin to GND with a 0.1µF capacitor as close to the pin as possible.

Analog Power Supply. Accepts a 3.135V to 3.465V supply range. Bypass each pin to GND with a

0.1µF capacitor as close to the pin as possible.

Clock Power Supply. Accepts a 3.135V to 3.465V supply range. Bypass to ground with a 0.1µF capacitor as close to the pin as possible.

MODULATOR

INTERPOLATING

FILTER

INTERPOLATING

MUX

fIM/2, fIM/4

MUX

∑

FILTER

MAX5895

INTERPOLATING

FILTER

MUX

DIGITAL OFFSET ADJUST

∑

DIGITAL OFFSET ADJUST

∑

IDAC

QDAC

DIGITAL GAIN ADJUST

OUTIP

OUTIN

DAC

DIGITAL GAIN ADJUST

OUTQP

OUTQN

RESET

/2/2

CONTROL REGISTERS

SERIAL INTERFACE

SDO SDI CS SCLK DACREF FSADJ REFIO

REFERENCE

CLOCK BUFFERS

AND DIVIDERS

/2/2

CLK

CLKPCLKN

DAC

MAX5895

16-Bit, 500Msps Interpolating and Modulating Dual DAC with CMOS Inputs

12 ______________________________________________________________________________________

Detailed Description

The MAX5895 dual, 500Msps, high-speed, 16-bit, current-output DAC provides superior performance in communication systems requiring low-distortion analog-signal reconstruction. The MAX5895 combines two DAC cores with 8x/4x/2x/1x programmable digital interpolation filters, a digital quadrature modulator, an SPIcompatible serial interface for programming the device, and an on-chip 1.20V reference. The full-scale output current range is programmable from 2mA to 20mA to optimize power dissipation and gain control.

Each channel contains three selectable interpolating filters making the MAX5895 capable of 1x, 2x, 4x, or 8x interpolation, which allows for low-input and high-output data rates. When operating in 8x interpolation mode, the interpolator increases the DAC conversion rate by a factor of eight, providing an eight-fold increase in separation between the reconstructed waveform spectrum and its first image. The MAX5895 accepts either two’s complement or offset binary input data format and can operate from either a single- or dual-port input bus.

The MAX5895 includes modulation modes at f

/2 and fIM/4, where fIMis the data rate at the input of the modulator. If 2x interpolation is used, this data rate is 2x the input data rate. If 4x or 8x interpolation is used, this data rate is 4x the input data rate. Table 1 summarizes the modulator operating data rates for dual-port mode.

The power-down modes can be used to turn off each DAC’s output current or the entire digital section. Programming both DACs into power-down simultaneously will automatically power down the digital interpolator filters. Note the SPI section is always active.

The analog and digital sections of the MAX5895 have separate power-supply inputs (AV

DD3.3

, AV

DD1.8

CLK

, DV

DD3.3

, and DV

DD1.8

), which minimize noise

coupling from one supply to the other. AV

DD1.8

and

DD1.8

operate from a typical 1.8V supply, and all

other supply inputs operate from a typical 3.3V supply.

Serial Interface

The SPI-compatible serial interface programs the MAX5895 registers. The serial interface consists of the CS, SDI, SCLK, and SDO. Data is shifted into SDI on the rising edge of the SCLK when CS is low. When CS is high, data presented at SDI is ignored and SDO is in high-impedance mode. Note: CS must transition high after each read/write operation. SDO is the serial data output for reading registers to facilitate easy debugging during development. SDI and SDO can be connected together to form a 3-wire serial interface bus or remain separate and form a 4-wire SPI bus.

The serial interface supports two-byte transfer in a communication cycle. The first byte is a control byte written to the MAX5895 only. The second byte is a data byte and can be written to or read from the MAX5895.

Table 1. Quadrature Modulator Operating Data Rates (fIMis the Data Rate at the Input of the Modulator) for Dual-Port Mode

INTERPOLATION RATE MODULATION MODE (fLO)

fIM/2 f

/4 f

fIM/2 f

/4 f

fIM/2 f

/4 f

fIM/2 f

/4 f

MODULATION FREQUENCY

RELATIVE TO f

DAC

/2 f

/4 f

/2 f

/4 f

/2 2 x f

/4 f

/4 2 x f

/8 f

MODULATION FREQUENCY

RELATIVE TO f

DATA

When writing to the MAX5895, data is shifted into SDI; data is shifted out of SDO in a read operation. Bits 0 to 3 of the control byte are the address bits. These bits set the address of the register to be written to or read from. Bits 4 to 6 of the control byte must always be set to 0. Bit 7 is a read/write bit: 0 for write operation and 1 for read operation. The most significant bit (MSB) is shifted

in first in default mode. If the serial port is set to LSBfirst mode, both the control byte and data byte are shifted LSB in first. Figures 1 and 2 show the SPI serial interface operation in the default write and read mode, respectively. Figure 3 is a timing diagram for the SPI serial interface.

MAX5895

16-Bit, 500Msps Interpolating and Modulating

Dual DAC with CMOS Inputs

______________________________________________________________________________________ 13

Figure 1. SPI Serial Interface Write Cycle, MSB-First Mode

Figure 2. SPI Serial Interface Read Cycle, MSB-First Mode

SCLK

SDI

SDO

0 0 0 0 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

HIGH IMPEDANCE

SCLK

SDI

SDO

READ CYCLE N - 1

ADDRESS DATA

10003210

HIGH

IMPEDANCE

IGNORED

DATA N - 2

ADDRESS DATA

10003210

HIGH

IMPEDANCE

READ CYCLE N

IGNORED

DATA N - 1

READ CYCLE N + 1

ADDRESS DATA

10003210

HIGH

IMPEDANCE

IGNORED

DATA N

MAX5895

16-Bit, 500Msps Interpolating and Modulating Dual DAC with CMOS Inputs

14 ______________________________________________________________________________________

Figure 3. SPI Serial-Interface Timing Diagram

SCLK

SDI

SDO

SDS

SDH

SDV

MAX5895

Programming Registers

Programming its registers with the SPI serial interface sets the MAX5895 operation modes. Table 2 shows all

of the registers. The following are descriptions of each register.

16-Bit, 500Msps Interpolating and Modulating

Dual DAC with CMOS Inputs

______________________________________________________________________________________ 15

Table 2. MAX5895 Programmable Registers

Conditions in bold are default states after reset.

ADD BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

00h Unused

Interpolation Rate (Bit 7, Bit 6) 00 = No interpolation

01h

01 = 2x interpolation 10 = 4x interpolation

11 = 8x interpolation

0 = Two’s complement input data

02h

1 = Offset binary input data

03h Unused

04h 8-Bit IDAC Fine-Gain Adjustment (see the Gain Adjustment section). Bit 7 is MSB and bit 0 is LSB. Default: 00h

05h Unused

10-Bit IDAC Offset Adjustment (see the Offset Adjustment section). Bits 7 to 0 of the 06h register are the MSB bits. Bit 1 and bit 0 are the LSB

06h

bits in 07h register. Default: 000h

IDAC IOFFSET Direction

0 = Current on

07h

OUTIN

1 = Current on OUTIP

08h 8-Bit QDAC Fine-Gain Adjustment (see the Gain Adjustment section). Bit 7 is MSB and bit 0 is LSB. Default: 00h

09h Unused

10-Bit QDAC Offset Adjustment (see the Offset Adjustment section). Bits 7 to 0 of the 0Ah register are the MSB bits. Bit 1 and bit 0 are the

0Ah

LSB bits in 0Bh register. Default: 000h

QDAC IOFFSET Direction

0 = Current on

0Bh

OUTQN

1 = Current on OUTQP

0Ch Reserved, do not write to these bits.

0Dh Reserved, do not write to these bits.

0Eh Reserved, do not write to these bits.

0 = MSB first

1 = LSB first

0 = Single port (A), interleaved I/Q

1 = Dual port I/Q input

Unused

Software Reset

0 = Normal

1 = Reset all registers

Third Interpolation Filter Configuration

0 = Lowpass

1 = Highpass

0 = Clock output on DATACLK

1 = Clock output on DATA CLK/B14

Interpolator Power-Down

0 = Normal

1 = Power-down

Modulation Mode (Bit 4, Bit 3) 00 = Modulation off 01 = f

10 = f

11 = f

0 = Input data latched on rising clock edge

1 = Input data latched on falling clock edge

IDAC PowerDown

0 = Normal

1 = Power-down

0 = Data clock input enabled

1 = Data clock output enabled

4-Bit IDAC Coarse-Gain Adjustment (see the Gain Adjustment section). Bit 3 is MSB and bit 0 is LSB. Default: Fh

4-Bit QDAC Coarse-Gain Adjustment (see the Gain Adjustment section). Bit 3 is MSB and bit 0 is LSB. Default: Fh

QDAC PowerDown

0 = Normal

1 = Power-down

Mixer Modulation Mode 0 = Complex

1 = Real

Data Synchronizer

0 = Enabled

1 = Disabled

Unused

Modulation Sign

-jω

0 = e

+jω

1 = e

Unused

IDAC Offset Adjustment Bit 1 (see 06h register)

QDAC Offset Adjustment Bit 1 (see 0Ah register)

Unused

IDAC Offset Adjustment Bit 0 (see 06h register)

QDAC Offset Adjustment Bit 0 (see 0Ah register)

MAX5895

16-Bit, 500Msps Interpolating and Modulating Dual DAC with CMOS Inputs

16 ______________________________________________________________________________________

Address 00h

Bit 6 Logic 0 (default) causes the serial port to use

MSB first address/data format. When set to a logic 1, the serial port will use LSB first address/data format.

Bit 5 When set to a logic 1, all registers reset to

their default state (this bit included).

Bit 4 Logic 1 stops the clock to the digital interpo-

lators. DAC outputs hold last value prior to interpolator power-down.

Bit 3 IDAC power-down mode. A logic 1 to this bit

powers down the IDAC.

Bit 2 QDAC power-down mode. A logic 1 to this bit

powers down the QDAC.

Note: If both bit 2 and bit 3 are 1, the MAX5895 is in full-power-down mode, leaving only the serial interface active.

Address 01h

Bits 7, 6 Configure the interpolation filters according

to the following table:

00 1x (no interpolation)

01 2x

10 4x

11 8x (default)

Bit 5 Logic 0 configures FIR3 as a lowpass digital

filter (default). A logic 1 configures FIR3 as a highpass digital filter.

Bits 4, 3 Configure the modulation frequency accord-

ing to the following table:

00 No modulation

01 fIM/2 modulation

10 fIM/4 modulation (default)

11 fIM/4 modulation

where fIMis the data rate at the input of the modulator.

Bit 2 Configures the modulation mode for either

real or complex (image reject) modulation. Logic 1 sets the modulator to the real mode (default). Complex modulation is only available for f

/4 modulation.

Bit 1 Quadrature modulator sign inversion. With I-

channel data leading Q-channel data by 90°, logic 0 sets the complex modulation to be e

-jw

(default), cancelling the upper image when used with an external quadrature modulator. A logic 1 sets the complex modulation

to be e

+jw

, cancelling the lower image when

used with an external quadrature modulator.

Address 02h

Bit 7 Logic 0 (default) configures the data port for

two’s complement. A logic 1 configures the data ports for offset binary.

Bit 6 Logic 0 (default) configures the data bus for

single-port, interleaved I/Q data. I and Q data enter through one 16-bit bus. Logic 1 configures the data bus for dual-port I/Q data. I and Q data enter on separate buses.

Bit 5 Logic 0 (default) configures the data clock

for pin 14. A logic 1 configures the data clock for pin 27 (DATACLK/B14).

Bit 4 Logic 0 (default) sets the internal latches to

latch the data on the rising edge of DATACLK. A logic 1 sets the internal latches to latch the data on the falling edge of DATACLK.

Bit 3 Logic 0 (default) configures the DATACLK

pin (pin 14 or pin 27) to be an input. A logic 1 configures the DATACLK pin to be an output.

Bit 2 Logic 0 (default) enables the data synchro-

nizer circuitry. A logic 1 disables the data synchronizer circuitry.

Address 03h

Bits 7–0 Unused.

Address 04h

Bits 7–0 These 8 bits define the binary number for

fine-gain adjustment of the IDAC full-scale current (see the

Gain Adjustment

section). Bit

7 is the MSB. Default is all zeros.

Address 05h

Bits 3–0 These four bits define the binary number for

the coarse-gain adjustment of the IDAC fullscale current (see the

Gain Adjustment

sec-

tion). Bit 3 is the MSB. Default is all ones.

Address 06h, Bits 7 to 0; Address 07h, Bit 1 and Bit 0

These 10 bits represent a binary number that defines the magnitude of the offset added to the IDAC output (see the

Offset Adjustment

section). Default is all zeros.

Address 07h

Bit 7 Logic 0 (default) adds the 10 bits offset cur-

rent to OUTIN. A logic 1 adds the 10 bits offset current to OUTIP.

Address 08h

Bits 7–0 These eight bits define the binary number for

fine-gain adjustment of the QDAC full-scale current (see the

Gain Adjustment

section). Bit

7 is the MSB. Default is all zeros.

Address 09h

Bits 3–0 These four bits define the binary number for

the coarse-gain adjustment of the QDAC fullscale current (see the

Gain Adjustment

sec-

tion). Bit 3 is the MSB. Default is all ones.

Address 0Ah, Bits 7 to 0; Address 0Bh, Bit 1 and Bit 0

These 10 bits represent a binary number that defines the magnitude of the offset added to the QDAC output (see the

Offset Adjustment

section). Default is all zeros.

Address 0Bh

Bit 7 Logic 0 (default) adds the 10 bits offset to

OUTQN. A logic 1 adds the 10 bits offset to OUTQP.

Offset Adjustment

Offset adjustment is achieved by adding a digital code to the DAC inputs. The code OFFSET (see equation below), as stored in the relevant control registers, has a range from 0 to 1023 and a sign bit. The applied DAC offset is 4 times the code stored in the register, providing an offset adjustment range of ±4092 LSB codes. The resolution is 4 LSB.

Gain Trim

Gain trimming is done by varying the full-scale current according to the following formula:

where I

REF

is the reference current (see the

Internal

Reference

section). COARSE is the register content of

registers 05h and 09h for the I- and Q-channel, respec-

tively. FINE is the register content of register 04h and 08h for the I- and Q-channel, respectively. The range of coarse is from 0 to 15, with 15 being the default. The range for FINE is from 0 to 255 with 0 being the default. Given this, the gain can be adjusted in steps of approximately 0.01dB.

Single-Port/Dual-Port Data Input Modes

The MAX5895 is capable of capturing data in singleport and dual-port modes (selected through bit 6, address 02h). In single-port mode, the data for both channels is input through the A port (A15–A0). The channel for the input data is determined through the state of the SELIQ/B15 (pin 26) bit. When SELIQ is set to logic-high, the input data is presented to the I-channel, when set to logic-low, the input data is presented to the Q-channel. The unused B-port inputs (DATACLK/B14, B13–B0) should be grounded when running in single-port mode.

Dual-port mode, as the name implies, requires that each channel receives its data from a separate data bus. SELIQ/B15 and DATACLK/B14 revert to data bit inputs for the Q-channel in dual-port mode.

The MAX5895 control registers can be programmed to allow either signed or unsigned binary format (bit 7, address 02h) data in either single-port or dual-port mode. Table 3 shows the corresponding DAC output levels when using signed or unsigned data modes.

Data Synchronization Modes

Data synchronization circuitry is provided to allow operation with an input data clock. The data clock must be frequency locked to the DAC clock (f

DAC

), but can have arbitrary phase with respect to the DAC clock. The synchronization circuitry allows for phase jitter on the input data clock of up to ±1 data clock cycles. Synchronization is initially established when the reset pin is asynchronously deasserted and the input data clock has been running for at least 4 clock cycles. Subsequently, the MAX5895 monitors the phase rela-

MAX5895

16-Bit, 500Msps Interpolating and Modulating

Dual DAC with CMOS Inputs

______________________________________________________________________________________ 17

Table 3. DAC Output Code Table

x OFFSET

OFFSET

OUTFS

DIGITAL INPUT CODE

OFFSET BINARY

(UNSIGNED)

0000 0000 0000 1000 0000 0000

0111 1111 1111 1111 000 0 000 0 000 0 000 0 I

1111 1111 1111 0111 1111 1111

TWO'S

COMPLEMENT

(SIGNED)

O U T_ P OUT_N

OUTFS

/2 I

OUTFS

⎡

⎛

⎢

⎜ ⎝

⎣

⎞

COARSE

⎛

REF REF

⎜

⎟

⎝

⎠

⎞ ⎟

⎠

⎛

−

⎜ ⎝

⎞ ⎟

⎠

32 256

⎛ ⎜

⎝

FINE

⎤

1024

⎞

⎛

⎟

⎜

⎥

⎠

⎝

⎦

⎞ ⎟

⎠

MAX5895

tionship and detects if the phase drifts more than ±1 data clock cycle. If this occurs, the synchronizer automatically reestablishes synchronization. However, during the resynchronization phase, up to 8 data words may be lost or repeated.

Bit 2 of register 02h disables or enables (default) the automatic data clock phase detection. Disabling the data synchronization circuitry requires the data clock and the DAC clock phase to be locked.

DATACLK Modes

The MAX5895 has a main DATACLK available at pin 14. An alternate DATACLK is available at pin 27 (DATACLK/B14) when configured in single-port data input mode (bit 5, address 02h). The DATACLK can be configured to accept an input clock signal for latching the input data, or to source a clock signal that can drive up to 10pF load while latching the input data (bit 3, address 02h). If DATACLK is configured as an output, it

is frequency divided from the CLKP/CLKN input, depending on the operating mode, see Table 4.

16-Bit, 500Msps Interpolating and Modulating Dual DAC with CMOS Inputs

18 ______________________________________________________________________________________

Table 4. Clock Frequency Ratios in Various Modes

Figure 4. Data Input Timing Diagram

CLKP–CLKN

INPUT MODE

Single

Port

Dual Port

INTERPOLATION

RATE

1x 1:1 1:2

2x 1:1 1:1

4x 1:2 1:1

8x 1:4 1:1

1x 1:1 1:1

2x 1:2 1:1

4x 1:4 1:1

8x 1:8 1:1

DATA:fCLKfDAC:fCLK

DATACLK

A0–A15/B0–B15

CLK

MAX5895

16-Bit, 500Msps Interpolating and Modulating

Dual DAC with CMOS Inputs

______________________________________________________________________________________ 19

The MAX5895 can be configured to latch the input data on either the rising edge or falling edge of the DATACLK signal (bit 4, address 02h). Figure 4 shows the timing requirements between the DATACLK signal and the input data bus with latching on the rising edge.

Interpolating Filter

The MAX5895 features three cascaded FIR half-band filters. The interpolating filters are enabled or disabled in combinations to support 1x (no interpolation), 2x, 4x, or 8x interpolation. Bits 7 and 6 of register 01h set the interpolation rate (see Table 2). The last interpolation fil-

Figure 5. Interpolation Filter Frequency Response, 2x Interpolation Mode

Figure 6. Interpolation Filter Frequency Response, 4x Interpolation Mode

Figure 7. Interpolation Filter Frequency Response, 8x Interpolation Mode (FIR3 Lowpass Mode)

Figure 8. Interpolation Filter Frequency Response, 8x Interpolation Mode (FIR3 Highpass Mode)

-20

-40

-60

GAIN (dBFS)

-80

-100

-120 0 0.4 0.6 0.8

0.2

OUT

-0.0002

-0.0004

- NORMALIZED TO INPUT DATA RATE

PASSBAND DETAIL

0 0.1 0.2 0.3

1.0 1.2 1.4 1.6 1.8 2.0

0.4

-20

-40

-60

-0.0002

-0.0004

GAIN (dBFS)

-80

-100

-120

0.5

0 1.0 1.5 2.0

- NORMALIZED TO INPUT DATA RATE

OUT

PASSBAND DETAIL

0 0.1 0.2 0.3 0.4

2.5 3.0 3.5 4.0

-20

PASSBAND DETAIL

-40

-60

GAIN (dBFS)

-0.0002

-0.0004 0 0.1 0.2 0.3 0.4

-80

-100

-120 1

0234

- NORMALIZED TO INPUT DATA RATE

OUT

5678

-20

-40

-60

GAIN (dBFS)

-0.0002

-0.0004

PASSBAND DETAIL

3.6 3.8 4.0 4.2 4.4

-80

-100

-120 1

0234

- NORMALIZED TO INPUT DATA RATE

OUT

5678

MAX5895

ter is located after the modulator. In the 8x interpolation mode, the last filter (FIR3) can be configured as lowpass or highpass (bit 5, address 01h) to select the lower or upper sideband from the modulation output. The frequency responses of these three filters are plotted in Figures 5–8.

The programmable interpolation filters multiply the MAX5895 input data rate by a factor of 2x, 4x, or 8x to separate the reconstructed waveform spectrum and the

DAC image. The original spectral images, appearing at around multiples of the input data rate, are attenuated by the internal digital filters. This feature provides three benefits:

1) Image separation reduces complexity of analog reconstruction filters.

2) Lower input data rates eliminate board-level highspeed data transmission.

16-Bit, 500Msps Interpolating and Modulating Dual DAC with CMOS Inputs

20 ______________________________________________________________________________________

Figure 9. Spectral Representation of Interpolating Filter Responses (Output Frequencies are Relative to the Data Input Frequency, fS)

FILTER

IMAGE

RESPONSE

INPUT SPECTRUM AND FIRST FILTER RESPONSE

OUTPUT SPECTRUM OF THE FIRST FILTER

INPUT SPECTRUM AND SECOND FILTER RESPONSE

SIGNAL

IMAGE

NO INTERPOLATION

FILTER RESPONSE

2x INTERPOLATION

OUTPUT SPECTRUM OF THE SECOND FILTER

INPUT SPECTRUM AND THIRD FILTER RESPONSE

OUTPUT SPECTRUM OF THE THIRD FILTER

SIGNAL

IMAGE

FILTER RESPONSE

IMAGE

4x INTERPOLATION

8x INTERPOLATION

3) Sin(x)/x rolloff is reduced over the effective bandwidth.

Figure 9 illustrates a practical example of the benefits when using the MAX5895 in 2x, 4x, and 8x interpolation modes with the third filter configured as a lowpass filter. With no interpolation filter, the first image signal appears

in the second Nyquist zone between fS/2 and fS. The first interpolating filter removes this image. In fact, all of the images at odd numbers of fSare filtered. At the output of the first filter, the images are at 2fS, 4fS, etc. This signal is then passed to the second interpolating filter, which is

MAX5895

16-Bit, 500Msps Interpolating and Modulating

Dual DAC with CMOS Inputs

______________________________________________________________________________________ 21

Figure 10. Spectral Representation of 4x Interpolation Filter with fIM/4 Modulation (Output Frequencies are Relative to the Data Input Frequency, f

)

INPUT SPECTRUM AND FIRST FILTER RESPONSE

OUTPUT SPECTRUM OF THE FIRST FILTER

INPUT SPECTRUM AND SECOND FILTER RESPONSE

SIGNAL

IMAGE

FILTER RESPONSE

FILTER

RESPONSE

IMAGE

NO INTERPOLATION

2x INTERPOLATION

OUTPUT SPECTRUM OF THE SECOND FILTER

OUTPUT SPECTRUM OF THE MODULATOR

SIGNAL

LOWER

SIDEBAND

FOR COMPLEX MODULATION THE MODULATION SIGN (BIT 1, ADDRESS 01h) SELECTS UPPER OR LOWER SIDEBAND

UPPER SIDEBAND

IMAGE

4x INTERPOLATION

MAX5895

16-Bit, 500Msps Interpolating and Modulating Dual DAC with CMOS Inputs

22 ______________________________________________________________________________________

Figure 11. Spectral Representation of 8x Interpolation Filter with fIM/4 Modulation and Lowpass Mode Enabled (Output Frequencies are Relative to the Data Input Frequency, f

)

INPUT

SIGNAL

SPECTRUM AND FIRST FILTER RESPONSE

OUTPUT

SIGNAL

SPECTRUM OF THE FIRST FILTER

INPUT SPECTRUM

SIGNAL

AND SECOND FILTER RESPONSE

OUTPUT

SIGNAL

SPECTRUM OF THE SECOND FILTER

FILTER

IMAGE

RESPONSE

IMAGE

NO INTERPOLATION

2x INTERPOLATION

FILTER

IMAGE

RESPONSE

IMAGE

4x INTERPOLATION

SIGNAL

OUTPUT

LOWER

SIDEBAND

UPPER SIDEBAND

IMAGE

SPECTRUM OF THE MODULATOR

FOR COMPLEX MODULATION THE MODULATION SIGN (BIT 1, ADDRESS 01h) SELECTS UPPER OR LOWER SIDEBAND

FILTER RESPONSE

IMAGE

INPUT SPECTRUM

SIGNAL

AND THIRD FILTER RESPONSE

OUTPUT SPECTRUM

SIGNAL

IMAGE

8x INTERPOLATION

OF THE THIRD FILTER

MAX5895

16-Bit, 500Msps Interpolating and Modulating

Dual DAC with CMOS Inputs

______________________________________________________________________________________ 23

Figure 12. Spectral Representation of 8x Interpolation Filter with fIM/4 Modulation and Highpass Mode Enabled (Output Frequencies are Relative to the Data Input Frequency, f

)

INPUT SPECTRUM AND FIRST FILTER RESPONSE

SIGNAL

FILTER

IMAGE

RESPONSE

NO INTERPOLATION

OUTPUT SPECTRUM OF THE FIRST FILTER

INPUT SPECTRUM AND SECOND FILTER RESPONSE

OUTPUT SPECTRUM OF THE SECOND FILTER

OUTPUT SPECTRUM OF THE MODULATOR

SIGNAL

IMAGE

FILTER RESPONSE

IMAGE

SIGNAL

LOWER

SIDEBAND

UPPER SIDEBAND

IMAGE

FOR COMPLEX MODULATION THE MODULATION SIGN (BIT 1, ADDRESS 01h) SELECTS UPPER OR LOWER SIDEBAND

2x INTERPOLATION

4x INTERPOLATION

INPUT SPECTRUM

SIGNAL

IMAGE

FILTER RESPONSE

AND THIRD FILTER RESPONSE

OUTPUT SPECTRUM

SIGNAL

IMAGE

8x INTERPOLATION

OF THE THIRD FILTER

MAX5895

similar to the first filter and removes the images at 2fS, 6fS, 10fS, etc. Finally, the third filter removes images at 4fS, 12fS, 20fS, etc. Figures 10, 11, and 12 similarly illustrate the spectral responses when using the interpolating filters combined with the digital modulator.

Digital Modulator

The MAX5895 features digital modulation at frequencies of fIM/2 and fIM/4, where fIMis the data rate at the input to the modulator. fIMequals f

DAC

in 1x, 2x, and 4x

interpolation modes. In 8x interpolation mode, f

equals f

DAC

/2. The output rate of the modulator is always the same as the input data rate to the modulator, fIM.

In complex modulation mode, data from the second interpolation filter is frequency mixed with the on-chip in-phase and quadrature (I/Q) local oscillator (LO). Complex modulation provides the benefit of image sideband rejection when combined with an external quadrature modulator commonly found in wireless communication systems.

In the fLO= fIM/4 mode, real or complex modulation can be used. The modulator multiplies successive input data samples by the sequence [1, 0, -1, 0] for a cos(ωt). The modulator modulates the input signal up to fIM/4, creating upper and lower images around fIM/4. The quadrature LO sin(ωt) is realized by delaying the cos(ωt) sequence by one clock cycle. Using complex modulation, complex IF is generated. The complex IF combined with an external quadrature modulator provides image rejection. The sign of the LO can be changed to allow the user to select whether the upper or the lower image should be rejected (bit 1 of register 01h).

When fIM/2 is chosen as the LO frequency, the input signal is multiplied by [-1, 1] on both channels. This produces images around fIM/2. The complex image-reject modulation mode is not available for this LO frequency.

The outputs of the modulator can be expressed as:

in complex modulation, e

+jwt

in complex modulation, e

-jwt

where ω = 2 x π x fLO.

For real modulation, The outputs of the modulator can be expressed as:

If more than one MAX5895 is used, their LO phases can be synchronized by simultaneously releasing RESET. This sets the MAX5895 to its predefined initial phase.

Device Reset

The MAX5895 can be reset by holding the RESET pin low for 10ns. This will program the control registers to

16-Bit, 500Msps Interpolating and Modulating Dual DAC with CMOS Inputs

24 ______________________________________________________________________________________

Figure 13. (a) Modulator in Complex Modulation Mode; (b) Modulator in Real Modulation Mode

It At t Bt t

cos sin

()=()×() ()×()

Qt At t Bt t

sin cos

()×()+()×()

()

It At t Bt t

cos sin

()=()×()+()×()

Qt At t Bt t

sin cos

()×()+()×()

()

−ωω

ωω

It At t

cos

()=()×()

Qt At t

cos

()×()

()

I-CHANNEL INPUT DATA

cos(ωt)

sin(ωt)

Q-CHANNEL INPUT DATA

cos(ωt)

(a)

∑

I-CHANNEL OUTPUT DATA

TO FIR3

Q-CHANNEL OUTPUT DATA

I-CHANNEL INPUT DATA

Q-CHANNEL INPUT DATA

cos(ωt)

sin(ωt)

cos(ωt)

I-CHANNEL

∑

OUTPUT DATA

TO FIR3

Q-CHANNEL

∑

OUTPUT DATA

(b)

their default values in Table 2. During power-on, RESET must be held low until all power supplies have stabilized. Alternatively, programming bit 5 of address 00h to a logic-high also resets the MAX5895 after power-up.

Power-Down Mode

The MAX5895 features three power-saving modes. Each DAC can be individually powered down through bits 2 and 3 of address 00h. The interpolation filters can also be powered down through bit 4 of address 00h, preserving the output level of each DAC (the DACs remain powered). Powering down both DACs will automatically put the MAX5895 into full power-down, including the interpolation filters.

Applications Information

Frequency Planning

System designers need to take the DAC into account during frequency planning for high-performance applications. Proper frequency planning can ensure that optimal system performance is achieved. The MAX5895 is designed to deliver excellent dynamic performance across wide bandwidths, as required for communication systems and, in particular, for multicarrier applications. As with all DACs, some combinations of output frequency and update rate produce better performance than others.

Harmonics are often folded down into the band of interest. Specifically, if the DAC outputs a frequency close to fS/N, the Mth harmonic of the output signal will be aliased down to:

Thus, if N ≈ (M + 1), the Mth harmonic will be close to the output frequency. SFDR performance of a currentsteering DAC is often dominated by third-order harmonic distortion. If this is a concern, placing the output signal at a different frequency other than fS/4 should be considered.

Common to interpolating DACs are images near the divided clocks. In a DAC configured for 4x interpolation this applies to images around fS/4 and fS/2. In a DAC configured for 8x interpolation this applies to images around fS/8, fS/4, and fS/2. Most of these images are not part of the in-band (0 to f

DATA

/2) SFDR specification, though they are a consideration for out-of-band (f

DATA

/2 - f

DAC

/2) SFDR and may depend on the rela-

tionship of the DATACLK to DAC update clock (see the

Data Clock

section). When specifying the output reconstruction filter for other than baseband signals, these images should not be ignored.

Data Clock

The MAX5895 features synchronizers that allow for arbitrary phase alignment between DATACLK and CLKP/CLKN. The DATACLK causes internal switching in the MAX5895 and the phase between DATACLK (input mode) to CLKP/CLKN will influence the images at DATACLK. Optimum image rejection is achieved when DATACLK transitions are aligned with the falling edge of CLKP. Figure 14 shows the image level near DATACLK as a function of the DATACLK (input mode) to CLKP/CLKN phase at 500Msps, 4x interpolation for a 10MHz, -6dBFS output signal.

Clock Interface

The MAX5895 features a flexible differential clock input (CLKP, CLKN) with a separate supply (AV

CLK

) to achieve optimum jitter performance. It uses an ultra-low jitter clock to achieve the required noise density. Clock jitter must be less than 0.5ps

RMS

to meet the specified noise density. For that reason, the CLKP/CLKN input source must be designed carefully. The differential clock (CLKN and CLKP) input can be driven from a single-ended or a differential clock source. Differential clock drive is required to achieve the best dynamic performance from the DAC. For single-ended operation, drive CLKP with a low noise source and bypass CLKN to GND with a 0.1µF capacitor.

The CLKP and CLKN pins are internally biased to AV

CLK

/2. This allows the user to AC-couple clock

MAX5895

16-Bit, 500Msps Interpolating and Modulating

Dual DAC with CMOS Inputs

______________________________________________________________________________________ 25

Figure 14. Effect of CLKP/CLKN to DATACLK Phase on fS/4 Images

ff Mxf f

−

S OUT S

⎡ ⎢

⎣

−

⎤ ⎥

⎦

fS/4 IMAGES vs. CLKP/CLKN to DATACLK DELAY

= 125MWps, 4x INTERPOLATION

DATA

-50

-60

-70

-80

IMAGE LEVEL (dBc)

-90

-100

-110 0 8.0

fS/4 - f

OUT

fS/4 + f

OUT

CLKP/CLKN DELAY (ns)

OUT

= 10MHz

= -6dBFS

6.04.02.0

MAX5895

sources directly to the device without external resistors to define the DC level. The input resistance of CLKP and CLKN is 5kΩ.

A convenient way to apply a differential signal is with a balun transformer as shown in Figure 15. Alternatively, these inputs may be driven from a CMOS-compatible clock source, however it is recommended to use sine-wave or AC-coupled differential ECL/PECL drive for best dynamic performance.

Output Interface (OUTI, OUTQ)

The MAX5895 outputs complementary currents (OUTIP, OUTIN) and (OUTQP, OUTQN), that can be utilized in a differential configuration. Load resistors convert these two output currents into a differential output voltage.

The differential output between OUTIP (OUTQP) and OUTIN (OUTQN) can be converted to a single-ended output using a transformer or a differential amplifier. Figure 16 shows a typical transformer-based application circuit for generation of IF output signals. In this configuration, the MAX5895 operates in differential mode, which reduces even-order harmonics, and increases the available output power. Pay close attention to the transformer core saturation characteristics when selecting a transformer. Transformer core saturation can introduce strong second harmonic distortion,

16-Bit, 500Msps Interpolating and Modulating Dual DAC with CMOS Inputs

26 ______________________________________________________________________________________

Figure 15. Single-Ended-to-Differential Clock Conversion Using a Balun Transformer

Figure 16. Differential-to-Single-Ended Conversion Using Wideband RF Transformers

100nF

CLKP

SINGLE-ENDED

IINPUT

MINI-CIRCUITS

ADTL1-12

1:1 RATIO

24.9Ω

MAX5895

24.9Ω

100nF

CLKN

50Ω

OUTIP

IDAC

OUTIN

MAX5895

OUTQP

QDAC

OUTQN

100Ω

1:1

50Ω

100Ω

1:1

50Ω

, SINGLE-ENDED

IOUT

1:1

, SINGLE-ENDED

QOUT

1:1

especially at low output frequencies and high signal amplitudes. It is recommended to connect the transformer center tap to ground.

If a transformer is not used, the outputs must have a resistive termination to ground. Figure 17 shows the MAX5895 output configured for differential DC-coupled mode. The DC-coupled configuration can be used to eliminate waveform distortion due to highpass filter effects. Applications include communication systems employing analog quadrature upconverters and requiring a high-speed DAC for baseband I/Q synthesis.

If a single-ended DC-coupled unipolar output is desirable, OUTIP (OUTQP) should be selected as the output, and connect OUTIN (OUTQN) to ground. Using the MAX5895 output single-ended is not recommended because it introduces additional noise and distortion.

The distortion performance of the DAC also depends on the load impedance. The MAX5895 is optimized for a 50Ω double termination. It can be used with a transformer output as shown in Figure 16 or just one 25Ω resistor from each output to ground and one 50Ω resistor between the outputs (Figure 17). Higher output termination resistors may be used, as long as each output voltage does not exceed +1V with respect to GND, but at the cost of degraded distortion performance and increased output noise voltage.

MAX5895

16-Bit, 500Msps Interpolating and Modulating

Dual DAC with CMOS Inputs

______________________________________________________________________________________ 27

Figure 17. The DC-Coupled Differential Output Configuration

25Ω

OUTIP

IDAC

OUTIN

MAX5895

OUTQP

QDAC

OUTQN

50Ω

25Ω

50Ω

25Ω

MAX5895

Reference Input/Output

The MAX5895 supports operation with the on-chip 1.2V bandgap reference or an external reference voltage source. REFIO serves as the input for an external, lowimpedance reference source, and as the output if the DAC is operating with the internal reference.

For stable operation with the internal reference, REFIO should be decoupled to GND with a 1µF capacitor. REFIO must be buffered with an external amplifier, if heavy loading is required, due to its 10kΩ output resistance.

Alternatively, apply a temperature-stable external reference to REFIO (Figure 18). The internal reference is overdriven by the external reference. For improved accuracy and drift performance, choose a fixed output voltage reference such as the MAX6520 bandgap reference.

The MAX5895’s reference circuit (Figure 19) employs a control amplifier, designed to regulate the full-scale current I

OUT

for the differential current outputs of the

DAC. The output current can be calculated as:

OUTFS

= 32 x I

REFIO

- 1LSB

OUTFS

= 32 x I

REFIO

- (I

OUT

/216)

where I

REFIO

is the reference output current (I

REFIO

REFIO/RSET

) and I

OUT

is the full-scale output current of the DAC. Located between FSADJ and DACREF, R

SET

is the reference resistor, which determines the amplifier’s output current for the DAC. Use Table 5 for a matrix of different I

OUTFS

and R

SET

selections.

16-Bit, 500Msps Interpolating and Modulating Dual DAC with CMOS Inputs

28 ______________________________________________________________________________________

Figure 18. Typical External Reference Circuit

Figure 19. MAX5895 Internal Reference Architecture

Table 5. I

OUTFS

and R

SET

Selection Matrix Based on a Typical 1.20V Reference Voltage

Terminated into a 50

Ω

load.

1.2V

REFERENCE

MAX5895

EXTERNAL

1.25V

REFERENCE

10kΩ

REFIO

1µF

REFIO

1µF

1.2V

REFERENCE

10kΩ

MAX5895

FSADJ

REF

SET

DACREF

FULL-SCALE

CURRENT

OUTFS

2 62.50 19.2k 19.1k 100

5 156.26 7.68k 7.5k 250

10 312.50 3.84k 3.83k 500

15 468.75 2.56k 2.55k 750

20 625.00 1.92k 1.91k 1000

(mA) I

REFERENCE

CURRENT

(µA) CALCULATED 1% EIA STD V

REF

CURRENT-

SOURCE

ARRAY DAC

FSADJ

REF

SET

DACREF

(Ω) OUTPUT VOLTAGE

SET

CURRENT-

SOURCE

ARRAY DAC

IOUTP/N

* (mV

P-P

)

MAX5895

16-Bit, 500Msps Interpolating and Modulating

Dual DAC with CMOS Inputs

______________________________________________________________________________________ 29

Power Supplies, Bypassing,

Decoupling, and Layout

Grounding and power-supply decoupling strongly influence the MAX5895 performance. Unwanted digital crosstalk can couple through the input, reference, power-supply, and ground connections, which can affect dynamic specifications like signal-to-noise ratio or spurious-free dynamic range. In addition, electromagnetic interference (EMI) can either couple into or be generated by the MAX5895. Observe the grounding and power-supply decoupling guidelines for highspeed, high-frequency applications. Follow the powersupply and filter configuration guidelines to achieve optimum dynamic performance.

Using a multilayer PCB with separate ground and power-supply planes, run high-speed signals on lines directly above the ground plane. Since the MAX5895 has separate analog and digital sections, the PCB should include separate analog and digital ground sections with only one point connecting the three planes at the exposed paddle under the MAX5895. Run digital signals above the digital ground plane and analog/clock signals above the analog/clock ground plane. Keep digital signals as far away from sensitive analog inputs, reference lines, and clock inputs as practical. Use a symmetric design of clock input and the analog output lines to minimize 2nd-order harmonic distortion components, thus optimizing the dynamic performance of the DAC. Keep digital signal paths short and run lengths matched to avoid propagation delay and data skew mismatches.

The MAX5895 requires five separate power-supply inputs for the analog (AV

DD1.8

and AV

DD3.3

), digital

(DV

DD1.8

and DV

DD3.3

), and clock (AV

CLK

) circuitry.

Decouple each voltage supply pin with a separate

0.1µF capacitor as close to the device as possible and with the shortest possible connection to the appropriate ground plane. Minimize the analog and digital load capacitances for optimized operation. Decouple all power-supply voltages at the point they enter the PCB with tantalum or electrolytic capacitors. Ferrite beads with additional decoupling capacitors forming a pi-network could also improve performance.

The exposed pad (EP) MUST be soldered to the ground. Use multiple vias, an array of at least 4 x 4

vias, directly under the EP to provide a low thermal and electrical impedance path for the IC.

Static Performance Parameter

Definitions

Integral Nonlinearity (INL)

Integral nonlinearity is the deviation of the values on an actual transfer function from either a best straight-line fit (closest approximation to the actual transfer curve) or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. For a DAC, the deviations are measured at every individual step.

Differential Nonlinearity (DNL)

Differential nonlinearity is the difference between an actual step height and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function.

Offset Error

The offset error is the difference between the ideal and the actual offset current. For a DAC, the offset point is the average value at the output for the two midscale digital input codes with respect to the full-scale of the DAC. This error affects all codes by the same amount.

Gain Error

A gain error is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after nullifying the offset error. This error alters the slope of the transfer function and corresponds to the same percentage error in each step.

Dynamic Performance

Parameter Definitions

Settling Time

The settling time is the amount of time required from the start of a transition until the DAC output settles its new output value to within the specified accuracy.

Noise Spectral Density

The DAC output noise is the sum of the quantization noise and thermal noise. Noise spectral density is the noise power in 1Hz bandwidth, specified in dBFS/Hz.

Signal-to-Noise Ratio (SNR)

For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog output (RMS value) to the RMS quantization error (residual error). The ideal, theoretical maximum SNR can be derived from the DAC’s resolution (N bits):

SNR

= 6.02dBx N + 1.76

MAX5895

However, noise sources such as thermal noise, reference noise, clock jitter, etc. affect the ideal reading. Therefore, SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first four harmonics, and the DC offset.

Spurious-Free Dynamic Range (SFDR)

SFDR is the ratio of the RMS amplitude of the carrier frequency (maximum signal components) to the RMS value of their next largest distortion component. SFDR is usually measured in dBc and with respect to the carrier frequency amplitude or in dBFS with respect to the DAC’s full-scale range. Depending on its test condition, SFDR is observed within a predefined window or to Nyquist.

Two-/Four-Tone Intermodulation

Distortion (IMD)

The two-tone IMD is the ratio expressed in dBc (or dBFS) of the worst 3rd-order (or higher) IMD products to either output tone.

Adjacent Channel Leakage

Power Ratio (ACLR)

Commonly used in combination with WCDMA (wideband code-division multiple-access), ACLR reflects the leakage power ratio in dB between the measured powers within a channel relative to its adjacent channel. ACLR provides a quantifiable method of determining out-of-band spectral energy and its influence on an adjacent channel when a bandwidth-limited RF signal passes through a nonlinear device.

16-Bit, 500Msps Interpolating and Modulating Dual DAC with CMOS Inputs

30 ______________________________________________________________________________________

Pin Configuration

PACKAGE TYPE PACKAGE CODE DOCUMENT NO.

68 QFN-EP G6800-4

21-0122

Package Information

For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.

TOP VIEW

CLKP

CLKN

N.C.

VDD1.8

A15

A14

A13

A12

A11

A10

VDD3.3

DATACLK

A7 17

CLK

EXPOSED PAD

DD1.8

GND

DD3.3

GND

OUTIP

656667

OUTIN

GND

DD3.3

GND

OUTQP

5859606162 5455565763

MAX5895

OUTQN

GND

DD3.3

GND

DD1.8

5253

FSADJ

51 DACREF

REFIO

RESET

48 CS

SCLK

SDI

SDO

DD3.3

37 DV

DD1.8

2322212019 2726252418 2928 323130

DD1.8

A2A3A0

SELIQ/B15

DATACLK/B14

B13

B12

DD1.8

B11

B10

3433

QFN

MAX5895

16-Bit, 500Msps Interpolating and Modulating

Dual DAC with CMOS Inputs

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________

Revision History

REVISION

NUMBER

0 — Initial release —

1 4/07 — —

2 10/08 Add note to setup and hold specifications. 5, 6

REVISION

DATE

DESCRIPTION

PAGES

CHANGED

MAXIM MAX5895 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual