MAXIM MAX5893 Technical data

General Description

The MAX5893 programmable interpolating, modulating,
500Msps, dual digital-to-analog converter (DAC) offers
superior dynamic performance and is optimized for high­performance wideband, single-carrier transmit applica­tions. The device integrates a selectable 2x/4x/8x
interpolating filter, a digital quadrature modulator, and
dual 12-bit high-speed DACs on a single integrated cir­cuit. At 30MHz output frequency and 500Msps update
rate, the in-band SFDR is 84dBc while consuming 1.1W.
The device also delivers 72dB ACLR for single-carrier
WCDMA at a 61.44MHz output frequency.

The selectable interpolating filters allow lower input data
rates while taking advantage of the high DAC update
rates. These linear-phase interpolation filters ease
reconstruction filter requirements and enhance the
passband dynamic performance. Individual offset and
gain programmability allow the user to calibrate out local
oscillator (LO) feedthrough and sideband suppression
errors generated by analog quadrature modulators.

The MAX5893 features a f

IM

/4 digital image-reject mod­ulator. This modulator generates a quadrature-modulat­ed IF signal that can be presented to an analog I/Q
modulator to complete the upconversion process. A
second digital modulation mode allows the signal to be
frequency-translated with image pairs at fIM/2 or fIM/4.

The MAX5893 features a standard 1.8V CMOS, 3.3V tol­erant data input bus for easy interface. A 3.3V SPI™ port
is provided for mode configuration. The programmable
modes include the selection of 2x/4x/8x interpolating fil­ters, f

IM

/2, fIM/4 or no digital quadrature modulation with
image rejection, channel gain and offset adjustment, and
offset binary or two’s complement data interface.

Pin-compatible 14- and 16-bit devices are also available.
Refer to the MAX5894 data sheet for the 14-bit version
and the MAX5895 data sheet for the 16-bit version.

Applications

Base Stations: 3G UMTS, CDMA, and GSM

Broadband Wireless Transmitters

Broadband Cable Infrastructure

Instrumentation and Automatic Test Equipment (ATE)

Analog Quadrature Modulation Architectures

Features

o 72dB ACLR at f

OUT

= 61.44MHz (Single-Carrier

WCDMA)

o Meets 3G UMTS, cdma2000

®

, GSM Spectral Masks

(f

OUT

= 122MHz)

o Noise Spectral Density = -151dBFS/Hz at

f

OUT

= 16MHz

o 90dBc SFDR at Low-IF Frequency (10MHz)

o 86dBc SFDR at High-IF Frequency (50MHz)

o Low Power: 511mW (f

CLK

= 100MHz)

o User Programmable

Selectable 2x, 4x, or 8x Interpolating Filters

< 0.01dB Passband Ripple

> 99dB Stopband Rejection
Selectable Real or Complex Modulator Operation
Selectable Modulator LO Frequency: OFF, fIM/2,
or f

IM

/4
Selectable Output Filter: Lowpass or Highpass
Channel Gain and Offset Adjustment

o EV Kit Available (Order the MAX5893EVKIT)

MAX5893

12-Bit, 500Msps Interpolating and Modulating

Dual DAC with CMOS Inputs

________________________________________________________________

Maxim Integrated Products

1

Ordering Information

Simplified Diagram

19-3546; Rev 2; 10/08

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.

Pin Configuration appears at end of data sheet.

SPI is a trademark of Motorola, Inc.
cdma2000 is a registered trademark of Telecommunications

Industry Association.

Selector Guide

D = Dry pack.

*

EP = Exposed pad.

+

Denotes a lead-free/RoHS-compliant package.

EVALUATION KIT

AVAILABLE

PART TEMP RANGE PIN-PACKAGE

MAX5893EGK-D -40°C to +85°C 68 QFN-EP*

MAX5893EGK+D -40°C to +85°C 68 QFN-EP*

PART

MAX5893 12 500 CMOS

MAX5894 14 500 CMOS

MAX5895 16 500 CMOS

MAX5898 16 500 LVDS

RESOLUTION

(BITS)

DAC UPDATE

RATE (Msps)

DATA

PORT A

DATACLK

DATA

PORT B

DATA SYNCH

AND DEMUX

FILTERS

INTERPOLATING

1x/2x/4x

MODULATOR

FILTERS

INTERPOLATING

DAC

2x

DAC

INPUT

LOGIC

OUTI

OUTQ

MAX5893

12-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(DV

DD1.8

= AV

DD1.8

= 1.8V, AV

CLK

= AV

DD3.3

= DV

DD3.3

= 3.3V, modulator off, 2x interpolation, DATACLK input mode, dual-port

mode, 50Ω double-terminated outputs, external reference at 1.25V, T

A

= -40°C to +85°C, unless otherwise noted. Typical values are

at T

A

= +25°C, unless otherwise noted.) (Note 2)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

DV

DD1.8

, AV

DD1.8

to GND, DACREF ..................-0.3V to +2.16V

AV

DD3.3

, AV

CLK

, DV

DD3.3

to GND, DACREF........-0.3V to +3.9V

DATACLK, A0–A11, B0–B9,

SELIQ/B11, DATACLK/B10, CS, RESET, SCLK,

SDI and SDO to GND, DACREF......-0.3V to (DV

DD3.3

+ 0.3V)

CLKP, CLKN to GND, DACREF..............-0.3V to (AV

CLK

+ 0.3V)

REFIO, FSADJ to GND, DACREF ........-0.3V to (AV

DD3.3

+ 0.3V)

OUTIP, OUTIN, OUTQP,

OUTQN to GND, DACREF..................-1V to (AV

DD3.3

+ 0.3V)

SDO, DATACLK, DATACLK/BIO Continuous Current ..........8mA

Continuous Power Dissipation (TA= +70°C)

68-Pin QFN (derate 41.7mW/°C above +70°C)

(Note 1) ...................................................................3333.3mW

Junction Temperature......................................................+150°C

Operating Temperature Range ...........................-40°C to +85°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

Thermal Resistance θ

JC

(Note 1)....................................0.8°C/W

Note 1: Thermal resistance based on a multilayer board with 4 x 4 via array in exposed pad area.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

STATIC PERFORMANCE

Resolution 12 Bits

Differential Nonlinearity DNL ±0.5 LSB

Integral Nonlinearity INL ±1 LSB

Offset Error OS -0.025 ±0.003 +0.025 %FS

Offset Drift ±0.03 ppm/°C

Full-Scale Gain Error GE

FS

Gain-Error Drift ±110 ppm/°C

Full-Scale Output Current I

OUTFS

Output Compliance -0.5 +1.1 V

Output Resistance R

Output Capacitance C

OUT

OUT

DYNAMIC PERFORMANCE

Maximum Clock Frequency f

Minimum Clock Frequency f

Maximum DAC Update Rate f

Minimum DAC Update Rate f

Maximum Input Data Rate f

CLK

CLK

DAC

DAC

DATA

f

= f

DAC

f

= f

DAC

f

DATACLK

f

= 16MHz, f

OUT

CLK

CLK

= 125MHz,

= 10MHz, -12dBFS

Noise Spectral Density

f

DATACLK

f

OUT

= 125MHz,

= 16MHz, f

= 10MHz, 0dBFS

-4 ±0.6 +4 %FS

220mA

1MΩ

5pF

500 MHz

or f

or f

DAC

DAC

= f

/2 500 Msps

CLK

= f

/2 1 Msps

CLK

125 MWps

No interpolation -151

OFFSET

2x interpolation -147

4x interpolation -148

OFFSET

4x interpolation -145

1 MHz

dBFS/

Hz

MAX5893

12-Bit, 500Msps Interpolating and Modulating

Dual DAC with CMOS Inputs

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(DV

DD1.8

= AV

DD1.8

= 1.8V, AV

CLK

= AV

DD3.3

= DV

DD3.3

= 3.3V, modulator off, 2x interpolation, DATACLK input mode, dual-port

mode, 50Ω double-terminated outputs, external reference at 1.25V, T

A

= -40°C to +85°C, unless otherwise noted. Typical values are

at T

A

= +25°C, unless otherwise noted.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

In-Band SFDR
(DC to f

DATA

/2)

SFDR

Two-Tone IMD TTIMD

f

DATACLK

= 125MHz,

interpolation off, 0dBFS

f

DATACLK

= 125MHz,

2x interpolation, 0dBFS

f

DATACLK

= 125MHz,

4x interpolation, 0dBFS

f

DATACLK

f

OUT1

= 125MHz,

= 9MHz, f

OUT2

10MHz, -6.1dBFS

f

= 125MHz, f

DATA

= 79MHz, f

OUT2

=

80MHz, -6.1dBFS

f

DATACLK

f

OUT1

= 62.5MHz,

= 9MHz, f

OUT2

10MHz, -6.1dBFS

f

= 10MHz 90

OUT

f

= 30MHz 83

OUT

= 50MHz 72

f

OUT

f

= 10MHz 77 88

OUT

f

= 30MHz 83

OUT

f

= 50MHz 84

OUT

f

= 10MHz 90

OUT

f

= 30MHz 84

OUT

f

= 50MHz 86

OUT

No interpolation -100

2x interpolation -100

=

4x interpolation -100

2x interpolation,
f

OUT1

/4 complex

IM

modulation

-73

4x interpolation,

/4 complex

f

IM

-75

modulation

=

8x interpolation -99

dBc

dBc

Four-Tone IMD FTIMD

ACLR for WCDMA
(Note 3)

ACLR

f

DATACLK

f

OUT1

= 70MHz, -6.1dBFS

f

DATACLK

f

OUT1

= 180MHz, -6.1dBFS

f

DATACLK

= 62.5MHz,

= 69MHz, f

= 62.5MHz,

= 179MHz, f

= 125MHz, f

OUT2

OUT2

8x interpolation,

/4 complex

f

IM

modulation

8x, highpass
interpolation,
f

/4 complex

IM

modulation

spaced 1MHz

OUT

apart from 32MHz, -12dBFS, 2x
interpolation

f

DATACLK

f

OUT

f

DATACLK

= 61.44MHz,

= baseband

=

122.88MHz, f

61.44MHz

f

DATACLK

=

122.88MHz, f

122.88MHz

OUT

OUT

=

=

4x interpolation 74

8x interpolation 73

2x interpolation,
fIM/4 complex
modulation

4x interpolation,
fIM/4 complex
modulation

-67

-62

-93 dBc

73

dB

69

MAX5893

12-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(DV

DD1.8

= AV

DD1.8

= 1.8V, AV

CLK

= AV

DD3.3

= DV

DD3.3

= 3.3V, modulator off, 2x interpolation, DATACLK input mode, dual-port

mode, 50Ω double-terminated outputs, external reference at 1.25V, T

A

= -40°C to +85°C, unless otherwise noted. Typical values are

at T

A

= +25°C, unless otherwise noted.) (Note 2)

Output Propagation Delay t

Output Rise Time t

Output Fall Time t

Output Settling Time To 0.5% (Note 5) 11 ns

Output Bandwidth -1dB bandwidth (Note 6) 240 MHz

Passband Width Ripple < -0.01dB

Stopband Rejection

Data Latency

DAC INTERCHANNEL MATCHING

Gain Match ∆Gain f
Gain-Match Tempco ∆Gain/°C I
Phase Match ∆Phase f
Phase-Match Tempco ∆Phase/°C f

DC Gain Match I

Channel-to-Channel Crosstalk f

REFERENCE

Reference Input Range 0.125 1.250 V

Reference Output Voltage V

Reference Input Resistance R

Reference Voltage Drift ±50 ppm/°C

CMOS LOGIC INPUT/OUTPUT (A11–A0, SELIQ/B11, DATACLK/B10, B9–B0, DATACLK)

Input High Voltage V

Input Low Voltage V

Input Current I

Input Capacitance C

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

PD

RISE

FALL

REFIO

REFIO

IH

IL

IN

IN

1x interpolation (Note 4) 2.9 ns

10% to 90% (Note 5) 0.75 ns

10% to 90% (Note 5) 1 ns

0.604 x f

0.604 x f

0.604 x f

1x interpolation 22

2x interpolation 70

4x interpolation 146

8x interpolation 311

OUT

OUTFS

OUT

OUT

OUTFS

OUT

Internal reference 1.14 1.20 1.27 V

DATA

DATA

DATA

= DC - 80MHz, I

= 20mA ±0.02 ppm/°C

= 60MHz, I

= 60MHz, I

= 20mA -0.2 ±0.04 +0.2 dB

= 50MHz, f

0.4 x

f

DATA

, 2x interpolation 100

, 4x interpolation 100

, 8x interpolation 100

= 20mA ±0.1 dB

OUTFS

= 20mA ±0.13 Deg

OUTFS

= 20mA ±0.006 Deg/°C

OUTFS

= 250MHz, 0dBFS -90 dB

DAC

10 kΩ

0.7 x

DV

DD1.8

0.3 x

DV

±1 ±20 µA

3pF

DD1.8

dB

Clock

Cycles

V

V

MAX5893

12-Bit, 500Msps Interpolating and Modulating

Dual DAC with CMOS Inputs

_______________________________________________________________________________________ 5

ELECTRICAL CHARACTERISTICS (continued)

(DV

DD1.8

= AV

DD1.8

= 1.8V, AV

CLK

= AV

DD3.3

= DV

DD3.3

= 3.3V, modulator off, 2x interpolation, DATACLK input mode, dual-port

mode, 50Ω double-terminated outputs, external reference at 1.25V, T

A

= -40°C to +85°C, unless otherwise noted. Typical values are

at T

A

= +25°C, unless otherwise noted.) (Note 2)

Output High Voltage V

Output Low Voltage V

Output Leakage Current Three-state 1 µA

Rise/Fall Time C

CLOCK INPUT (CLKP, CLKN)

Differential Input Voltage Swing V

Differential Input Slew Rate > 100 V/µs

Common-Mode Voltage V

Input Resistance R

Input Capacitance C

Minimum Clock Duty Cycle 45 %

Maximum Clock Duty Cycle 55 %

CLKP/CLKN, DATACLK TIMING (Figure 4) (Notes 7, 8)

CLK to DATACLK Delay t

Data Hold Time, DATACLK
Input/Output (Pin 14)

Data Setup Time, DATACLK
Input/Output (Pin 14)

Data Hold Time, DATACLK/B10
Input/Output (Pin 27)

Data Setup Time, DATACLK/B10
Input/Output (Pin 27)

SERIAL PORT INTERFACE TIMING (Figure 3) (Note 7)

SCLK Frequency f
CS Setup Time t

Input Hold Time t

Input Setup Time t

Data Valid Duration t

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

OH

OL

DIFF

COM

CLK

CLK

D

t

DH

t

DS

t

DH

t

DS

SCLK

SS

SDH

SDS

SDV

200µA load

200µA load

Sine-wave input > 1.5

Square-wave input > 0.5

AC-coupled AV

DATACLK output mode, C

Capturing rising edge 1.0

Capturing falling edge 2.1

Capturing rising edge 0.4

Capturing falling edge -0.7

Capturing rising edge 1.0

Capturing falling edge 2.3

Capturing rising edge 0.2

Capturing falling edge -0.4

= 10pF, 20% to 80% 1.6 ns

LOAD

0.8 x

DV

DD3.3

= 10pF 6.2 ns

LOAD

2.5 ns

0ns

4.5 ns

6.5 16.5 ns

0.2 x

DV

DD3.3

/2 V

CLK

5kΩ

3pF

10 MHz

V

V

V

P-P

ns

ns

ns

ns

MAX5893

12-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs

6 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(DV

DD1.8

= AV

DD1.8

= 1.8V, AV

CLK

= AV

DD3.3

= DV

DD3.3

= 3.3V, modulator off, 2x interpolation, DATACLK input mode, dual-port

mode, 50Ω double-terminated outputs, external reference at 1.25V, T

A

= -40°C to +85°C, unless otherwise noted. Typical values are

at T

A

= +25°C, unless otherwise noted.) (Note 2)

Note 2: All specifications are 100% tested at T

A

≥ +25°C. Specifications at TA< +25°C are guaranteed by design and characteriza-

tion data.

Note 3: 3.84MHz bandwidth, single carrier.
Note 4: Excludes data latency.
Note 5: Measured single-ended into a 50Ω load.
Note 6: Excludes sin(x)/x rolloff.
Note 7: Guaranteed by design and characterization.
Note 8: Setup and hold time specifications characterized with 3.3V CMOS logic levels.
Note 9: Parameter defined as the change in midscale output caused by a ±5% variation in the nominal supply voltage.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

POWER SUPPLIES

Digital Supply Voltage DV

Digital I/O Supply Voltage DV

Clock Supply Voltage AV

Analog Supply Voltage

AV

AV

I

AVDD3.3

Analog Supply Current

I

AVDD1.8

Digital Supply Current I

Digital I/O Supply Current I

Clock Supply Current I

DVDD1.8

DVDD3.3

AVCLK

Total Power Dissipation P

Power-Down Current

AV
Ratio

Power-Supply Rejection

DD3.3

PSRR

DD1.8

DD3.3

CLK

DD3.3

DD1.8

TOTAL

1.71 1.8 1.89 V

3.0 3.3 3.6 V

3.135 3.3 3.465 V

3.135 3.3 3.465

1.71 1.8 1.89

f

= 250MHz, 2x interpolation, 0dBFS,

CLK

f

= 10MHz, DATACLK output mode

OUT

f

= 250MHz, 2x interpolation, 0dBFS,

CLK

f

= 10MHz, DATACLK output mode

OUT

f

= 250MHz, 2x interpolation, 0dBFS,

CLK

= 10MHz, DATACLK output mode

f

OUT

f

= 250MHz, 2x interpolation, 0dBFS,

CLK

= 10MHz, DATACLK output mode

f

OUT

f

= 250MHz, 2x interpolation, 0dBFS,

CLK

= 10MHz, DATACLK output mode

f

OUT

110 130

27 32

205 250 mA

21 32 mA

35mA

511 mW

AV

DD3.3

AV

DV

DV

AV

DD1.8

DD1.8

DD3.3

CLK

All I/O are static high or
low, bit 2 to bit 4 of
address 00h are set high

(Note 9) 0.05 %FS/V

A

450

1

10

100

1

V

mA

µA

MAX5893

12-Bit, 500Msps Interpolating and Modulating

Dual DAC with CMOS Inputs

_______________________________________________________________________________________

7

Y

Typical Operating Characteristics

(DV

DD1.8

= AV

DD1.8

= 1.8V, AV

CLK

= AV

DD3.3

= DV

DD3.3

= 3.3V, modulator off, 2x interpolation, output is transformer-coupled to

50Ω load, T

A

= +25°C, unless otherwise noted.)

IN-BAND SFDR vs. OUTPUT FREQUENCY

f

120

100

80

60

SFDR (dBc)

40

20

0

050

IN-BAND SFDR vs. OUTPUT FREQUENCY

f

120

100

80

60

SFDR (dBc)

40

20

0

050

IN-BAND SFDR vs. OUTPUT FREQUENCY

f

90

80

70

60

50

40

SFDR (dBc)

30

20

10

0

125 175

DATA

SPURS MEASURED BETWEEN
0MHz AND 62.5MHz

DATA

SPURS MEASURED BETWEEN
0MHz AND 62.5MHz

DATA

-6dBFS

UPPER SIDEBAND MODULATION
SPURS MEASURED BETWEEN
125MHz AND 187.5MHz

= 125MWps, 2x INTERPOLATION

-6dBFS

-12dBFS

OUTPUT FREQUENCY (MHz)

-0.1dBFS

40302010

= 125MWps, 4x INTERPOLATION

-6dBFS

OUTPUT FREQUENCY (MHz)

-0.1dBFS

-12dBFS

40302010

= 125MWps, 4x INTERPOLATION

-0.1dBFS

-12dBFS

165155145135

OUTPUT FREQUENCY (MHz)

MAX5893 toc01

MAX5893 toc04

MAX5893 toc07

100

SFDR (dBc)

SFDR (dBc)

120

100

TWO-TONE IMD (-dBc)

0UT-OF-BAND SFDR vs. OUTPUT FREQUENCY

= 125MWps, 2x INTERPOLATION

f

DATA

-12dBFS

90

80

70

60

50

40

30

20

10

-6dBFS

-0.1dBFS

SPURS MEASURED BETWEEN

62.5MHz AND 125MHz

0

050

OUTPUT FREQUENCY (MHz)

40302010

MAX5893 toc02

OUT-OF-BAND SFDR vs. OUTPUT FREQUENC

f

= 125MWps, 4x INTERPOLATION

DATA

90

80

70

60

-6dBFS

50

40

30

20

SPURS MEASURED BETWEEN

10

62.5MHz AND 250MHz

0

050

-0.1dBFS

MAX5893 toc05

-12dBFS

40302010

OUTPUT FREQUENCY (MHz)

TWO-TONE IMD vs. OUTPUT FREQUENCY

= 125MWps, 2x INTERPOLATION

f

DATA

80

60

40

20

0

0

-9dBFS

1MHz CARRIER SPACING
COMPLEX MODULATION FOR
OUTPUT FREQUENCIES
GREATER THAN 50MHz

CENTER FREQUENCY (MHz)

-12dBFS

-6dBFS

MAX5893 toc08

100755025

IN-BAND SFDR vs. OUTPUT FREQUENCY

= 125MWps, 2x INTERPOLATION

f

DATA

90

80

70

60

50

40

SFDR (dBc)

30

20

UPPER SIDEBAND MODULATION
SPURS MEASURED BETWEEN

10

62.5MHz AND 125MHz

0

62.5 112.5

IN-BAND SFDR vs. OUTPUT FREQUENCY

= 125MWps, 4x INTERPOLATION

f

DATA

100

90

80

70

60

-6dBFS

50

SFDR (dBc)

40

30

20

LOWER SIDEBAND MODULATION
SPURS MEASURED BETWEEN

10

62.5MHz AND 125MHz

0

75 125

TWO-TONE IMD vs. OUTPUT FREQUENCY

f

DATA

120

90

60

TWO-TONE IMD (-dBc)

30

1MHz CARRIER SPACING
COMPLEX MODULATION FOR
OUTPUT FREQUENCIES
GREATER THAN 50MHz

0

0

-6dBFS

-0.1dBFS -12dBFS

102.592.582.572.5

OUTPUT FREQUENCY (MHz)

-0.1dBFS

-12dBFS

1151059585

OUTPUT FREQUENCY (MHz)

= 125Msps, 4x INTERPOLATION

-6dBFS

-12dBFS

-9dBFS

150120906030

CENTER FREQUENCY (MHz)

MAX5893 toc03

MAX5893 toc06

MAX5893 toc09

MAX5893

12-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs

8 _______________________________________________________________________________________

Typical Operating Characteristics (continued)

(DV

DD1.8

= AV

DD1.8

= 1.8V, AV

CLK

= AV

DD3.3

= DV

DD3.3

= 3.3V, modulator off, 2x interpolation, output is transformer-coupled to

50Ω load, T

A

= +25°C, unless otherwise noted.)

GAIN MISMATCH vs. TEMPERATURE

= 125Msps, 2x INTERPOLATION

f

DATA

0.100

f

= 22.7MHz

OUT

= -6dBFS

A

OUT

0.075

0.050

GAIN MISMATCH (dB)

0.025

0

-40 85

TEMPERATURE (°C)

603510-15

MAX5893 toc10

DIFFERENTIAL NONLINEARITY

vs. DIGITAL INPUT CODE

1.0

0.5

0

DNL (LSB)

-0.5

-1.0
512

0 4096

1536

1024

DIGITAL INPUT CODE

2048

2560

3072

3584

MAX5893 toc11

INL (LSB)

1.00

0.75

0.50

0.25

0

-0.25

-0.50

-0.75

-1.00

INTEGRAL NONLINEARITY

vs. DIGITAL INPUT CODE

1536

512

0 4096

1024

DIGITAL INPUT CODE

2048

2560

3072

MAX5893 toc12

3584

SUPPLY CURRENTS vs. DAC UPDATE RATE

3.3V TOTAL

(MHz)

OUT

= 5MHz

250200150

2x INTERPOLATION, f

500

450

400

350

300

250

200

150

SUPPLY CURRENT (mA)

100

50

0

100 300

1.8V TOTAL

f

DAC

MAX5893 toc13

SUPPLY CURRENTS vs. DAC UPDATE RATE

1.8V TOTAL

3.3V TOTAL

(MHz)

OUT

= 5MHz

400300200

4x INTERPOLATION, f

500

450

400

350

300

250

200

150

SUPPLY CURRENT (mA)

100

50

0

100 500

f

DAC

SUPPLY CURRENTS vs. DAC UPDATE RATE

8x INTERPOLATION, f

500

450

MAX5893 toc14

400

350

300

250

200

150

SUPPLY CURRENT (mA)

100

50

0

100 500

f

(MHz)

DAC

OUT

1.8V TOTAL

3.3V TOTAL

= 5MHz

MAX5893 toc15

400300200

MAX5893

12-Bit, 500Msps Interpolating and Modulating

Dual DAC with CMOS Inputs

_______________________________________________________________________________________

9

Typical Operating Characteristics (continued)

(DV

DD1.8

= AV

DD1.8

= 1.8V, AV

CLK

= AV

DD3.3

= DV

DD3.3

= 3.3V, modulator off, 2x interpolation, output is transformer-coupled to

50Ω load, T

A

= +25°C, unless otherwise noted.)

WCDMA ACLR vs. OUTPUT FREQUENCY

f

DATA

= 122.88MWps, 4x INTERPOLATION

MAX5893 toc16

f

CENTER

(MHz)

ACLR (dB)

1208040

50

60

70

80

90

100

40

0 160

SINGLE-CARRIER
ALTERNATE CHANNEL

SINGLE-CARRIER
ADJACENT CHANNEL

WCDMA ACLR vs. OUTPUT FREQUENCY

f

DATA

= 76.8MWps, 4x INTERPOLATION

MAX5893 toc17

f

CENTER

(MHz)

ACLR (dB)

8040

50

60

70

80

90

100

40

0

SINGLE-CARRIER
ALTERNATE CHANNEL

SINGLE-CARRIER
ADJACENT CHANNEL

MAX5893 toc18

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-120

WCDMA ACLR SPECTRAL PLOT

f

DATA

= 61.44MWps, 8x INTERPOLATION

f

CENTER

= 61.44MHz

SPAN = 25.5MHz

ACLR2 = 73dB

OUTPUT POWER (dBm)

ACLR1 = 73dB

ACLR1 = 72dB

ACLR2 = 73dB

CARRIER = -12dBm

WCDMA ACLR SPECTRAL PLOT
= 122.88MWps, 4x INTERPOLATION

f

DATA

-20

-30

-40

-50

-60

-70

-80

-90

OUTPUT POWER (dBm)

-100

-110

-120

ACLR2 = 71dB

ACLR1 = 69dB

CARRIER = -14dBm

f

= 122.88MHz

CENTER

SPAN = 25.5MHz

ACLR2 = 70dB

ACLR1 = 69dB

MAX5893 toc19

MAX5893

12-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs

10 ______________________________________________________________________________________

Pin Description

PIN NAME FUNCTION

1 CLKP Noninverting Differential Clock Input

2 CLKN Inverting Differential Clock Input

3, 4, 5, 22–25,

40–43

6, 21, 30, 37 DV

7–12, 15–20 A11–A0

N.C. Internally Connected. Do not connect.

DD1.8

Digital Power Supply. Accepts a 1.71V to 1.89V supply range. Bypass each pin to ground with a

0.1µF capacitor as close to the pin as possible.

A-Port Data Inputs.
Dual-port mode:
I-channel data input. Data is latched on the rising/falling edge (programmable) of the DATACLK.
Single-port mode:
I-channel and Q-channel data input, with SELIQ.

13, 44 DV

14 DATACLK Programmable Data Clock Input/Output. See the DATACLK Modes section for details.

26 SELIQ/B11

27 DATACLK/B10

28, 29, 31–36,

38, 39

45 SDO Serial-Port Data Output

46 SDI Serial-Port Data Input

47 SCLK Serial-Port Clock Input. Data on SDI is latched on the rising edge of SCLK.
48 CS Serial-Port Interface Select. Drive CS low to enable serial-port interface.
49 RESET Reset Input. Set RESET low during power-up.

50 REFIO Reference Input/Output. Bypass to ground with a 1µF capacitor as close to the pin as possible.

51 DACREF

52 FSADJ

DD3.3

B9–B0

CMOS I/O Power Supply. Accepts a 3.0V to 3.6V supply range. Bypass each pin to ground with a

0.1µF capacitor as close to the pin as possible.

Select I/Q-Channel Input or B-Port MSB Input.
Single-port mode:
If SELIQ = LOW, data is latched into Q-channel on the rising/falling edge (programmable) of
the DATACLK.
If SELIQ = HIGH, data is latched into I-channel on the rising/falling edge (programmable) of the
DATACLK.
Dual-port mode:
Q-channel MSB input.

Alternate DATACLK Input/Output or B-Port Bit 10 Input.
Single-port mode:
See the DATACLK Modes section for details.
Dual-port mode:
Q-channel bit 10 input.
If unused connect to GND.

B-Port Data Bits 9–0.
Dual-port mode:
Q-channel inputs. Data is latched on the rising/falling (programmable) edge of the DATACLK.
Single-port mode:
Connect to GND.

C ur r ent- S et Resi stor Retur n P ath. For a 20m A ful l - scal e outp ut cur r ent, connect a 2kΩ r esi stor b etw een
FS AD J and D AC RE F. Inter nal l y connected to GN D . D o no t u s e a s a n e x t e r n a l g r o u n d co n n e c t io n .

Full-Scale Adjust Input. This input sets the full-scale output current of the DAC. For a 20mA full­scale output current, connect a 2kΩ resistor between FSADJ and DACREF.