MAXIM MAX5891 Technical data

General Description
The MAX5891 advanced 16-bit, 600Msps, digital-to­analog converter (DAC) meets the demanding perfor­mance requirements of signal synthesis applications found in wireless base stations and other communica­tions applications. Operating from 3.3V and 1.8V sup­plies, the MAX5891 DAC supports update rates of 600Msps using high-speed LVDS inputs while consum­ing only 298mW of power and offers exceptional dynamic performance such as 80dBc spurious-free dynamic range (SFDR) at f
OUT
= 30MHz.
The MAX5891 utilizes a current-steering architecture that supports a 2mA to 20mA full-scale output current range, and produces -2dBm to -22dBm full-scale output signal levels with a double-terminated 50Ω load. The MAX5891 features an integrated 1.2V bandgap reference and con­trol amplifier to ensure high-accuracy and low-noise per­formance. A separate reference input (REFIO) allows for the use of an external reference source for optimum flexi­bility and improved gain accuracy.
The MAX5891 digital inputs accept LVDS voltage lev­els, and the flexible clock input can be driven differen­tially or single-ended, AC- or DC-coupled. The MAX5891 is available in a 68-pin QFN package with an exposed paddle (EP) and is specified for the extended (-40°C to +85°C) temperature range.
Refer to the MAX5890 and MAX5889 data sheets for pin­compatible 14-bit and 12-bit versions of the MAX5891.
Applications
Base Stations: Single/Multicarrier UMTS, CDMA, GSM
Communications: Fixed Broadband Wireless Access, Point-to-Point Microwave
Direct Digital Synthesis (DDS)
Cable Modem Termination Systems (CMTS)
Automated Test Equipment (ATE)
Instrumentation
Features
600Msps Output Update Rate
Low Noise Spectral Density: -163dBFS/Hz at
f
OUT
= 36MHz
Excellent SFDR and IMD Performance
SFDR = 80dBc at f
OUT
= 30MHz (to Nyquist)
SFDR = 71dBc at f
OUT
= 130MHz (to Nyquist)
IMD = -95dBc at f
OUT
= 30MHz
IMD = -70dBc at f
OUT
= 130MHz
ACLR = 73dB at f
OUT
= 122.88MHz
2mA to 20mA Full-Scale Output Current
LVDS-Compatible Digital Inputs
On-Chip 1.2V Bandgap Reference
Low 298mW Power Dissipation at 600Msps
Compact (10mm x 10mm) QFN-EP Package
Evaluation Kit Available (MAX5891EVKIT)
MAX5891
16-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
19-3542; Rev 4; 2/07
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
EVALUATION KIT
AVAILABLE
PART
TEMP
RANGE
PIN­PACKAGE
PKG
CODE
M AX5891E GK-D
68 QFN -E P *
G6800- 4
M AX5891E GK+D
68 QFN -E P *
G6800- 4
MAX5891
1.2V
REFERENCE
REFIO
DACREF
FSADJ
CLK
INTERFACE
600MHz
16-BIT DAC
LATCH
LVDS
RECEIVER
D0–D15
LVDS DATA
INPUTS
POWER
DOWN
PD
CLKP
CLKN
OUTP
OUTN
Functional Diagram
PART
RESOLUTION
(BITS)
UPDATE RATE
(Msps)
LOGIC INPUT
MAX5889
12 600 LVDS
MAX5890
14 600 LVDS
MAX5891
16 600 LVDS
Selector Guide
Pin Configuration appears at end of data sheet.
*
EP = Exposed paddle.
+ = Lead-free package. D = Dry pack.
- 40°C to + 85°C
- 40°C to + 85°C
MAX5891
16-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= 3.3V, AV
DD1.8
= DV
DD1.8
= 1.8V, external reference V
REFIO
= 1.2V, output load 50Ω double-terminated,
transformer-coupled output, I
OUT
= 20mA, TA= -40°C to +85°C, unless otherwise noted. Specifications at TA≥ +25°C are guaranteed
by production testing. Specifications at T
A
< +25°C are guaranteed by design and characterization. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
AV
DD1.8
, DV
DD1.8
to AGND, DGND, DACREF,
and CGND.......................................................-0.3V to +2.16V
AV
DD3.3
, DV
DD3.3
, AV
CLK
to AGND, DGND,
DACREF, and CGND.........................................-0.3V to +3.9V
REFIO, FSADJ to AGND, DACREF,
DGND, and CGND ..........................-0.3V to (AV
DD3.3
+ 0.3V)
OUTP, OUTN to AGND, DGND, DACREF,
and CGND .......................................-1.2V to (AV
DD3.3
+ 0.3V)
CLKP, CLKN to AGND, DGND, DACREF,
and CGND..........................................-0.3V to (AV
CLK
+ 0.3V)
PD to AGND, DGND, DACREF,
and CGND.......................................-0.3V to (DV
DD3.3
+ 0.3V)
Digital Data Inputs (D0N–D15N, D0P–D15P) to AGND,
DGND, DACREF, and CGND ..........-0.3V to (DV
DD1.8
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C) (Note 1)
68-Pin QFN-EP (derate 28.6mW/°C above +70°C)....3333mW
Thermal Resistance
θ
JA
(Note 1) ....................................24°C/W
Operating Temperature Range ..........................-40°C to +85°C
Junction Temperature .....................................................+150°C
Storage Temperature Range ............................-60°C to +150°C
Lead Temperature (soldering, 10s) ................................+300°C
PARAMETER
CONDITIONS
UNITS
STATIC PERFORMANCE
Resolution 16 Bits
Integral Nonlinearity INL Measured differentially
LSB
Differential Nonlinearity DNL Measured differentially
LSB
Offset Error OS
%FS
Full-Scale Gain Error GE
FS
External reference -4 ±1 +4
%FS
Internal reference
Gain-Drift Tempco
External reference
ppm/°C
Full-Scale Output Current I
OUT
220mA
Output Compliance Single-ended
V
Output Resistance R
OUT
1MΩ
Output Capacitance C
OUT
5pF
Output Leakage Current PD = high, power-down mode ±1µA
DYNAMIC PERFORMANCE
Maximum DAC Update Rate
Msps
Minimum DAC Update Rate 1
Msps
f
OUT
= 36MHz
Noise Spectral Density N
-12dBFS, 20MHz offset from the carrier
f
OUT
= 151MHz
dBFS/Hz
Note 1: Thermal resistance based on a multilayer board with 4x4 via array in exposed paddle area
SYMBOL
MIN TYP MAX
±3.8
±2.8
-0.02 ±0.001 +0.02
±130 ±100
f
= 500MHz,
CLK
A
FULL-SCALE
A
FULL-SCALE
= -3.5dBm
= -6.4dBm
-1.0 +1.1
600
-163
-155
MAX5891
16-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
_______________________________________________________________________________________ 3
PARAMETER
CONDITIONS
UNITS
f
OUT
= 16MHz 89
f
CLK
= 200MHz,
0dBFS (Note 2)
f
OUT
= 30MHz 85
f
OUT
= 16MHz 79
f
OUT
= 30MHz 81
76 81
80
71
Spurious-Free Dynamic Range to Nyquist
SFDR
f
CLK
= 500MHz,
0dBFS
56
dBc
f
CLK
= 500MHz
f
OUT1
= 29MHz,
f
OUT2
= 30MHz,
-6.5dBFS per tone
-95
Two-Tone IMD TTIMD
f
CLK
= 500MHz
f
OUT1
= 129MHz,
f
OUT2
= 130MHz,
-6.5dBFS per tone
-70
dBc
f
CLK
= 491.52MHz,
f
OUT
= 30.72MHz
82
WCDMA single carrier
f
CLK
= 491.52MHz,
f
OUT
= 122.88MHz
73
f
CLK
= 491.52MHz,
f
OUT
= 30.72MHz
74
Adjacent Channel Leakage Power Ratio
ACLR
WCDMA four carriers
f
CLK
= 491.52MHz,
f
OUT
= 122.88MHz
67
dB
Output Bandwidth
(Note 4)
MHz
REFERENCE
Internal Reference Voltage Range
V
REFIO
1.2
V
Reference Input Voltage Range
Using external reference
1.2
V
Reference Input Resistance R
REFIO
10 kΩ
Reference Voltage Temperature Drift
ppm/°C
ANALOG OUTPUT TIMING (Figure 3)
Output Fall Time t
FALL
90% to 10% (Note 5) 0.4 ns
Output Rise Time t
RISE
10% to 90% (Note 5) 0.4 ns
Output Propagation Delay t
PD
Reference to data latency (Note 5) 2.5 ns
Output Settling Time To 0.025% of the final value (Note 5) 11 ns
Glitch Impulse Measured differentially 1
pVs
I
OUT
= 2mA 30
Output Noise N
OUT
I
OUT
= 20mA 30
pA/Hz
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= 3.3V, AV
DD1.8
= DV
DD1.8
= 1.8V, external reference V
REFIO
= 1.2V, output load 50Ω double-terminated,
transformer-coupled output, I
OUT
= 20mA, TA= -40°C to +85°C, unless otherwise noted. Specifications at TA≥ +25°C are guaranteed
by production testing. Specifications at T
A
< +25°C are guaranteed by design and characterization. Typical values are at TA= +25°C.)
SYMBOL
f
= 200MHz,
CLK
MIN TYP MAX
-12dBFS (Note 2)
f
= 16MHz (Note 3)
OUT
f
= 30MHz (Note 2)
OUT
f
= 130MHz (Note 2)
OUT
f
= 200MHz (Note 2)
OUT
BW
-1dB
1000
V
REFIOCR
TCO
REF
1.14
0.10
±30
1.26
1.32
MAX5891
16-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs
4 _______________________________________________________________________________________
PARAMETER
CONDITIONS
UNITS
TIMING CHARACTERISTICS
Input Data Rate 600
Mwps
Data Latency 5.5
Clock
cycles
Data to Clock Setup Time t
SETUP
ns
Data to Clock Hold Time t
HOLD
2.6 ns
Clock Frequency f
CLK
CLKP, CLKN 600
MHz
Minimum Clock Pulse-Width High
t
CH
CLKP, CLKN 0.6 ns
Minimum Clock Pulse-Width Low
t
CL
CLKP, CLKN 0.6 ns
Turn-On Time t
SHDN
External reference, PD falling edge to output settle within 1%
µs
CMOS LOGIC INPUT (PD)
Input Logic High V
IH
0.7 x V
Input Logic Low V
IL
0.3 x V
Input Current I
IN
-10
µA
Input Capacitance C
IN
3pF
LVDS INPUTS
Differential Input High
(Notes 6, 7, 8)
mV
Differential Input Low
(Notes 6, 7, 8)
mV
Internal Common-Mode Bias
V
E xter nal C om m on- M od e Tol er ance
(Notes 6, 8) 0.8
V
DD1.8
-
0.15
V
Differential Input Resistance
Ω
Common-Mode Input Resistance
3.2 kΩ
Input Capacitance
3pF
DIFFERENTIAL CLOCK INPUTS (CLKP, CLKN)
Clock Common-Mode Voltage CLKP and CLKN are internally biased
V
Minimum Differential Input Voltage Swing
0.5
V
P-P
Minimum Common-Mode Voltage
1V
Maximum Common-Mode Voltage
1.9 V
Input Resistance R
CLK
Single-ended 5 kΩ
Input Capacitance C
CLK
3pF
POWER SUPPLIES
3.3
Analog Supply Voltage Range
1.8
V
Clock Supply Voltage Range AV
CLK
3.3
V
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= 3.3V, AV
DD1.8
= DV
DD1.8
= 1.8V, external reference V
REFIO
= 1.2V, output load 50Ω double-terminated,
transformer-coupled output, I
OUT
= 20mA, TA= -40°C to +85°C, unless otherwise noted. Specifications at TA≥ +25°C are guaranteed
by production testing. Specifications at T
A
< +25°C are guaranteed by design and characterization. Typical values are at TA= +25°C.)
SYMBOL
MIN TYP MAX
Referenced to rising edge of clock (Note 6) -1.5
V
IHLVDS
V
ILLVDS
V
ICMLVDS
V
ECMLVDS
R
IDLVDS
R
ICMLVDS
C
INLVDS
AV
DD3.3
AV
DD1.8
Referenced to rising edge of clock (Note 6)
DV
DD3.3
+100 +1000
-1000 -100
1.125 1.375
AV
3.135
1.710
3.135
350
DV
DD3.3
±1.8 +10
110
/ 2
CLK
3.465
1.890
3.465
MAX5891
16-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
_______________________________________________________________________________________ 5
Note 2: Parameter tested with input data pattern based on 16,384 data points. f
OUT
has been chosen so the corresponding input pattern
contains prime number of f
OUT
cycles and is a nonrepetitive sequence. f
OUT
has been rounded to the nearest MHz number in both
the Electrical Characteristics table and Typical Operating Characteristics.
Note 3: Parameter tested exactly at f
OUT
= 16.204833984375MHz and with a clock frequency of 500MHz at an output amplitude of 0dBFS.
Note 4: This parameter does not include update-rate-dependent effects of sin(x)/x filtering inherent in the MAX5891. Note 5: Parameter measured single-ended with 50Ω double-terminated outputs. Note 6: Not production tested. Guaranteed by design. Note 7: Differential input voltage defined as V
D_P
- V
D_N
.
Note 8: Combination of logic-high/-low and common-mode voltages must not exceed absolute maximum rating for D_P/D_N inputs. Note 9: Parameter defined as the change in midscale output caused by a ±5% variation in the nominal supply voltages.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
3.3
Digital Supply Voltage Range
1.8
V
f
CLK
= 100MHz, f
OUT
= 16MHz
f
CLK
= 500MHz, f
OUT
= 16MHz
f
CLK
= 600MHz, f
OUT
= 16MHz
f
CLK
= 100MHz, f
OUT
= 16MHz
f
CLK
= 500MHz, f
OUT
= 16MHz 50 58
Analog Supply Current
f
CLK
= 600MHz, f
OUT
= 16MHz 61
mA
f
CLK
= 100MHz, f
OUT
= 16MHz 2.8
f
CLK
= 500MHz, f
OUT
= 16MHz 2.8 3.6
Clock Supply Current I
AVCLK
f
CLK
= 600MHz, f
OUT
= 16MHz 2.8
mA
f
CLK
= 100MHz, f
OUT
= 16MHz 0.2
f
CLK
= 500MHz, f
OUT
= 16MHz 0.2 0.5
f
CLK
= 600MHz, f
OUT
= 16MHz 0.2
f
CLK
= 100MHz, f
OUT
= 16MHz
f
CLK
= 500MHz, f
OUT
= 16MHz 44 50
Digital Supply Current
f
CLK
= 600MHz, f
OUT
= 16MHz
mA
f
CLK
= 100MHz, f
OUT
= 16MHz
f
CLK
= 500MHz, f
OUT
= 16MHz
301
f
CLK
= 600MHz, f
OUT
= 16MHz
mW
Total Power Dissipation P
DISS
Power-down, clock static low, data input static
13 µW
Power-Supply Rejection Ratio PSRR (Note 9)
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= 3.3V, AV
DD1.8
= DV
DD1.8
= 1.8V, external reference V
REFIO
= 1.2V, output load 50Ω double-terminated,
transformer-coupled output, I
OUT
= 20mA, TA= -40°C to +85°C, unless otherwise noted. Specifications at TA≥ +25°C are guaranteed
by production testing. Specifications at T
A
< +25°C are guaranteed by design and characterization. Typical values are at TA= +25°C.)
V
D_N
V
D_P
V
IHLVDS
V
ILLVDS
DV
DD3.3
DV
DD1.8
I
AVDD3.3
I
AVDD1.8
I
DVDD3.3
I
DVDD1.8
3.135
1.710
3.465
1.890
26.5
26.5 28.5
26.5
11.3
10.6
50.5
137
267
298
±0.025 %FS
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