MAXIM MAX5891 Technical data

General Description

The MAX5891 advanced 16-bit, 600Msps, digital-to­analog converter (DAC) meets the demanding perfor­mance requirements of signal synthesis applications
found in wireless base stations and other communica­tions applications. Operating from 3.3V and 1.8V sup­plies, the MAX5891 DAC supports update rates of
600Msps using high-speed LVDS inputs while consum­ing only 298mW of power and offers exceptional
dynamic performance such as 80dBc spurious-free
dynamic range (SFDR) at f

OUT

= 30MHz.

The MAX5891 utilizes a current-steering architecture that
supports a 2mA to 20mA full-scale output current range,
and produces -2dBm to -22dBm full-scale output signal
levels with a double-terminated 50Ω load. The MAX5891
features an integrated 1.2V bandgap reference and con­trol amplifier to ensure high-accuracy and low-noise per­formance. A separate reference input (REFIO) allows for
the use of an external reference source for optimum flexi­bility and improved gain accuracy.

The MAX5891 digital inputs accept LVDS voltage lev­els, and the flexible clock input can be driven differen­tially or single-ended, AC- or DC-coupled. The
MAX5891 is available in a 68-pin QFN package with an
exposed paddle (EP) and is specified for the extended
(-40°C to +85°C) temperature range.

Refer to the MAX5890 and MAX5889 data sheets for pin­compatible 14-bit and 12-bit versions of the MAX5891.

Applications

Base Stations: Single/Multicarrier UMTS,
CDMA, GSM

Communications: Fixed Broadband Wireless
Access, Point-to-Point Microwave

Direct Digital Synthesis (DDS)

Cable Modem Termination Systems (CMTS)

Automated Test Equipment (ATE)

Instrumentation

Features

♦ 600Msps Output Update Rate

♦ Low Noise Spectral Density: -163dBFS/Hz at

f

OUT

= 36MHz

♦ Excellent SFDR and IMD Performance

SFDR = 80dBc at f

OUT

= 30MHz (to Nyquist)

SFDR = 71dBc at f

OUT

= 130MHz (to Nyquist)

IMD = -95dBc at f

OUT

= 30MHz

IMD = -70dBc at f

OUT

= 130MHz

♦ ACLR = 73dB at f

OUT

= 122.88MHz

♦ 2mA to 20mA Full-Scale Output Current

♦ LVDS-Compatible Digital Inputs

♦ On-Chip 1.2V Bandgap Reference

♦ Low 298mW Power Dissipation at 600Msps

♦ Compact (10mm x 10mm) QFN-EP Package

♦ Evaluation Kit Available (MAX5891EVKIT)

MAX5891

16-Bit, 600Msps, High-Dynamic-Performance

DAC with LVDS Inputs

________________________________________________________________ Maxim Integrated Products 1

Ordering Information

19-3542; Rev 4; 2/07

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

PART

TEMP

RANGE

PIN­PACKAGE

PKG

CODE

M AX5891E GK-D

68 QFN -E P *

G6800- 4

M AX5891E GK+D

68 QFN -E P *

G6800- 4

MAX5891

1.2V

REFERENCE

REFIO

DACREF

FSADJ

CLK

INTERFACE

600MHz

16-BIT DAC

LATCH

LVDS

RECEIVER

D0–D15

LVDS DATA

INPUTS

POWER

DOWN

PD

CLKP

CLKN

OUTP

OUTN

Functional Diagram

PART

RESOLUTION

(BITS)

UPDATE RATE

(Msps)

LOGIC INPUT

MAX5889

12 600 LVDS

MAX5890

14 600 LVDS

MAX5891

16 600 LVDS

Selector Guide

Pin Configuration appears at end of data sheet.

*

EP = Exposed paddle.

+ = Lead-free package.
D = Dry pack.

- 40°C to + 85°C

- 40°C to + 85°C

MAX5891

16-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(AV

DD3.3

= DV

DD3.3

= AV

CLK

= 3.3V, AV

DD1.8

= DV

DD1.8

= 1.8V, external reference V

REFIO

= 1.2V, output load 50Ω double-terminated,

transformer-coupled output, I

OUT

= 20mA, TA= -40°C to +85°C, unless otherwise noted. Specifications at TA≥ +25°C are guaranteed

by production testing. Specifications at T

A

< +25°C are guaranteed by design and characterization. Typical values are at TA= +25°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

AV

DD1.8

, DV

DD1.8

to AGND, DGND, DACREF,

and CGND.......................................................-0.3V to +2.16V

AV

DD3.3

, DV

DD3.3

, AV

CLK

to AGND, DGND,

DACREF, and CGND.........................................-0.3V to +3.9V

REFIO, FSADJ to AGND, DACREF,

DGND, and CGND ..........................-0.3V to (AV

DD3.3

+ 0.3V)

OUTP, OUTN to AGND, DGND, DACREF,

and CGND .......................................-1.2V to (AV

DD3.3

+ 0.3V)

CLKP, CLKN to AGND, DGND, DACREF,

and CGND..........................................-0.3V to (AV

CLK

+ 0.3V)

PD to AGND, DGND, DACREF,

and CGND.......................................-0.3V to (DV

DD3.3

+ 0.3V)

Digital Data Inputs (D0N–D15N, D0P–D15P) to AGND,

DGND, DACREF, and CGND ..........-0.3V to (DV

DD1.8

+ 0.3V)

Continuous Power Dissipation (T

A

= +70°C) (Note 1)

68-Pin QFN-EP (derate 28.6mW/°C above +70°C)....3333mW

Thermal Resistance

θ

JA

(Note 1) ....................................24°C/W

Operating Temperature Range ..........................-40°C to +85°C

Junction Temperature .....................................................+150°C

Storage Temperature Range ............................-60°C to +150°C

Lead Temperature (soldering, 10s) ................................+300°C

PARAMETER

CONDITIONS

UNITS

STATIC PERFORMANCE

Resolution 16 Bits

Integral Nonlinearity INL Measured differentially

LSB

Differential Nonlinearity DNL Measured differentially

LSB

Offset Error OS

%FS

Full-Scale Gain Error GE

FS

External reference -4 ±1 +4

%FS

Internal reference

Gain-Drift Tempco

External reference

ppm/°C

Full-Scale Output Current I

OUT

220mA

Output Compliance Single-ended

V

Output Resistance R

OUT

1MΩ

Output Capacitance C

OUT

5pF

Output Leakage Current PD = high, power-down mode ±1µA

DYNAMIC PERFORMANCE

Maximum DAC Update Rate

Msps

Minimum DAC Update Rate 1

Msps

f

OUT

= 36MHz

Noise Spectral Density N

-12dBFS, 20MHz
offset from the
carrier

f

OUT

= 151MHz

dBFS/Hz

Note 1: Thermal resistance based on a multilayer board with 4x4 via array in exposed paddle area

SYMBOL

MIN TYP MAX

±3.8

±2.8

-0.02 ±0.001 +0.02

±130
±100

f

= 500MHz,

CLK

A

FULL-SCALE

A

FULL-SCALE

= -3.5dBm

= -6.4dBm

-1.0 +1.1

600

-163

-155

MAX5891

16-Bit, 600Msps, High-Dynamic-Performance

DAC with LVDS Inputs

_______________________________________________________________________________________ 3

PARAMETER

CONDITIONS

UNITS

f

OUT

= 16MHz 89

f

CLK

= 200MHz,

0dBFS (Note 2)

f

OUT

= 30MHz 85

f

OUT

= 16MHz 79

f

OUT

= 30MHz 81

76 81

80

71

Spurious-Free
Dynamic Range to
Nyquist

SFDR

f

CLK

= 500MHz,

0dBFS

56

dBc

f

CLK

= 500MHz

f

OUT1

= 29MHz,

f

OUT2

= 30MHz,

-6.5dBFS per tone

-95

Two-Tone IMD TTIMD

f

CLK

= 500MHz

f

OUT1

= 129MHz,

f

OUT2

= 130MHz,

-6.5dBFS per tone

-70

dBc

f

CLK

= 491.52MHz,

f

OUT

= 30.72MHz

82

WCDMA single
carrier

f

CLK

= 491.52MHz,

f

OUT

= 122.88MHz

73

f

CLK

= 491.52MHz,

f

OUT

= 30.72MHz

74

Adjacent Channel
Leakage Power Ratio

ACLR

WCDMA four
carriers

f

CLK

= 491.52MHz,

f

OUT

= 122.88MHz

67

dB

Output Bandwidth

(Note 4)

MHz

REFERENCE

Internal Reference Voltage Range

V

REFIO

1.2

V

Reference Input Voltage Range

Using external reference

1.2

V

Reference Input Resistance R

REFIO

10 kΩ

Reference Voltage Temperature
Drift

ppm/°C

ANALOG OUTPUT TIMING (Figure 3)

Output Fall Time t

FALL

90% to 10% (Note 5) 0.4 ns

Output Rise Time t

RISE

10% to 90% (Note 5) 0.4 ns

Output Propagation Delay t

PD

Reference to data latency (Note 5) 2.5 ns

Output Settling Time To 0.025% of the final value (Note 5) 11 ns

Glitch Impulse Measured differentially 1

pV•s

I

OUT

= 2mA 30

Output Noise N

OUT

I

OUT

= 20mA 30

pA/√Hz

ELECTRICAL CHARACTERISTICS (continued)

(AV

DD3.3

= DV

DD3.3

= AV

CLK

= 3.3V, AV

DD1.8

= DV

DD1.8

= 1.8V, external reference V

REFIO

= 1.2V, output load 50Ω double-terminated,

transformer-coupled output, I

OUT

= 20mA, TA= -40°C to +85°C, unless otherwise noted. Specifications at TA≥ +25°C are guaranteed

by production testing. Specifications at T

A

< +25°C are guaranteed by design and characterization. Typical values are at TA= +25°C.)

SYMBOL

f

= 200MHz,

CLK

MIN TYP MAX

-12dBFS (Note 2)

f

= 16MHz (Note 3)

OUT

f

= 30MHz (Note 2)

OUT

f

= 130MHz (Note 2)

OUT

f

= 200MHz (Note 2)

OUT

BW

-1dB

1000

V

REFIOCR

TCO

REF

1.14

0.10

±30

1.26

1.32

MAX5891

16-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs

4 _______________________________________________________________________________________

PARAMETER

CONDITIONS

UNITS

TIMING CHARACTERISTICS

Input Data Rate 600

Mwps

Data Latency 5.5

Clock

cycles

Data to Clock Setup Time t

SETUP

ns

Data to Clock Hold Time t

HOLD

2.6 ns

Clock Frequency f

CLK

CLKP, CLKN 600

MHz

Minimum Clock Pulse-Width High

t

CH

CLKP, CLKN 0.6 ns

Minimum Clock Pulse-Width Low

t

CL

CLKP, CLKN 0.6 ns

Turn-On Time t

SHDN

External reference, PD falling edge to
output settle within 1%

µs

CMOS LOGIC INPUT (PD)

Input Logic High V

IH

0.7 x
V

Input Logic Low V

IL

0.3 x
V

Input Current I

IN

-10

µA

Input Capacitance C

IN

3pF

LVDS INPUTS

Differential Input High

(Notes 6, 7, 8)

mV

Differential Input Low

(Notes 6, 7, 8)

mV

Internal Common-Mode Bias

V

E xter nal C om m on- M od e Tol er ance

(Notes 6, 8) 0.8

V

DD1.8

-

0.15

V

Differential Input Resistance

Ω

Common-Mode Input Resistance

3.2 kΩ

Input Capacitance

3pF

DIFFERENTIAL CLOCK INPUTS (CLKP, CLKN)

Clock Common-Mode Voltage CLKP and CLKN are internally biased

V

Minimum Differential Input
Voltage Swing

0.5

V

P-P

Minimum Common-Mode Voltage

1V

Maximum Common-Mode
Voltage

1.9 V

Input Resistance R

CLK

Single-ended 5 kΩ

Input Capacitance C

CLK

3pF

POWER SUPPLIES

3.3

Analog Supply Voltage Range

1.8

V

Clock Supply Voltage Range AV

CLK

3.3

V

ELECTRICAL CHARACTERISTICS (continued)

(AV

DD3.3

= DV

DD3.3

= AV

CLK

= 3.3V, AV

DD1.8

= DV

DD1.8

= 1.8V, external reference V

REFIO

= 1.2V, output load 50Ω double-terminated,

transformer-coupled output, I

OUT

= 20mA, TA= -40°C to +85°C, unless otherwise noted. Specifications at TA≥ +25°C are guaranteed

by production testing. Specifications at T

A

< +25°C are guaranteed by design and characterization. Typical values are at TA= +25°C.)

SYMBOL

MIN TYP MAX

Referenced to rising edge of clock (Note 6) -1.5

V

IHLVDS

V

ILLVDS

V

ICMLVDS

V

ECMLVDS

R

IDLVDS

R

ICMLVDS

C

INLVDS

AV

DD3.3

AV

DD1.8

Referenced to rising edge of clock (Note 6)

DV

DD3.3

+100 +1000

-1000 -100

1.125 1.375

AV

3.135

1.710

3.135

350

DV

DD3.3

±1.8 +10

110

/ 2

CLK

3.465

1.890

3.465

MAX5891

16-Bit, 600Msps, High-Dynamic-Performance

DAC with LVDS Inputs

_______________________________________________________________________________________ 5

Note 2: Parameter tested with input data pattern based on 16,384 data points. f

OUT

has been chosen so the corresponding input pattern

contains prime number of f

OUT

cycles and is a nonrepetitive sequence. f

OUT

has been rounded to the nearest MHz number in both

the Electrical Characteristics table and Typical Operating Characteristics.

Note 3: Parameter tested exactly at f

OUT

= 16.204833984375MHz and with a clock frequency of 500MHz at an output amplitude of 0dBFS.

Note 4: This parameter does not include update-rate-dependent effects of sin(x)/x filtering inherent in the MAX5891.
Note 5: Parameter measured single-ended with 50Ω double-terminated outputs.
Note 6: Not production tested. Guaranteed by design.
Note 7: Differential input voltage defined as V

D_P

- V

D_N

.

Note 8: Combination of logic-high/-low and common-mode voltages must not exceed absolute maximum rating for D_P/D_N inputs.
Note 9: Parameter defined as the change in midscale output caused by a ±5% variation in the nominal supply voltages.

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

3.3

Digital Supply Voltage Range

1.8

V

f

CLK

= 100MHz, f

OUT

= 16MHz

f

CLK

= 500MHz, f

OUT

= 16MHz

f

CLK

= 600MHz, f

OUT

= 16MHz

f

CLK

= 100MHz, f

OUT

= 16MHz

f

CLK

= 500MHz, f

OUT

= 16MHz 50 58

Analog Supply Current

f

CLK

= 600MHz, f

OUT

= 16MHz 61

mA

f

CLK

= 100MHz, f

OUT

= 16MHz 2.8

f

CLK

= 500MHz, f

OUT

= 16MHz 2.8 3.6

Clock Supply Current I

AVCLK

f

CLK

= 600MHz, f

OUT

= 16MHz 2.8

mA

f

CLK

= 100MHz, f

OUT

= 16MHz 0.2

f

CLK

= 500MHz, f

OUT

= 16MHz 0.2 0.5

f

CLK

= 600MHz, f

OUT

= 16MHz 0.2

f

CLK

= 100MHz, f

OUT

= 16MHz

f

CLK

= 500MHz, f

OUT

= 16MHz 44 50

Digital Supply Current

f

CLK

= 600MHz, f

OUT

= 16MHz

mA

f

CLK

= 100MHz, f

OUT

= 16MHz

f

CLK

= 500MHz, f

OUT

= 16MHz

301

f

CLK

= 600MHz, f

OUT

= 16MHz

mW

Total Power Dissipation P

DISS

Power-down, clock static low,
data input static

13 µW

Power-Supply Rejection Ratio PSRR (Note 9)

ELECTRICAL CHARACTERISTICS (continued)

(AV

DD3.3

= DV

DD3.3

= AV

CLK

= 3.3V, AV

DD1.8

= DV

DD1.8

= 1.8V, external reference V

REFIO

= 1.2V, output load 50Ω double-terminated,

transformer-coupled output, I

OUT

= 20mA, TA= -40°C to +85°C, unless otherwise noted. Specifications at TA≥ +25°C are guaranteed

by production testing. Specifications at T

A

< +25°C are guaranteed by design and characterization. Typical values are at TA= +25°C.)

V

D_N

V

D_P

V

IHLVDS

V

ILLVDS

DV

DD3.3

DV

DD1.8

I

AVDD3.3

I

AVDD1.8

I

DVDD3.3

I

DVDD1.8

3.135

1.710

3.465

1.890

26.5

26.5 28.5

26.5

11.3

10.6

50.5

137

267

298

±0.025 %FS

TWO-TONE INTERMODULATION DISTORTION

vs. OUTPUT FREQUENCY

(f

CLK

= 500MHz, 1MHz CARRIER SPACING)

MAX5891 toc06

OUTPUT FREQUENCY (MHz)

TTIMD (dBc)

1601208040

-110

-100

-90

-80

-70

-60

-50

-120
0 200

-12dBFS

-6.5dBFS

MAX5891

16-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs

6 _______________________________________________________________________________________

Typical Operating Characteristics

(AV

DD3.3

= DV

DD3.3

= AV

CLK

= 3.3V, AV

DD1.8

= DV

DD1.8

= 1.8V, external reference V

REFIO

= 1.2V, output load 50Ω double-terminated,

transformer-coupled output, I

OUT

= 20mA, TA= +25°C, unless otherwise noted.)

SPURIOUS-FREE DYNAMIC RANGE

vs. OUTPUT FREQUENCY (f

CLK

= 100MHz)

MAX5891 toc01

OUTPUT FREQUENCY (MHz)

SFDR (dBc)

30 352010 25155

10

20

30

40

50

60

70

80

90

100

0

040

-6dBFS

0dBFS

-12dBFS

SPURIOUS-FREE DYNAMIC RANGE

vs. OUTPUT FREQUENCY (f

CLK

= 200MHz)

MAX5891 toc02

OUTPUT FREQUENCY (MHz)

SFDR (dBc)

706040 5020 3010

10

20

30

40

50

60

70

80

90

100

0

080

-6dBFS
0dBFS

-12dBFS

SPURIOUS-FREE DYNAMIC RANGE

vs. OUTPUT FREQUENCY (f

CLK

= 500MHz)

MAX5891 toc03

OUTPUT FREQUENCY (MHz)

SFDR (dBc)

1601208040

10

20

30

40

50

60

70

80

90

100

0

0 200

-6dBFS

0dBFS

-12dBFS

SPURIOUS-FREE DYNAMIC RANGE

vs. OUTPUT FREQUENCY (f

CLK

= 600MHz)

MAX5891 toc04

OUTPUT FREQUENCY (MHz)

SFDR (dBc)

1601208040

10

20

30

40

50

60

70

80

90

100

0

0 200

-6dBFS

0dBFS

-12dBFS

SPURIOUS-FREE DYNAMIC RANGE

vs. OUTPUT FREQUENCY

(f

CLK

= 500MHz, I

OUT

= 20mA, 10mA, 5mA)

MAX5891 toc05

OUTPUT FREQUENCY (MHz)

SFDR (dBc)

1601208040

10

20

30

40

50

60

70

80

90

100

0

0 200

10mA

20mA

5mA

MAX5891

16-Bit, 600Msps, High-Dynamic-Performance

DAC with LVDS Inputs

_______________________________________________________________________________________ 7

SINGLE-CARRIER WCDMA ACLR

(f

CLK

= 491.52MHz)

OUTPUT POWER (dBm)

MAX5891 toc07

ACLR = 72.3dB
f

CENTER

= 122.88MHz

2.5MHz/div

-20

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

FOUR-CARRIER WCDMA ACLR

(f

CLK

= 491.52MHz)

MAX5891 toc08

4.06MHz/div

OUTPUT POWER (dBm)

ACLR = 67.3dB
f

CENTER

= 122.88MHz

-20

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

SPURIOUS-FREE DYNAMIC RANGE

vs. TEMPERATURE (f

CLK

= 500MHz)

MAX5891 toc09

TEMPERATURE (°C)

SFDR (dBc)

603510-15

55

65

60

75

70

85

80

90

50

-40 85

f

OUT

= 10MHz

f

OUT

= 100MHz

f

OUT

= 50MHz

INTEGRAL NONLINEARITY

MAX5891 toc10

DIGITAL INPUT CODE

INL (LSB)

57344

49152

8192

16384

24576

32768

40960

-3

-2

-1

0

1

2

3

4

-4
0 65536

DIFFERENTIAL NONLINEARITY

MAX5891 toc11

DIGITAL INPUT CODE

DNL (LSB)

57344

49152

8192

16384

24576

32768

40960

-3

-2

-1

0

1

2

-4
0 65536

TOTAL POWER DISSIPATION vs. CLOCK FREQUENCY

(f

OUT

= 16MHz, A

OUT

= 0dBFS)

MAX5891 toc12

CLOCK FREQUENCY (MHz)

POWER DISSIPATION (mW)

500400300200100

50

100

150

200

250

300

350

0

0 600

Typical Operating Characteristics (continued)

(AV

DD3.3

= DV

DD3.3

= AV

CLK

= 3.3V, AV

DD1.8

= DV

DD1.8

= 1.8V, external reference V

REFIO

= 1.2V, output load 50Ω double-terminated,

transformer-coupled output, I

OUT

= 20mA, TA= +25°C, unless otherwise noted.)

MAX5891

16-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs

8 _______________________________________________________________________________________

PIN NAME FUNCTION

1, 3, 5, 7, 9,
46, 48, 50, 52,
54, 56, 58, 60,

63, 65, 67

D4N, D3N, D2N,

D1N, D0N, D15N,

D14N, D13N, D12N,

D11N, D10N, D9N,

Differential Negative LVDS Inputs. Data bits D0–D15 (offset binary format).

2, 4, 6, 8, 45,
47, 49, 51, 53,
55, 57, 59, 62,

64, 66, 68

D3P, D2P, D1P, D0P,

D15P, D14P, D13P,
D12P, D11P, D10P,

D9P, D8P, D7P, D6P,

D5P, D4P

Differential Positive LVDS Inputs. Data bits D0–D15 (offset binary format).

10 DGND Digital Ground. Ground return for DV

DD3.3

and DV

DD1.8

.

15, 20, 23, 24,

27, 30, 33

AGND Analog Ground. Ground return for AV

DD3.3

and AV

DD1.8

.

11 DV

DD3.3

Digital Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a

0.1µF capacitor to DGND.

12 PD

Power-Down Input. Set PD high to force the DAC into power-down mode. Set PD low for
normal operation. PD has an internal 2µA pulldown.

13, 42, 43, 44

N.C. No Connection. Leave floating or connect to AGND.

14, 21, 22, 25,

26, 31, 32

AV

DD3.3

Analog Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a

0.1µF capacitor to AGND.

16 REFIO

Reference I/O. Output of the internal 1.2V precision bandgap reference. Bypass with a

0.1µF capacitor to AGND. REFIO can be driven with an external reference source.

17 FSADJ

Full-Scale Current Adjustment. Connect an external resistor R

SET

between FSADJ and
DACREF to set the output full-scale current. The output full-scale current is equal to 32 x
V

REF

/ R

SET

.

18 DACREF

Current-Set Resistor Return Path. Internally connected to ground, but do not use as
ground connection.

19, 34, 35 AV

DD1.8

Analog Supply Voltage. Accepts a 1.71V to 1.89V supply voltage range. Bypass with a

0.1µF capacitor to AGND.

28 OUTN Complementary DAC Output. Negative terminal for current output.

29 OUTP DAC Output. Positive terminal for current output.

36, 41 AV

CLK

Clock Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a

0.1µF capacitor to CGND.

37, 40 CGND Clock Supply Ground

38 CLKN

Complementary Converter Clock Input. Negative input terminal for differential converter
clock.

39 CLKP Converter Clock Input. Positive input terminal for differential converter clock.

61 DV

DD1.8

Digital Supply Voltage. Accepts a 1.71V to 1.89V supply voltage range. Bypass with a

0.1µF capacitor to DGND.

—EP

Exposed Pad. Must be connected to common point for AGND, DGND, and CGND through
a low-impedance path. EP is internally connected to AGND, DGND, and CGND.

Pin Description

D8N, D7N, D6N, D5N

Detailed Description

Architecture

The MAX5891 high-performance, 16-bit, current-steer­ing DAC (see the Functional Diagram) operates with
DAC update rates up to 600Msps. The current-steering
array generates differential full-scale currents in the
2mA to 20mA range. An internal current-switching net­work, in combination with external 50Ω termination
resistors, converts the differential output currents into a
differential output voltage with a 0.1V to 1V peak-to­peak output voltage range. The analog outputs have a

-1.0V to +1.1V voltage compliance. For applications
requiring high dynamic performance, use the differen­tial output configuration and limit the output voltage
swing to ±0.5V at each output. An integrated 1.2V
bandgap reference, control amplifier, and user-selec­table external resistor determine the data converter’s
full-scale output range.

Reference Architecture and Operation

The MAX5891 operates with the internal 1.2V bandgap
reference or an external reference voltage source.
REFIO serves as the input for an external, low-imped­ance reference source or as a reference output when
the DAC operates in internal reference mode. For sta­ble operation with the internal reference, bypass REFIO
to AGND with a 0.1µF capacitor. The REFIO output
resistance is 10kΩ. Buffer REFIO with a high-input­impedance amplifier when using it as a reference
source for external circuitry.

The MAX5891’s reference circuit (Figure 1) employs a
control amplifier to regulate the full-scale current,
I

OUTFS

, for the differential current outputs of the DAC.

Calculate the output current as follows:

where I

OUTFS

is the full-scale output current of the

DAC. R

SET

(located between FSADJ and DACREF)
determines the amplifier’s full-scale output current for
the DAC. See Table 1 for a matrix of different I

OUTFS

and R

SET

selections.

Analog Outputs (OUTP, OUTN)

The complementary current outputs (OUTP, OUTN) can
be connected in a single-ended or differential configu­ration. A load resistor converts these two output cur­rents into complementary single-ended output
voltages. A transformer or a differential amplifier con­verts the differential voltage existing between OUTP
and OUTN to a single-ended voltage. When not using a
transformer, terminate each output with a 25Ω resistor
to ground and a 50Ω resistor between the outputs.

To generate a single-ended output, select OUTP as the
output and connect OUTN to AGND. Figure 2 shows a
simplified diagram of the internal output structure of the
MAX5891.

I

V

R

OUTFS

REFIO

SET

=× ×−

⎛

⎝

⎜

⎞

⎠

⎟

32 1

1

2

16

MAX5891

16-Bit, 600Msps, High-Dynamic-Performance

DAC with LVDS Inputs

_______________________________________________________________________________________ 9

R

SET

(Ω)

FULL-SCALE CURRENT

I

OUTFS

(mA)

1% EIA STD

2 19.2k 19.1k

5 7.68k 7.5k

10 3.84k 3.83k

15 2.56k 2.55k

20 1.92k 1.91k

Table 1. I

OUTFS

and R

SET

Selection Matrix
Based on a Typical 1.200V Reference
Voltage

OUTP

OUTN

1.2V

REFERENCE

CURRENT-SOURCE

ARRAY DAC

REFIO

FSADJ

R

SET

I

REF

10kΩ

DACREF

0.1μF

I

REF

= V

REFIO

/ R

SET

Figure 1. Reference Architecture, Internal Reference
Configuration

CALCULATED

MAX5891

Clock Inputs (CLKP, CLKN)

To achieve the best possible jitter performance, the
MAX5891 features flexible differential clock inputs
(CLKP, CLKN) that operate from a separate clock
power supply (AV

CLK

). Drive the differential clock
inputs from a single-ended or a differential clock
source. For highest dynamic performance, differential
clock source is required. For single-ended operation,
drive CLKP and bypass CLKN to CGND.

CLKP and CLKN are internally biased at AV

CLK

/ 2,
allowing the AC-coupling of clock sources directly to
the device without external resistors to define the DC
level. The input resistance from CLKP and CLKN to
ground is approximately 5kΩ.

Data-Timing Relationship

Figure 3 shows the timing relationship between digital
LVDS data, clock, and output signals. The MAX5891
features a 2.6ns hold, a -1.5ns setup, and a 2.5ns prop­agation delay time. There is a 5.5 clock-cycle latency
between data write operation and the corresponding
analog output transition.

LVDS Data Inputs

The MAX5891 has 16 pairs of LVDS data inputs (offset
binary format) and can accept data rates up to
600Mwps. Each differential input pair is terminated with
an internal 110Ω resistor. The common-mode input
resistance is 3.2kΩ.

Power-Down Operation (PD)

The MAX5891 features a power-down mode that
reduces the DAC’s power consumption. Set PD high to
power down the MAX5891. Set PD low or leave uncon­nected for normal operation.

When powered down, the MAX5891 overall power con­sumption is reduced to less than 13µW. The MAX5891
requires 350µs to wake up from power-down and enter
a fully operational state if the external reference is
used. If the internal reference is used, the power-down
recovery time is 10ms. The PD internal pulldown circuit
sets the MAX5891 in normal mode when PD is left
unconnected.

16-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs

10 ______________________________________________________________________________________

I

OUT

I

OUT

OUTN OUTP

CURRENT
SOURCES

CURRENT

SWITCHES

AV

DD3.3

Figure 2. Simplified Analog Output Structure

D0–D16

t

SETUP

t

HOLD

D

N

CLKP

CLKN

D

N + 2

D

N + 4

D

N + 6

IOUTP

IOUTN

t

PD

D

N + 1

D

N + 3

D

N + 5

D

N + 7

OUT

N - 2

OUT

N - 3

OUT

N - 4

OUT

N - 5

OUT

N - 6

OUT

N - 7

OUT

N-1

OUT

N

Figure 3. Timing Relationship Between Clock, Input Data, and Analog Output

Applications Information

Clock Interface

To achieve the best possible jitter performance, the
MAX5891 features flexible differential clock inputs
(CLKP, CLKN) that operate from a separate clock
power supply (AV

CLK

). Use a low-jitter clock to reduce
the DAC’s phase noise and wideband noise. To
achieve the best DAC dynamic performance, the
CLKP/CLKN input source must be designed carefully.
The differential clock (CLKN and CLKP) input can be
driven from a single-ended or a differential clock
source. Use differential clock drive to achieve the best
dynamic performance from the DAC. For single-ended
operation, drive CLKP with a low noise source and
bypass CLKN to CGND with a 0.1µF capacitor.

Figure 4 shows a convenient and quick way of applying
a differential signal created from a single-ended source
using a wideband transformer. Alternatively, drive
CLKP/CLKN from a CMOS-compatible clock source.
Use sinewave or AC-coupled differential ECL/PECL
drive for best dynamic performance.

Differential Output Coupling Using a

Wideband RF Transformer

Use a pair of transformers (Figure 5) or a differential
amplifier configuration to convert the differential voltage
existing between OUTP and OUTN to a single-ended
voltage. Optimize the dynamic performance by using a
differential transformer-coupled output and limit the out­put power to < 0dBm full scale. To achieve the best
dynamic performance, use the differential transformer
configuration. Terminate the DAC as shown in Figure 5,
and use 50Ω termination at the transformer single­ended output. This will provide double 50Ω termination
for the DAC output network. With the double-terminated
output and 20mA full-scale current, the DAC will pro­duce a full-scale signal level of approximately -2dBm.
Pay close attention to the transformer core saturation
characteristics when selecting a transformer for the
MAX5891. Transformer core saturation can introduce
strong 2nd-order harmonic distortion especially at low
output frequencies and high signal amplitudes. For best
results, connect the center tap of the transformer to
ground. When not using a transformer, terminate each
DAC output to ground with a 25Ω resistor. Additionally,
place a 50Ω resistor between the outputs (Figure 6).

For a single-ended unipolar output, select OUTP as the
output and connect OUTN to AGND. Operating the
MAX5891 single-ended is not recommended because
it degrades the dynamic performance.

The distortion performance of the DAC depends on the
load impedance. The MAX5891 is optimized for 50Ω
differential double termination. Using higher termination
impedance degrades distortion performance and
increases output noise voltage.

MAX5891

16-Bit, 600Msps, High-Dynamic-Performance

DAC with LVDS Inputs

______________________________________________________________________________________ 11

WIDEBAND RF TRANSFORMER

PERFORMS SINGLE-ENDED-TO-

DIFFERENTIAL CONVERSION

SINGLE-ENDED

CLOCK SOURCE

AGND

1:1

25Ω

25Ω

CLKP

CLKN

TO DAC

0.1μF

0.1μF

Figure 4. Differential Clock-Signal Generation

MAX5891

OUTP

OUTN

WIDEBAND RF TRANSFORMER T2 PERFORMS THE
DIFFERENTIAL-TO-SINGLE-ENDED CONVERSION

T1, 1:1

T2, 1:1

AGND

50Ω

100Ω

50Ω

V

OUT

, SINGLE-ENDED

D0–D15

LVDS

DATA INPUTS

Figure 5. Differential-to-Single-Ended Conversion Using a Wideband RF Transformer

MAX5891

Grounding, Bypassing, and Power-Supply

Considerations

Grounding and power-supply decoupling strongly influ­ence the MAX5891 performance. Unwanted digital
crosstalk coupling through the input, reference, power
supply, and ground connections affects dynamic per­formance. High-speed, high-frequency applications
require closely followed proper grounding and power­supply decoupling. These techniques reduce EMI and
internal crosstalk that can significantly affect the
MAX5891 dynamic performance.

Use a multilayer printed circuit board (PCB) with sepa­rate ground and power-supply planes. Run high-speed
signals on lines directly above the ground plane. Keep
digital signals as far away from sensitive analog inputs
and outputs, reference input sense lines, common­mode inputs, and clock inputs as practical. Use a sym­metric design of clock input and the analog output lines
to minimize 2nd-order harmonic distortion components,
thus optimizing the DAC’s dynamic performance. Keep
digital signal paths short and run lengths matched to
avoid propagation delay and data skew mismatches.

The MAX5891 requires five separate power-supply
inputs for analog (AV

DD1.8

and AV

DD3.3

), digital

(DV

DD1.8

and DV

DD3.3

), and clock (AV

CLK

) circuitry.

Decouple each AV

DD3.3

, AV

DD1.8

, AV

CLK

, DV

DD3.3

, and

DV

DD1.8

input with a separate 0.1µF capacitor as close
to the device as possible with the shortest possible con­nection to the respective ground plane (Figure 7).
Connect all of the 3.3V supplies together at one point
with ferrite beads to minimize supply noise coupling.
Decouple all five power-supply voltages at the point they
enter the PCB with tantalum or electrolytic capacitors.
Ferrite beads with additional decoupling capacitors
forming a pi network can also improve performance.
Similarly, connect all 1.8V supplies together at one point
with ferrite beads.

The analog and digital power-supply inputs AV

DD3.3

,

AV

CLK

, and DV

DD3.3

allow a 3.135V to 3.465V supply
voltage range. The analog and digital power-supply
inputs AV

DD1.8

and DV

DD1.8

allow a 1.71V to 1.89V

supply voltage range.

The MAX5891 is packaged in a 68-pin QFN-EP pack­age with exposed paddle, providing optimized DAC AC
performance. The exposed pad must be soldered to
the ground plane of the PCB. Thermal efficiency is not
the key factor, since the MAX5891 features low- power
operation. The exposed pad ensures a solid ground
connection between the DAC and the PCB’s ground
layer.

The data converter die attaches to an EP lead frame
with the back of this frame exposed at the package
bottom surface, facing the PCB side of the package.
This allows for a solid attachment of the package to the
PCB with standard infrared (IR) reflow soldering tech­niques. A specially created land pattern on the PCB,
matching the size of the EP (6mm x 6mm), ensures the
proper attachment and grounding of the DAC. Place
vias into the land area and implement large ground

16-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs

12 ______________________________________________________________________________________

MAX5891

OUTP

OUTN

AGND

25Ω

50Ω

25Ω

OUTP

OUTN

D0–D15

LVDS

DATA INPUTS

Figure 6. Differential Output Configuration

MAX5891

OUTPAV

DD3.3

AV

DD1.8

DV

DD3.3

DV

DD1.8

AV

CLK

OUTN

0.1μF

3.3V VOLTAGE SUPPLY

0.1μF

0.1μF 0.1μF

1.8V VOLTAGE SUPPLY

0.1μF

BYPASSING—DAC LEVEL

*FERRITE BEADS

D0–D15

LVDS

DATA INPUTS

*

**

**

Figure 7. Recommended Power-Supply Decoupling and
Bypassing Circuitry

planes in the PCB design to ensure the highest dynam­ic performance of the DAC. Connect the MAX5891
exposed paddle to the common connection point of
DGND, AGND, and CGND. Vias connect the top land
pattern to internal or external copper planes. Use as
many vias as possible to the ground plane to minimize
inductance. The vias should have a diameter greater
than 0.3mm.

Static Performance Parameter

Definitions

Integral Nonlinearity (INL)

Integral nonlinearity is the deviation of the values on an
actual transfer function from a line drawn between the
end points of the transfer function, once offset and gain
errors have been nullified. For a DAC, the deviations
are measured at every individual step.

Differential Nonlinearity (DNL)

Differential nonlinearity is the difference between an
actual step height and the ideal value of 1 LSB.

Offset Error

The offset error is the difference between the ideal and
the actual offset current. For a DAC, the offset point is
the average value at the output for the two midscale
digital input codes with respect to the full scale of the
DAC. This error affects all codes by the same amount.

Gain Error

A gain error is the difference between the ideal and the
actual full-scale output voltage on the transfer curve,
after nullifying the offset error. This error alters the slope
of the transfer function and corresponds to the same
percentage error in each step.

Settling Time

The settling time is the amount of time required from the
start of a transition until the DAC output settles its new
output value to within the converter’s specified accuracy.

Glitch Impulse

A glitch is generated when a DAC switches between
two codes. The largest glitch is usually generated
around the midscale transition, when the input pattern
transitions from 011...111 to 100...000. The glitch
impulse is found by integrating the voltage of the glitch
at the midscale transition over time. The glitch impluse
is usually specified in pV

•s.

Dynamic Performance Parameter

Definitions

Signal-to-Noise Ratio (SNR)

For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of the
full-scale analog output (RMS value) to the RMS quanti­zation error (residual error). The ideal, theoretical maxi­mum can be derived from the DAC’s resolution (N bits):

SNRdB = 6.02dB x N + 1.76dB

However, noise sources such as thermal noise, refer­ence noise, clock jitter, etc., affect the ideal reading;
therefore, SNR is computed by taking the ratio of the
RMS signal to the RMS noise, which includes all spec­tral components minus the fundamental, the first four
harmonics, and the DC offset.

Noise Spectral Density

The DAC output noise floor is the sum of the quantiza­tion noise and the output amplifier noise (thermal and
shot noise). Noise spectral density is the noise power in
1Hz bandwidth, specified in dBFS/Hz.

Spurious-Free Dynamic Range (SFDR)

SFDR is the ratio of RMS amplitude of the carrier
frequency (maximum signal components) to the RMS
value of their next-largest distortion component. SFDR is
usually measured in dBc and with respect to the carrier
frequency amplitude or in dBFS with respect to the
DAC’s full-scale range. Depending on its test condition,
SFDR is observed within a predefined window or to
Nyquist.

Two-Tone Intermodulation Distortion (IMD)

The two-tone IMD is the ratio expressed in dBc (or
dBFS) of the worst 3rd-order IMD differential product to
either output tone. The two-tone IMD performance of
the MAX5891 is tested with the two individual output
tone levels set to at least -6.5dBFS.

Adjacent Channel Leakage Power Ratio (ACLR)

Commonly used in combination with wideband code­division multiple-access (WCDMA), ACLR reflects the
leakage power ratio in dB between the measured
power within a channel relative to its adjacent channel.
ACLR provides a quantifiable method of determining
out-of-band spectral energy and its influence on an
adjacent channel when a bandwidth-limited RF signal
passes through a nonlinear device.

MAX5891

16-Bit, 600Msps, High-Dynamic-Performance

DAC with LVDS Inputs

______________________________________________________________________________________ 13

MAX5891

16-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs

14 ______________________________________________________________________________________

Pin Configuration

D4N 1

D3P

2

D3N

3

D2P

4

D2N

5

D1P

6

D1N

7

D0P

8

D0N

9

DGND

10

DV

DD3.3

11

PD

12

N.C.

13

AV

DD3.3

14

AGND

15

REFIO

EXPOSED PADDLE

16

FSADJ

17

D12P

51

D13N

50

D13P

49

D14N

48

D14P

47

D15N

46

D15P

45

N.C.

44

N.C.

43

N.C.

42

AV

CLK

41

CGND

40

CLKP

39

CLKN

38

CGND

37

AV

CLK

36

AV

DD1.8

35

DACREF

18

AV

DD1.8

19

AGND

20

AV

DD3.3

21

AV

DD3.3

22

AGND23AGND

24

AV

DD3.3

25

AV

DD3.3

26

AGND

27

OUTN

28

OUTP

29

AGND

30

AV

DD3.3

31

AV

DD3.3

32

AGND

33

AV

DD1.8

34

D4P68D5N67D5P66D6N65D6P64D7N63D7P62DV

DD1.8

61

D8N60D8P59D9N58D9P57D10N56D10P55D11N54D11P53D12N

52

MAX5891

QFN-EP

16-Bit, 600Msps, High-Dynamic-Performance

DAC with LVDS Inputs

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,

www.maxim-ic.com/packages

go to

.)

68L QFN.EPS

MAX5891

     



______________________________________________________________________________________ 15







16-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs

Package Information (continued)

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,

www.maxim-ic.com/packages

go to

.)

MAX5891

     









Revision History

Pages changed at Rev 4: 2–5, 12, 13

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implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

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