MAXIM MAX5889 Technical data

General Description

The MAX5889 advanced 12-bit, 600Msps, digital-to­analog converter (DAC) meets the demanding perfor­mance requirements of signal synthesis applications
found in wireless base stations and other communica­tions applications. Operating from 3.3V and 1.8V sup­plies, the MAX5889 DAC supports update rates of
600Msps using high-speed LVDS inputs while consum­ing only 292mW of power and offers exceptional
dynamic performance such as 79dBc spurious-free
dynamic range (SFDR) at f

OUT

= 30MHz.

The MAX5889 utilizes a current-steering architecture that
supports a 2mA to 20mA full-scale output current range,
and produces -2dBm to -22dBm full-scale output signal
levels with a double-terminated 50Ω load. The MAX5889
features an integrated 1.2V bandgap reference and con­trol amplifier to ensure high-accuracy and low-noise per­formance. A separate reference input (REFIO) allows for
the use of an external reference source for optimum flexi­bility and improved gain accuracy.

The MAX5889 digital inputs accept LVDS voltage lev­els, and the flexible clock input can be driven differen­tially or single-ended, AC- or DC-coupled. The
MAX5889 is available in a 68-pin QFN package with an
exposed paddle (EP) and is specified for the extended
(-40°C to +85°C) temperature range.

Refer to the MAX5891 and MAX5890 data sheets for pin­compatible 16-bit and 14-bit versions of the MAX5889.

Applications

Base Stations: Single-Carrier UMTS,
CDMA, GSM

Communications: Fixed Broadband Wireless
Access, Point-to-Point Microwave

Direct Digital Synthesis (DDS)

Cable Modem Termination Systems (CMTS)

Automated Test Equipment (ATE)

Instrumentation

Features

♦ 600Msps Output Update Rate

♦ Low-Noise Spectral Density: -157dBFS/Hz at

f

OUT

= 36MHz

♦ Excellent SFDR and IMD Performance

SFDR = 79dBc at f

OUT

= 30MHz (to Nyquist)

SFDR = 67dBc at f

OUT

= 130MHz (to Nyquist)

IMD = -95dBc at f

OUT

= 30MHz

IMD = -70dBc at f

OUT

= 130MHz

♦ ACLR = 72dB at f

OUT

= 122.88MHz

♦ 2mA to 20mA Full-Scale Output Current

♦ LVDS-Compatible Digital Inputs

♦ On-Chip 1.2V Bandgap Reference

♦ Low 292mW Power Dissipation at 600Msps

♦ Compact (10mm x 10mm) QFN-EP Package

♦ Evaluation Kit Available (MAX5891EVKIT)

MAX5889

12-Bit, 600Msps, High-Dynamic-Performance

DAC with LVDS Inputs

________________________________________________________________ Maxim Integrated Products 1

Ordering Information

19-3620; Rev 1; 3/07

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

PART

TEMP RANGE

PIN-

PKG

CODE

MAX5889EGK-D

G6800-4

MAX5889EGK+D

G6800-4

MAX5889

1.2V

REFERENCE

REFIO

DACREF

FSADJ

CLK

INTERFACE

600MHz

12-BIT DAC

LATCH

LVDS

RECEIVER

D0–D11

LVDS DATA

INPUTS

POWER

DOWN

PD

CLKP

CLKN

OUTP

OUTN

Functional Diagram

PART

RESOLUTION

(BITS)

UPDATE RATE

(Msps)

LOGIC INPUT

MAX5889

12 600 LVDS

MAX5890

14 600 LVDS

MAX5891

16 600 LVDS

Selector Guide

*EP = Exposed paddle.
D = Dry pack.
+Denotes lead-free package.

Pin Configuration appears at end of data sheet.

PACKAGE

-40°C to +85°C 68 QFN-EP*

-40°C to +85°C 68 QFN-EP*

MAX5889

12-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(AV

DD3.3

= DV

DD3.3

= AV

CLK

= 3.3V, AV

DD1.8

= DV

DD1.8

= 1.8V, external reference V

REFIO

= 1.2V, output load 50Ω double-terminat-

ed, transformer-coupled output, I

OUT

= 20mA, TA= -40°C to +85°C, unless otherwise noted. Specifications at TA≥ +25°C are guar-

anteed by production testing. Specifications at T

A

< +25°C are guaranteed by design and characterization. Typical values are at T

A

= +25°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

AV

DD1.8

, DV

DD1.8

to AGND, DGND, DACREF,

and CGND.......................................................-0.3V to +2.16V

AV

DD3.3

, DV

DD3.3

, AV

CLK

to AGND, DGND,

DACREF, and CGND.........................................-0.3V to +3.9V

REFIO, FSADJ to AGND, DACREF,

DGND, and CGND ..........................-0.3V to (AV

DD3.3

+ 0.3V)

OUTP, OUTN to AGND, DGND, DACREF,

and CGND .......................................-1.2V to (AV

DD3.3

+ 0.3V)

CLKP, CLKN to AGND, DGND, DACREF,

and CGND..........................................-0.3V to (AV

CLK

+ 0.3V)

PD to AGND, DGND, DACREF,

and CGND.......................................-0.3V to (DV

DD3.3

+ 0.3V)

Digital Data Inputs (D0N–D11N, D0P–D11P) to AGND,

DGND, DACREF, and CGND ..........-0.3V to (DV

DD1.8

+ 0.3V)

Continuous Power Dissipation (T

A

= +70°C) (Note 1)

68-Pin QFN-EP (derate 28.6mW/°C above +70°C)....3333mW

Thermal Resistance

θ

JA

(Note 1) ....................................24°C/W

Operating Temperature Range ..........................-40°C to +85°C

Junction Temperature .....................................................+150°C

Storage Temperature Range ............................-60°C to +150°C

Lead Temperature (soldering, 10s) ................................+300°C

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

STATIC PERFORMANCE

Resolution 12 Bits

Integral Nonlinearity INL Measured differentially

LSB

Differential Nonlinearity DNL Measured differentially

LSB

Offset Error OS

%FS

Full-Scale Gain Error GE

FS

External reference -4 ±1+4

%FS

Internal reference

Gain-Drift Tempco

External reference

ppm/°C

Full-Scale Output Current I

OUT

220mA

Output Compliance Single-ended

V

Output Resistance R

OUT

1MΩ

Output Capacitance C

OUT

5pF

Output Leakage Current PD = high, power-down mode ±1µA

DYNAMIC PERFORMANCE

Maximum DAC Update Rate

Msps

Minimum DAC Update Rate 1

Msps

f

OUT

= 36MHz,

Noise Spectral Density N

-12dBFS, 20MHz
offset from the
carrier

f

OUT

= 151MHz,

dBFS/Hz

Note 1: Thermal resistance based on a multilayer board with 4 x 4 via array in exposed paddle area.

±0.25
±0.15

-0.02 0.001 +0.02

±130
±100

f

= 500MHz,

CLK

A

FULL-SCALE

A

FULL-SCALE

= -3.5dBm

= -6.4dBm

-1.0 +1.1

600

-157

-152

MAX5889

12-Bit, 600Msps, High-Dynamic-Performance

DAC with LVDS Inputs

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(AV

DD3.3

= DV

DD3.3

= AV

CLK

= 3.3V, AV

DD1.8

= DV

DD1.8

= 1.8V, external reference V

REFIO

= 1.2V, output load 50Ω double-terminat-

ed, transformer-coupled output, I

OUT

= 20mA, TA= -40°C to +85°C, unless otherwise noted. Specifications at TA≥ +25°C are guar-

anteed by production testing. Specifications at T

A

< +25°C are guaranteed by design and characterization. Typical values are at T

A

= +25°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

f

OUT

= 16MHz 88

f

CLK

= 200MHz,

0dBFS

f

OUT

= 30MHz 85

f

OUT

= 16MHz 78

f

CLK

= 200MHz,

-12dBFS

f

OUT

= 30MHz 77

f

OUT

= 16MHz 76 81

f

OUT

= 30MHz 80

f

OUT

= 130MHz 71

Spurious-Free
Dynamic Range to
Nyquist

SFDR

f

CLK

= 500MHz,

0dBFS

f

OUT

= 200MHz 54

dBc

f

CLK

= 500MHz

f

OUT1

= 29MHz,

f

OUT2

= 30MHz,

-6.5dBFS per tone

-95

Two-Tone IMD TTIMD

f

CLK

= 500MHz

f

OUT1

= 129MHz,

f

OUT2

= 130MHz,

-6.5dBFS per tone

-70

dBc

f

CLK

= 491.52MHz,

f

OUT

= 30.72MHz

80

WCDMA single
carrier

f

CLK

= 491.52MHz,

72

f

CLK

= 491.52MHz,

f

OUT

= 30.72MHz

72

Adjacent Channel
Leakage Power Ratio

ACLR

f

CLK

= 491.52MHz,

67

dB

Output Bandwidth

(Note 2)

REFERENCE

Internal Reference Voltage Range

V

REFIO

1.2

V

Reference Input Voltage Range

Using external reference

1.2

V

Reference Input Resistance R

REFIO

10 kΩ

Reference Voltage Temperature
Drift

ANALOG OUTPUT TIMING (Figure 3)

Output Fall Time t

FALL

90% to 10% (Note 3) 0.4 ns

Output Rise Time t

RISE

10% to 90% (Note 3) 0.4 ns

Output Propagation Delay t

PD

Reference to data latency (Note 3) 2.5 ns

Output Settling Time To 0.025% of the final value (Note 3) 11 ns

BW

-1dB

V

REFIOCR

TCO

REF

WCDMA four carriers

f

= 122.88MHz

OUT

f

= 122.88MHz

OUT

1.14

0.10

1000 MHz

1.26

1.32

±30 ppm/°C

MAX5889

12-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(AV

DD3.3

= DV

DD3.3

= AV

CLK

= 3.3V, AV

DD1.8

= DV

DD1.8

= 1.8V, external reference V

REFIO

= 1.2V, output load 50Ω double-terminat-

ed, transformer-coupled output, I

OUT

= 20mA, TA= -40°C to +85°C, unless otherwise noted. Specifications at TA≥ +25°C are guar-

anteed by production testing. Specifications at T

A

< +25°C are guaranteed by design and characterization. Typical values are at T

A

= +25°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Glitch Impulse Measured differentially 1

I

OUT

= 2mA 30

Output Noise N

OUT

I

OUT

= 20mA 30

TIMING CHARACTERISTICS

Input Data Rate 600

Data Latency 5.5

Clock

Data to Clock Setup Time t

SETUP

ns

Data to Clock Hold Time t

HOLD

2.6 ns

Clock Frequency f

CLK

CLKP, CLKN 600

Minimum Clock Pulse-Width High

t

CH

CLKP, CLKN 0.6 ns

Minimum Clock Pulse-Width Low

t

CL

CLKP, CLKN 0.6 ns

Turn-On Time t

SHDN

External reference, PD falling edge to
output settle within 1%

µs

CMOS LOGIC INPUT (PD)

Input Logic High V

IH

0.7 x
V

Input Logic Low V

IL

0.3 x
V

Input Current I

IN

-10

µA

Input Capacitance C

IN

3pF

LVDS INPUTS

Differential Input High

(Notes 6, 7, 8)

mV

Differential Input Low

(Notes 6, 7, 8)

mV

Internal Common-Mode Bias

V

Differential Input Resistance

Ω

Common-Mode Input Resistance

3.2 kΩ

Input Capacitance

3pF

DIFFERENTIAL CLOCK INPUTS (CLKP, CLKN)

Clock Common-Mode Voltage CLKP and CLKN are internally biased

V

Minimum Differential Input
Voltage Swing

0.5

Minimum Common-Mode Voltage

1V

Maximum Common-Mode
Voltage

1.9 V

Referenced to rising edge of clock (Note 4) -1.5

V

IHLVDS

V

ILLVDS

V

ICMLVDS

R

IDLVDS

R

ICMLVDS

C

INLVDS

Referenced to rising edge of clock (Note 4)

DV

DD3.3

+100 +1000

-1000 -100

1.125 1.375

AV

350

DV

DD3.3

±1.8 +10

110

/ 2

CLK

pV•s

pA/√Hz

MWps

cycles

MHz

V

P-P

MAX5889

12-Bit, 600Msps, High-Dynamic-Performance

DAC with LVDS Inputs

_______________________________________________________________________________________ 5

Note 2: This parameter does not include update-rate-dependent effects of sin(x)/x filtering inherent in the MAX5889.
Note 3: Parameter measured single-ended with 50Ω double-terminated outputs.
Note 4: Not production tested. Guaranteed by design.
Note 5: Parameter defined as the change in midscale output caused by a ±5% variation in the nominal supply voltages.
Note 6: Not production tested. Guaranteed by design.
Note 7: Differential input voltage defined as V

D_P

- V

D_N

.

Note 8: Combination of logic-high/-low and common-mode voltages must not exceed absolute maximum rating for D_P/D_N inputs.

ELECTRICAL CHARACTERISTICS (continued)

(AV

DD3.3

= DV

DD3.3

= AV

CLK

= 3.3V, AV

DD1.8

= DV

DD1.8

= 1.8V, external reference V

REFIO

= 1.2V, output load 50Ω double-terminat-

ed, transformer-coupled output, I

OUT

= 20mA, TA= -40°C to +85°C, unless otherwise noted. Specifications at TA≥ +25°C are guar-

anteed by production testing. Specifications at T

A

< +25°C are guaranteed by design and characterization. Typical values are at T

A

= +25°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Input Resistance R

CLK

Single-ended 5 kΩ

Input Capacitance C

CLK

3pF

POWER SUPPLIES

3.3

Analog Supply Voltage Range

1.8

V

Clock Supply Voltage Range AV

CLK

3.3

V

3.3

Digital Supply Voltage Range

1.8

V

f

CLK

= 100MHz, f

OUT

= 16MHz

f

CLK

= 500MHz, f

OUT

= 16MHz

f

CLK

= 600MHz, f

OUT

= 16MHz

f

CLK

= 100MHz, f

OUT

= 16MHz

f

CLK

= 500MHz, f

OUT

= 16MHz 50 58

Analog Supply Current

f

CLK

= 600MHz, f

OUT

= 16MHz 60

mA

f

CLK

= 100MHz, f

OUT

= 16MHz 2.8

f

CLK

= 500MHz, f

OUT

= 16MHz 2.8 3.6Clock Supply Current I

AVCLK

f

CLK

= 600MHz, f

OUT

= 16MHz 2.8

mA

f

CLK

= 100MHz, f

OUT

= 16MHz 0.2

f

CLK

= 500MHz, f

OUT

= 16MHz 0.2 0.5

f

CLK

= 600MHz, f

OUT

= 16MHz 0.2

f

CLK

= 100MHz, f

OUT

= 16MHz

f

CLK

= 500MHz, f

OUT

= 16MHz 42 48

Digital Supply Current

f

CLK

= 600MHz, f

OUT

= 16MHz 48

mA

f

CLK

= 100MHz, f

OUT

= 16MHz

f

CLK

= 500MHz, f

OUT

= 16MHz

297

f

CLK

= 600MHz, f

OUT

= 16MHz

mW

Total Power Dissipation P

DISS

Power-down, clock static low,
data input static

13 µW

Power-Supply Rejection Ratio PSRR (Note 5)

%FS

V

D_N

V

D_P

AV

DD3.3

AV

DD1.8

DV

DD3.3

DV

DD1.8

AVDD3.3

I

AVDD1.8

I

DVDD3.3

I

DVDD1.8

V

IHLVDS

3.135

1.710

3.135

3.135

1.710

26.5

26.5 28.5I

26.5

11.3

V

ILLVDS

10.2

137

263

292

±0.025

3.465

1.890

3.465

3.465

1.890